TREA

Three dimensional structure memory

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Information

  • Patent Grant
  • 8907499
  • Patent Number
    8,907,499
  • Date Filed
    Friday, January 4, 2013
    12 years ago
  • Date Issued
    Tuesday, December 9, 2014
    10 years ago
Information
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention


The present invention relates to stacked integrated circuit memory.


2. State of the Art


Manufacturing methods for increasing the performance and decreasing the cost of electronic circuits, nearly without exception, are methods that increase the integration of the circuit and decrease its physical size per equivalent number of circuit devices such as transistors or capacitors. These methods have produced as of 1996 microprocessors capable of over 100 million operations per second that cost less than $1,000 and 64 Mbit DRAM circuits that access data in less than 50 ns and cost less than $50. The physical size of such circuits is less than 2 cm2. Such manufacturing methods support to a large degree the economic standard of living in the major industrialized countries and will most certainly continue to have significant consequences in the daily lives of people all over the world.


Circuit manufacturing methods take two primary forms: process integration and assembly integration. Historically the line between these two manufacturing disciplines has been clear, but recently with the rise in the use of MCMs (Multi-Chip Modules) and flip-chip die attach, this clear separation may soon disappear. (The predominate use of the term Integrated Circuit (IC) herein is in reference to an Integrated Circuit in singulated die form as sawed from a circuit substrate such as s semiconductor wafer versus, for example, an Integrated Circuit in packaged form.) The majority of ICs when in initial die form are presently individually packaged, however, there is an increasing use of MCMs. Die in an MCM are normally attached to a circuit substrate in a planar fashion with conventional IC die I/O interconnect bonding methods such as wire bonding, DCA (Direct Chip Attach) or FCA (Flip-Chip Attach).


Integrated circuit memory such as DRAM, SRAM, flash EPROM, EEPROM, Ferroelectric, GMR (Giant MagnetoResistance), etc. have the common architectural or structural characteristic of being monolithic with the control circuitry integrated on the same die with the memory array circuitry. This established (standard or conventional) architecture or circuit layout structure creates a design trade-off constraint between control circuitry and memory array circuitry for large memory circuits. Reductions in the fabrication geometries of memory cell circuitry has resulted in denser and denser memory ICs, however, these higher memory densities have resulted in more sophisticated control circuitry at the expense of increased area of the IC. Increased IC area means at least higher fabrication costs per IC (fewer ICs per wafer) and lower IC yields (fewer working ICs per wafer), and in the worst case, an IC design that cannot be manufactured due to its non-competitive cost or unreliable operation.


As memory density increases and the individual memory cell size decreases more control circuitry is required. The control circuitry of a memory IC as a percentage of IC area in some cases such as DRAMs approaches or exceeds 40%. One portion of the control circuitry is the sense amp which senses the state, potential or charge of a memory cell in the memory array circuitry during a read operation. The sense amp circuitry is a significant portion of the control circuitry and it is a constant challenge to the IC memory designer to improve sense amp sensitivity in order to sense ever smaller memory cells while preventing the area used by the sense amp from becoming too large.


If this design constraint or trade-off between control and memory circuits did not exist, the control circuitry could be made to perform numerous additional functions, such as sensing multiple storage states per memory cell, faster memory access through larger more sensitive sense amps, caching, refresh, address translation, etc. But this trade-off is the physical and economic reality for memory ICs as they are presently made by all manufacturers.


The capacity of DRAM circuits increases by a factor of four from one generation to the next; e.g. 1 bit, 4 bit, 16 Mbit and 64 Mbit DRAMs. This four times increase in circuit memory capacity per generation has resulted in larger and larger DRAM circuit areas. Upon introduction of a new DRAM generation the circuit yields are too low and, therefore, not cost effective for high volume manufacture. It is normally several years between the date prototype samples of a new DRAM generation are shown and the date such circuits are in volume production.


Assembling die in a stacked or three dimensional (3D) manner is disclosed in U.S. Pat. No. 5,354,695 of the present inventor, incorporated herein by reference. Furthermore, assembling die in a 3D manner has been attempted with regard to memory. Texas Instruments of Dallas Tex., Irvine Sensors of Costa Mesa Calif. and Cubic Memory Corporation of Scotts Valley Calif. have all attempted to produce stacked or 3D DRAM products. In all three cases, conventional DRAM circuits in die form were stacked and the interconnect between each DRAM in the stack was formed along the outside surface of the circuit stack. These products have been available for the past several years and have proved to be too expensive for commercial applications, but have found some use in space and military applications due to their small physical size or footprint.


The DRAM circuit type is referred to and often used as an example in this specification, however, this invention is clearly not limited to the DRAM type of circuit. Undoubtedly memory cell types such as EEPROMs (Electrically Erasable Programmable Read Only Memories), flash EPROM, Ferroelectric, GMR Giant Magneto Resistance or combinations (intra or inter) of such memory cells can also be used with the present Three Dimensional Structure (3DS) methods to form 3DS memory devices.


The present invention furthers, among others, the following objectives:


1. Several-fold lower fabrication cost per megabyte of memory than circuits conventionally made solely with monolithic circuit integration methods.


2. Several-fold higher performance than conventionally made memory circuits.


3. Many-fold higher memory density per IC than conventionally made memory circuits.


4. Greater designer control of circuit area size, and therefore, cost.


5. Circuit dynamic and static self-test of memory cells by an internal controller.


6. Dynamic error recovery and reconfiguration.


7. Multi-level storage per memory cell.


8. Virtual address translation, address windowing, various address functions such as indirect addressing or content addressing, analog circuit functions and various graphics acceleration and microprocessor functions.


SUMMARY OF THE INVENTION

The present 3DS memory technology is a stacked or 3D circuit assembly technology. Features include:


1. Physical separation of the memory circuits and the control logic circuit onto different layers;


2. The use of one control logic circuit for several memory circuits;


3 Thinning of the memory circuit to less than about 50 microns in thickness forming a substantially flexible substrate with planar processed bond surfaces and bonding the circuit to the circuit stack while still in wafer substrate form; and


4. The use of fine-grain high density inter layer vertical bus connections.


The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. Using the DRAM circuit as an example, a 64 Mbit DRAM made with a 0.25 microns process could have a die size of 84 mm2, a memory area to die size ratio of 40% and a access time of about 50 ns for 8 Mbytes of storage; a 3DS DRAM IC made with the same 0.25 microns process would have a die size of 18.6 mm2, use 17 DRAM array circuit layers, a memory area to die size ratio of 94.4% and an expected access time of less than 10 ns for 64 Mbytes of storage. The 3DS DRAM IC manufacturing method represents a scalable, many-fold reduction in the cost per megabyte versus that of conventional DRAM IC manufacturing methods. In other words, the 3DS memory manufacturing method represents, at the infrastructure level, a fundamental cost savings that is independent of the process fabrication technology used.





BRIEF DESCRIPTION OF THE DRAWING

The present invention may be further understood from the following description in conjunction with the appended drawing. In the drawing:



FIG. 1
a is a pictorial view of a 3DS DRAM IC manufactured with Method A or Method B and demonstrating the same physical appearance of I/O bond pads as a conventional IC die;



FIG. 1
b is a cross-sectional view of a 3DS memory IC showing the metal bonding interconnect between several thinned circuit layers;



FIG. 1
c is a pictorial view of a 3DS DRAM IC stack bonded and interconnected face-down onto a larger conventional IC or another 3DS IC;



FIG. 2
a is a diagram showing the physical layout of a 3DS DRAM array circuit block with one data-line set of bus lines, i.e. one port;



FIG. 2
b is a diagram showing the physical layout of a 3DS DRAM array circuit block with two sets of data-line bus lines, i.e. two ports;



FIG. 2
c is a diagram showing the physical layout of a portion of an exemplary memory controller circuit;



FIG. 3 is a diagram showing the physical layout of a 3DS DRAM array circuit showing partitions for sixty-four (64) 3DS DRAM array blocks;



FIG. 4 is a cross-sectional view of a generic 3DS vertical interconnection or feed-through in a thinned substrate;



FIG. 5 is a diagram showing the layout of a 3DS memory multiplexer for down-selecting gate-line read or write selection.





DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1a and FIG. 1b, the 3DS (Three Dimensional Structure) memory device 100 is a stack of integrated circuit layers with fine-grain vertical interconnect between all circuit layers. The term fine-grain inter-layer vertical interconnect is used to mean electrical conductors that pass through a circuit layer with or without an intervening device element and have a pitch of nominally less than 100 microns and more typically less than 10 microns, but not limited to a pitch of less than 2 microns, as best seen in FIG. 2a and FIG. 2b. The fine-grain inter-layer vertical interconnect also functions to bond together the various circuit layers. As shown in FIG. 1b, although the bond and interconnect layers 105a, 105b, etc., are preferably metal, other material may also be used as described more fully hereinafter.


The pattern 107a, 107b, etc. in the bond and interconnect layers 105a, 105b, etc. defines the vertical interconnect contacts between the integrated circuit layers and serves to electrically isolate these contacts from each other and the remaining bond material; this pattern takes the form of either voids or dielectric filled spaces in the bond layers.


The 3DS memory stack is typically organized as a controller circuit 101 and some number of memory array circuit layers 103, typically between nine (9) and thirty-two (32), but there is no particular limit to the number of layers. The controller circuit is of nominal circuit thickness (typically 0.5 mm or greater), but each memory array circuit layer is a thinned and substantially flexible circuit with net low stress, less than 50 microns and typically less than 10 microns in thickness. Conventional I/O bond pads are formed on a final memory array circuit layer for use with conventional packaging methods. Other metal patterns may be used such as insertion interconnection (disclosed in U.S. Pat. Nos. 5,323,035 and 5,453,404 of the present inventor), DCA (Direct Chip Attach) or FCA (Flip-Chip Attach) methods.


Further, the fine grain inter-layer vertical interconnect can be used for direct singulated die bonding between a 3DS memory die and a conventional die (wherein the conventional die could be the controller circuit as shown in FIG. 1c) or a 3DS memory die and another 3DS memory die; it should be assumed that the areas (sizes) of the respective dice to be bonded together can vary and need not be the same. Referring more particularly to FIG. 1c, a 3DS DRAM IC stack 100 is bonded and interconnected face-down onto a larger conventional IC or another 3DS IC 107. Optionally the 3DS stack 100 can be composed of only DRAM array circuits with the DRAM controller circuitry as part of the larger die. If the DRAM controller circuitry is part of the larger die, then fine-grain vertical bus interconnect would be required (at the face 109 of the 3DS DRAM IC stack 100) to connect the 3DS DRAM array circuit to the DRAM controller, otherwise larger grain conventional interconnection could be incorporated (patterned) into the planarized bond layer.


As shown in FIG. 3, each memory array circuit layer includes a memory array circuit 300 composed of memory array blocks 301 (nominally less than 5 mm2 in area) and each block is composed of memory cells (in much the same manner as the cell array of a DRAM or EEPROM circuit), busing electrodes, and—at the option of the designer—enabling gates for selection of specific rows or columns of the memory array. The controller circuit is composed of sense amps, address, control and drive logic that would normally be found at the periphery of a typical memory circuit of monolithic design such as in a conventional DRAM.


Fine-grain busing vertically connects the controller independently to each memory array layer such that the controller can provide drive (power) or enable signals to any one layer without affecting the state of any of the other layers. This allows the controller to test, read or write independently each of the memory circuit layers.



FIG. 2
a and FIG. 2b show examples of layouts of possible blocks of a memory array such as the block 301 of FIG. 3. Although only a portion of the block is shown, in the illustrated embodiment, the blocks exhibit bilateral symmetry such that the layout of the complete block may be ascertained from the illustrated portion. Abbreviations “T”, “L”, and “TL” are used following various reference numerals to indicate “Top”, “Left” and “Top-Left,” respectively, implying corresponding elements not shown in the figure. Referring to FIG. 2a, a core portion 200 of the block is composed of a “sea” of memory cells. Logically, the aggregation of memory cells may be subdivided into “macrocells” 201 each containing some number of memory cells, e.g. an 8×8 array of 64 memory cells. At the periphery of the core is formed fine-grain vertical interconnect comprising inter-layer bond and bus contact metallizations 400, described in greater detail hereinafter with reference to FIG. 4. The fine-grain vertical interconnect includes I/O power and ground bus lines 203TL, memory circuit layer selects 205T, memory macro cell column selects 207T, data lines 209L, and gate-line multiplexer (“mux”) selects 209TL. Gate-line multiplexers 211T are, in the illustrated embodiment, 4:1 multiplexers used to select one of four columns within an eight-wide memory macro cell column. Corresponding bottom-side 4:1 multiplexers combine with the topside multiplexers 211T to form equivalent 8:1 multiplexers for selecting a single gate-line from an eight-gate-line-wide memory macro cell column.


One implementation of a 4:1 gate-line bus muliplexer 500 is shown in FIG. 5. Gate-line enables 209TL′ (formed in a Metal-1 layer, for example) control transistors 501a through 501d, respectively. Coupled to the transistors are respective gate lines 503a through 503d. Also partly visible are gate-lines 505a through 505d which are coupled to a corresponding 4:1 multiplexer (not shown). When one of the gate-line enables is active, the corresponding gate-line is coupled to an output line 507 of the multiplexer (formed in a Metal-2 layer, for example). The output line is connected to one or more vertical bus connects through a line 509 (formed in a Metal-3 layer and corresponding to metal contact 400 of vertical bus interconnect, for example) and tungsten plugs 511 and 513. The tungsten plug 513 joins the line 509 to a vertical interconnect (not shown).


Referring again to FIG. 2a, in the case of a memory circuit layer, the layer may also include output line enables (gates) from controller layer enable signals 205T, for which I/O enables (gates) 213 may be provided.


Note that at the memory layer level, each memory block 301 is electrically isolated from every other memory block 301. Accordingly, the yield probability for each memory block is independent.


Additional read/write ports can be added as can additional gate-line vertical interconnections; additional vertical interconnection can be used in a redundant manner to improve vertical interconnect yield. The 3DS memory circuit can be designed to have one or more data read and write bus port interconnections. Referring to FIG. 2b, a memory block 301′ is shown as having a port P0, (209L) and a further port P1 (209L′). The only limitation on the number of vertical interconnections is the overhead such vertical interconnections impose on the cost of the circuit. The fine-grain vertical interconnect method allows thousands of interconnects per block at an increase in die area of only a few percent.


As an example, the overhead of the vertical interconnect shown in FIG. 2b for a DRAM memory block of 4 bits with two read/write ports and implemented in 0.35 microns or 0.15 microns design rules consists of approximately 5,000 connections and is less than 6% of the total area of the memory array block. Therefore, the vertical interconnect overhead for each memory array circuit layer in the 3DS DRAM circuit is less than 6%. This is significantly less than that presently experienced in monolithic DRAM circuit designs where the percentage of non-memory cell area can exceed 40%. In a completed 3DS DRAM circuit the percentage of non-memory cell area is typically less than 10% of the total area of all circuits in the stacked structure.


The 3DS memory device decouples control functions that normally would be found adjacent the memory cells of monolithic memory circuits and segregates them to the controller circuit. The control functions, rather than occurring on each memory array layer as in conventional memory ICs, occur only once in the controller circuit. This creates an economy by which several memory array layers share the same controller logic, and therefore, lowers the net cost per memory cell by as much as a factor of two versus conventional memory design.


The segregation of the control functions to a separate controller circuit allows more area for such functions (i.e., an area equal to the area one or several of the memory array blocks). This physical segregation by function also allows fabrication process segregation of the two very different fabrication technologies used for the control logic and the memory array, again realizing additional fabrication cost savings versus the more complicated combined logic/memory fabrication process used for conventional memory. The memory array can also be fabricated in a process technology without consideration of the process requirements of control logic functions. This results in the ability to design higher performance controller functions at lower cost than is the case with present memory circuits. Furthermore, the memory array circuit can also be fabricated with fewer process steps and nominally reduce memory circuit fabrication costs by 30% to 40% (e.g., in the case of a DRAM array, the process technology can be limited to NMOS or PMOS transistors versus CMOS).


Hence, although bonding of sufficiently planar surfaces of a memory controller substrate and a memory array substrate using thermal diffusion metal bonding is preferred, in the broader aspects of the present invention, the invention contemplates bonding of separate memory controller and memory array substrates by any of various conventional surface bonding methods, such as anisotropically conductive epoxy adhesive, to form interconnects between the two to provide random access data storage.


Referring to FIG. 2c, the layout of a portion of an exemplary memory controller circuit is shown. The inter-layer bond and bus contact metallization has the same pattern as previously described in relation to FIG. 2a. Instead of a sea of memory cells, however, there is provided memory controller circuitry including, for example, sense amps and data line buffers 215. Because of the increased availability of die area, multi-level logic may be provided in conjunction with the sense amps and data line buffers 215. Also shown are address decode, gate-line and DRAM layer select logic 217, refresh and self-test logic 219, ECC logic 221, windowing logic 223, etc. Note that self-test logic, ECC logic, and windowing logic are provided in addition to functions normally found within a DRAM memory controller circuit. Depending on die size or the number of controller circuit layers used, any of numerous other functions may also be provided including, for example, virtual memory management, address functions such as indirect addressing or content addressing, data compression, data decompression, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management, database processing, graphics acceleration functions, microprocessor functions (including adding a microprocessor substrate), etc.


The size of the 3DS memory circuit die is not dependent on the present constraint of containing the necessary number of memory cells and control function logic on one monolithic layer. This allows the circuit designer to reduce the 3DS circuit die size or choose a die size that is more optimal for the yield of the circuit. 3DSmemory circuit die size is primarily a function of the size and number of memory array blocks and the number of memory array layers used to fabricate the final 3DSmemory circuit. (The yield of a nineteen (19) layer, 0.25 microns process 3DS DRAM memory circuit may be shown to be greater than 90% as described below.) This advantage of selecting the 3DS circuit die size enables an earlier first production use of a more advanced process technology than would normally be possible for conventional monolithic circuit designs. This, of course, implies additional cost reductions and greater performance over the conventional memory circuits.


3DS Memory Device Fabrication Methods


There are two principal fabrication methods for 3DS memory circuits. The two 3DS memory fabrication methods, however, have a common objective which is the thermal diffusion metal bonding (also referred to as thermal compression bonding) of a number of circuit substrates onto a rigid supporting or common substrate which itself may optionally also be a circuit component layer.


The supporting or common substrate can be a standard semiconductor wafer, a quartz wafer or a substrate of any material composition that is compatible with the processing steps of the 3DS circuit, the operation of the circuit and the processing equipment used. The size and shape of the supporting substrate is a choice that best optimizes available manufacturing equipment and methods. Circuit substrates are bonded to the supporting substrate and then thinned through various methods. Circuit substrates may be formed on standard single crystal semiconductor substrates or as polysilicon circuits formed on an appropriate substrate such as silicon or quartz. Polysilicon transistor circuits have the important cost saving option of incorporating a parting layer (film) that allows the substrate upon which the polysilicon circuits are formed to be released and reused. Polysilicon transistor or TFTs (Thin Film Transistor) devices are widely used, and need not be made solely from silicon.


The various circuit layers of the 3DS memory circuit are bonded together by use of thermal diffusion of two metal surfaces, typically aluminum. The surface of the circuits to be bonded are smooth and sufficiently planar as is the case with the surface of an unprocessed semiconductor wafer or a processed semiconductor wafer that has been planarized with the CMP (Chemical Mechanical Processing) method with a surface planarity of less than 1 micron and preferably less than 1,000 angstrom over at least the area of the surface of the circuit (formed on the substrate) to be bonded. The metal bonding material on the surfaces of the circuits to be bonded are patterned to be mirror images of each other and to define the various vertical interconnect contacts as indicated in FIG. 2a, FIG. 2b, FIG. 2c and FIG. 5. The step of bonding two circuit substrates results in simultaneously forming the vertical interconnection between the two respective circuit layers or substrates.


The thermal diffusion bonding of the circuit layers takes place preferably in an equipment chamber with controlled pressure and atmospheric components such as N2 with little H2O and O2 content. The bonding equipment aligns the patterns of the substrates to be bonded, presses them together with a set of programmed pressures and at one or more temperatures for a period of time as required by the type of metal used as the bonding material. The thickness of the bonding material is nominally in a range of 500 angstrom to 15,000 angstrom or greater with a preferred thickness of 1,500 angstrom. The initial bonding of the substrates is preferably done at lower than standard pressure such as a negative pressure between 1 torr and 740 torr depending on the design of the bond pattern. This can leave an interior negative pressure between the bonding surfaces once external atmospheric pressure is returned which further assists in the formation of the bond and enhances the reliability of the bond.


The preferred bonding material is pure aluminum or an alloy of aluminum, but it is not limited to aluminum and may include, for example, such metals as Sn, Ti, In, Pb, Zn, Ni, Cu, Pt, Au or alloys of such metals that provide acceptable surface bond diffusion capabilities at acceptable temperatures and forming periods. The bonding material is not limited to metal, and could be a combination of bonding materials, such as highly conductive polysilicon, some of which are non-conducting such as silicon dioxide, and the foregoing exemplary types of bond material choices should not be considered to be limitations on how the circuit layers can be bonded.


In the case where metal bond materials form a native surface oxide that either inhibits the forming of a satisfactory bond or may increase the resistance in the vertical interconnections formed by the bond, the oxide should be removed. The bonding equipment provides an oxide reduction capability such that bonding surfaces of the bond material are rendered without native surface oxide. The methods of forming gas atmospheres for the reduction of surface oxides are well known, and there are other methods for removing the native oxide such as sputter etching, plasma etching or ion mill etching. In the case where aluminum is used as the bonding material, it is preferred that the thin native aluminum oxide film of approximately 40 angstrom on the bonding surfaces be removed prior to bonding.


The thinned (substantially flexible) substrate circuit layers of the 3DS memory circuit are typically memory array circuits, however, the thinned substrate circuit layers are not limited to memory circuits. Other circuit layer types can be controller circuits, non-volatile memory such as EEPROM, additional logic circuitry including microprocessor logic and application specific logic functions such as those that support graphic or database processing, etc. The selection of such circuit layer types follows from the functional requirements of the design of the circuit and is not limited by the 3DS memory fabrication process.


The thinned (substantially flexible) substrate circuit layers are preferably made with dielectrics in low stress (less than 5×108 dynes/cm2) such as low stress silicon dioxide and silicon nitride dielectrics as opposed to the more commonly used higher stress dielectrics of silicon oxide and silicon nitride used in conventional memory circuit fabrication. Such low stress dielectrics are discussed at length in U.S. Pat. No. 5,354,695 of the present inventor, incorporated herein by reference. The use of dielectrics with conventional stress levels could be used in the assembly of a 3DS DRAM circuit, however, if more than a few layers comprise the stacked assembly, each layer in the assembly will have to be stress balanced so that the net stress of the deposited films of a layer is less than 5×108 dynes/cm2. The use of intrinsically low stress deposited films is the preferred method of fabrication versus the use of the method where the stress of individually deposited films are not equal but are deposited to create a net balanced lower stress.


Method A, 3DS Memory Device Fabrication Sequence


This fabrication sequence assumes that several circuit layers will be bonded to a common or support substrate and subsequently thinned in place. An example of a resulting 3DS memory circuit is shown in FIG. 1a.


1. Align and bond to the common substrate the topside of a second circuit substrate.


2A. Grind the backside or exposed surface of the second circuit substrate to a thickness of less than 50 microns and then polish or smooth the surface. The thinned substrate is now a substantially flexible substrate.


Optionally an etch stop may be incorporated in the second substrate from less than a microns to several microns below the semiconductor surface prior to device fabrication. This etch stop can be an epitaxially formed film such as GeB (described in U.S. Pat. Nos. 5,354,695 and 5,323,035 of the present inventor, incorporated herein by reference) or a low density implanted layer of O2 or N2 to form a buried oxide or nitride barrier etch stop layer just below the device layer on the topside of the second substrate. After a preliminary grinding of a significant portion of the backside of the substrate, the remaining portion of the backside of the second substrate is then selectively etched in a chemical bath which stops on the surface of the eptiaxial or implanted layer. Subsequent polishing and RIE steps as necessary can then be used to complete the thinning of the second substrate.


Alternately, a parting layer such as H2 implanted into the topside surface of the second substrate prior to device fabrication can be used with a thermal step to crack off the majority of the backside of the second substrate, allowing its reuse.


2B. The second substrate may alternatively be a circuit formed of polysilicon transistors or TFTs over a parting layer such as aluminum, titanium, AlAs, KBr, etc. which can be activated by a specific chemical release agent. The backside of the second substrate is then removed upon activating (dissolving) the release layer and followed as needed by interconnect semiconductor processing steps.


3. Process the thinned backside of the second substrate to form vertical interconnections such as that shown in FIG. 4 with the bonded surface side of the second substrate. The backside processing typically comprises conventional semiconductor processing steps of dielectric and metal deposition, lithography and RIE, the order of which can vary to a great degree. The completion of the backside processing will also result in a patterned metal layer that is similar to the topside bond material pattern to facilitate the subsequent bonding of an additional circuit substrate, a terminal pattern such as a conventional I/O IC bond pad (wire bonding) pattern, a pattern for thermal diffusion bonding of the 3DS memory circuit to another die (either another 3DS circuit or a conventional die), or a pattern for insertion interconnection, conventional DCA (Direct Chip Attach) or FCA (Flip-Chip Attach).


Referring more particularly to FIG. 4, during the fabrication of active circuit devices, an oxide mask 401 is thermally grown or deposited. Vertical bus contacts 403 are then formed, for example from highly-doped polysilicon coincident with a polysilicon gate forming step. Alternatively, contact 403 may be formed of metal. Conventional DRAM interconnect structures 410 are then formed using conventional processing. The DRAM interconnect may include an internal pad 405. The “DRAM processed” portion 420 of the wafer includes various dielectric and metal layers. A final passivation layer 407 is deposited, after which vias 409 are formed. Conventional CMP processing is then used to obtain a planar surface 411. Contacts 413 and bond surfaces not shown are then patterned in a top-most metal layer (e.g, Metal-3).


After bonding and thinning of the backside of the second substrate to about 1-8 microns of silicon (or other semiconductor) substrate 415, feed-throughs 417 are then formed in registration with the contacts 403. A passivation layer 419 and contacts 421 are then formed. The contacts 421 may be formed so as to form a mirror image of the contacts 413, allowing for the bonding of further wafers.


4. If another circuit layer is to be bonded to the 3DS circuit stack, steps 1-3 are repeated.


5A. The circuits of the finished 3DS memory substrate are then conventionally sawed into die (singulated), resulting in a circuit of the type shown in FIG. 1a, and packaged as would be the case with conventional integrated circuits.


5B. The circuits of the finished 3DS memory substrate are then conventionally sawed and then individually aligned and thermal diffusion bonded (metal pattern down) to the surface of a second (conventional IC) die or MCM substrate in a manner similar to that used in the bonding of the circuit substrates of step 1 above. (The conventional die or MCM substrate may have a larger area than the 3DS memory substrate and may include a graphics controller, video controller or microprocessor, such that the 3DS becomes embedded as part of another circuit.) This final bonding step typically incorporates a fine-grain interconnect between the 3DS memory circuit and the die or MCM substrate, but could also use a conventional interconnect pattern. Further, a 3DS memory circuit can be bonded face up to a conventional IC in die form or MCM substrate and wire bonding used to form conventional I/O interconnections.


Method B, 3DS Memory Device Fabrication Sequence


This fabrication sequence assumes that a circuit substrate will first be bonded to a transfer substrate, thinned and then bonded to a common substrate as a layer of the circuit stack. The transfer substrate is then released. This method has the advantage over Method A of allowing substrates to be thinned prior to being bonded to the final circuit stack and allows for simultaneous thinning and vertical interconnect processing of substrate circuit layers.


1. Bond to a transfer substrate a second circuit substrate using a release or parting layer. A transfer substrate may have high tolerance parallel surfaces (TTV or Total Thickness Variance of less than 1 micron) and may be perforated with an array of small holes to assist the parting process.


The parting layer can be a blanket deposition of a bonding metal. Precise alignment of the surfaces is not required.


2. Perform step 2A or 2B of Method A.


3. Process the backside of the second substrate to form interconnections with the bonded topside surface of the second substrate as shown in FIG. 4. The backside processing typically comprises conventional semiconductor processing steps of dielectric and metal deposition, lithography and RIE, the order of which can vary to great degree. The completion of the backside processing will also result in a patterned metal layer that is similar to the bond material pattern of the common substrate to facilitate the subsequent bonding of an additional circuit layer.


4. Bond the second circuit to a common or support substrate (3DS stack) and release the transfer substrate by activating the parting layer between it and the second circuit.


5. Process the now exposed topside of the second substrate to form interconnections for subsequent substrate bonding or a terminal pattern for conventional I/O bonding (wire bonding) pad pattern, a pattern for thermal diffusion bonding of the 3DS memory circuit to another die (either another 3DS circuit or a conventional die), or a pattern for conventional insertion interconnect, DCA (Direct Chip Attach) or FCA (Flip-Chip Attach). If another circuit layer is to be bonded to the 3DScircuit stack, steps 1 through 4 are repeated.


6. Perform step 5A or 5B of Method A.


3DS Memory Device Yield Enhancement Methods


The 3DS circuit may be considered a vertically assembled MCM (Multi-Chip Module) and as with an MCM the final yield is the product of the yield probabilities of each component circuit (layer) in the completed 3DS circuit. The 3DS circuit uses several yield enhancement methods that are synergistic in their combined usage within a single memory IC. The yield enhancement methods used in the 3DS memory circuit include small memory array block size, memory array block electrical isolation through physically unique or separate vertical bus interconnections, intra memory array block gate-line sparing, memory array layer sparing (inter-block gate-line sparing), controller sparing and ECC (Error Correcting Codes). The term sparing is used to mean substitution by a redundant element.


The selected size of the memory array block is the first component in the yield equation for the 3DS memory circuit. Each memory array block is individually (uniquely) accessed and powered by the controller circuit and is physically independent of each and every other memory array block including those on the same memory array layer in addition to those on a different memory array layer. The size of the memory array block is typically less than 5 mm2 and preferably less than 3 mm2, but is not limited to a specific size. The size of memory array block, the simplicity of its NMOS or PMOS fabrication process and its physical independence from each of the other memory array blocks, for nearly all production IC processes, provides a conservatively stated nominal yield of greater than 99.5%. This yield assumes that most point defects in the memory array block such as open or shorted interconnect lines or failed memory cells can be spared (replaced) from the intra-block or inter-block set of redundant gate-lines. Major defects in a memory array block which render the complete memory array block unusable result in the complete sparing of the block from a redundant memory array layer or the rejection of the 3DS circuit.


In the example of a 3DS DRAM circuit the yield of a stack of memory array blocks is calculated from the yield equation Ys=((1−(1−PY)2)n)b, where n is the number DRAM array layers, b is the number of blocks per DRAM array and Py is the effective yield (probability) of a DRAM array block less than 3 mm2 in area. Assuming a DRAM array block redundancy of 4% for gate-lines in the DRAM array block lines and one redundant DRAM array layer, and assuming further that the number of blocks per layer is 64, the number of memory array layers in the stack is 17 and the effective value for Py is 0.995, then the stack yield Ys for the complete memory array (including all memory array block stacks) is 97.47%.


The Ys memory array stack yield is then multiplied by the yield of the controller Yc. Assuming a die size of less than 50 mm2, a reasonable Yc for a controller fabricated from a 0.5 micron BiCMOS or mixed signal process would be between 65% and 85%, giving a net 3DS memory circuit yield of between 63.4% and 82.8%. If a redundant controller circuit layer is added to the 3DS memory stack, the yield probabilities would be between 85.7% and 95.2%.


The effective yield of a memory array block can be further increased by the optional use of ECC logic. ECC logic corrects data bit errors for some group size of data bits. The syndrome bits necessary for the operation of ECC logic would be stored on redundant gate-lines of any of the memory array layers in a vertically associated block stack. Further, if necessary, in order to accommodate the storage of ECC syndrome bits, additional memory array layers could be added to the circuit.


Advantageous 3DS Memory Device Controller Capabilities


As compared to a conventional memory circuit, the 3DS memory controller circuit can have various advantageous capabilities due the additional area available for controller circuitry and the availability of various mixed signal process fabrication technologies. Some of these capabilities are self-test of memory cells with dynamic gate-line address assignment, virtual address translation, programmable address windowing or mapping, ECC, data compression and multi-level storage.


Dynamic gate-line address assignment is the use of programmable gates to enable the layer and gate-line for a read/write operation. This allows the physical order of memory storage to be separate or different from the logical order of stored memory.


The testing of each generation of memory devices has resulted in significantly increased test costs. The 3DS memory controller reduces the cost of testing by incorporating sufficient control logic to perform an internal test (self-test) of the various memory array blocks. Circuit testing in the conventional ATE manner is required only for verification of controller circuit functions. The scope of the internal test is further extended to the programmable (dynamic) assignment of unique addresses corresponding to the various gate-lines of each memory array block on each layer. Self-test capability of the 3DS controller circuit can be used anytime during the life of the 3DS memory circuit as a diagnostic tool and as a means to increase circuit reliability by reconfiguring (sparing) the addresses of gate-lines that fail after the 3DS memory circuit is in use in a product.


ECC is a circuit capability that, if included in the controller circuit, can be enabled or disabled by a programming signal or made a dedicated function.


Data compression logic will allow the total amount of data that can be stored in the 3DS memory array to be increased. There are various generally known data compression methods available for this purpose.


Larger sense amps allow greater dynamic performance and enable higher speed read operations from the memory cells. Larger sense amps are expected to provide the capability to store more than one bit (multi-level storage) of information in each memory cell; this capability has already been demonstrated in non-volatile memory circuits such as flash EPROM. Multi-level storage has also been proposed for use in the 4 Gbit DRAM generation circuits.


It will be appreciated by those of ordinary skill in the art that the invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalents thereof are intended to be embraced therein.

Claims
  • 1. A thin and substantially flexible structure comprising: a thin, substantially flexible monocrystalline semiconductor layer of one piece; anda silicon-based dielectric layer formed on the thin semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile.
  • 2. The thin and substantially flexible structure of claim 1, further comprising: a vertical interconnect conductor extending vertically through the thin semiconductor layer; anda vertical silicon-based dielectric insulator extending vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile.
  • 3. The thin and substantially flexible structure of claim 2, wherein: the thin semiconductor layer comprises vertical holes etched therethrough; andthe vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer.
  • 4. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer is formed from a semiconductor wafer.
  • 5. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer has a thickness of 50 microns or less.
  • 6. The thin and substantially flexible structure of claim 4, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.
  • 7. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer is unitary.
  • 8. The thin and substantially flexible structure of claim 2, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.
  • 9. The thin and substantially flexible structure of claim 8, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.
  • 10. The thin and substantially flexible structure of claim 1, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.
  • 11. The thin and substantially flexible structure of claim 2, further comprising: a bottomside surface and a topside surface;a contact formed on the bottomside surface and electrically connected to the vertical interconnect conductor; andan interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the vertical interconnect.
  • 12. A thin and substantially flexible circuit comprising: a thin monocrystalline semiconductor layer of one piece;a silicon-based dielectric layer formed on the thin semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile; andcircuitry supported by the thin semiconductor layer and the dielectric layer defining an integrated circuit die having an area, wherein the thin semiconductor layer extends throughout a substantial portion of the area of the integrated circuit die.
  • 13. The thin and substantially flexible circuit of claim 12, comprising: a vertical interconnect conductor extending vertically through the thin semiconductor layer and coupled to said circuitry; anda vertical silicon-based dielectric insulator extending vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile.
  • 14. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer is formed from a semiconductor wafer.
  • 15. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer has a thickness of 50 microns or less.
  • 16. The thin and substantially flexible circuit of claim 14, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.
  • 17. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer is unitary.
  • 18. The thin and substantially flexible circuit of claim 13, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.
  • 19. The thin and substantially flexible circuit of claim 18, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.
  • 20. The thin and substantially flexible circuit of claim 12, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.
  • 21. The thin and substantially flexible circuit of claim 13, further comprising: a bottomside surface and a topside surface;a contact formed on the bottomside surface and electrically connected to the vertical interconnect conductor; andan interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the vertical interconnect.
  • 22. A structure comprising: a monocrystalline semiconductor layer of one piece; anda silicon-based dielectric layer formed on the semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile;wherein the semiconductor layer is capable of being thinned to obtain a thin and substantially flexible substrate.
  • 23. The structure of claim 22, comprising: a vertical interconnect conductor extending vertically through the thin semiconductor layer and coupled to said circuitry; anda vertical silicon-based dielectric insulator extending vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile.
  • 24. A thin and substantially flexible integrated circuit comprising: a thin, substantially flexible monocrystalline semiconductor layer of one piece comprising integrated circuit devices; anda silicon-based dielectric layer formed on the thin semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile.
  • 25. The structure of claim 23, wherein: the thin semiconductor layer comprises vertical holes etched therethrough; andthe vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer.
  • 26. The structure of claim 23, wherein the thin semiconductor layer comprises monocystalline silicon.
  • 27. The structure of claim 23, wherein the thin semiconductor layer is formed from a semiconductor wafer.
  • 28. The structure of claim 23, wherein the thin semiconductor layer has a thickness of 50 microns or less.
  • 29. The structure of claim 27, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.
  • 30. The structure of claim 23, wherein the thin semiconductor layer is unitary.
  • 31. The structure of claim 23, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.
  • 32. The structure of claim 31, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.
  • 33. The structure of claim 22, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.
  • 34. The structure of claim 23, further comprising: a bottomside surface and a topside surface;a contact formed on the bottomside surface and electrically connected to the vertical interconnect conductor; andan interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the vertical interconnect.
  • 35. The thin and substantially flexible integrated circuit of claim 24, wherein: the thin semiconductor layer comprises vertical holes etched therethrough; andvertical interconnect conductors and vertical silicon-based dielectric insulators are formed in the vertical holes of the thin semiconductor layer.
  • 36. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer comprises monocystalline silicon.
  • 37. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer is formed from a semiconductor wafer.
  • 38. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer has a thickness of 50 microns or less.
  • 39. The thin and substantially flexible integrated circuit of claim 37, wherein the semiconductor wafer comprises monocrystalline silicon, and the thin semiconductor layer comprises monocrystalline silicon formed from the semiconductor wafer.
  • 40. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer is unitary.
  • 41. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer extends from edge to edge of the dielectric layer.
  • 42. The thin and substantially flexible integrated circuit of claim 41, wherein the dielectric layer extends from edge to edge of the thin semiconductor layer.
  • 43. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer comprises a polished surface formed by removing semiconductor material during thinning of the thin semiconductor layer to expose a surface thereof and then polishing the exposed surface, wherein the thin semiconductor layer is substantially flexible based on being thinned and having the polished surface.
  • 44. The thin and substantially flexible integrated circuit of claim 24, further comprising: a bottomside surface and a topside surface;a contact formed on the bottomside surface and electrically connected to a vertical interconnect conductor; andan interconnect, contact or circuit formed on or near the topside surface and electrically connected to the vertical interconnect conductor;wherein the interconnect, contact or circuit is electrically connected to the contact on the bottomside surface via the interconnect.
  • 45. The thin and substantially flexible structure of claim 1, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.
  • 46. The thin and substantially flexible circuit of claim 12, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.
  • 47. The structure of claim 22, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.
  • 48. The thin and substantially flexible integrated circuit of claim 24, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.
  • 49. The thin and substantially flexible structure of claim 1, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 50. The thin and substantially flexible circuit of claim 12, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 51. The structure of claim 22, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 52. The thin and substantially flexible integrated circuit of claim 24, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 53. A thin and substantially flexible structure comprising: a thinned substantially flexible monocrystalline semiconductor layer of one piece formed from a semiconductor wafer; anda silicon-based dielectric layer formed on the thinned semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile.
  • 54. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer has a thickness of 50 microns or less.
  • 55. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer is made flexible by the combination of, first, removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.
  • 56. The thin and substantially flexible structure of claim 53, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the thin semiconductor layer.
  • 57. The thin and substantially flexible structure of claim 53, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprises a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 58. The thin and substantially flexible structure of claim 53, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprises a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 59. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 60. The thin and substantially flexible structure of claim 59, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
  • 61. The thin and substantially flexible structure of claim 53, comprising at least one conductive interconnection that passes vertically through the thinned semiconductor layer and is insulated from the thinned semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×108 dynes/cm2 tensile.
  • 62. The thin and substantially flexible structure of claim 53, comprising a logic layer for performing at least one of the following functions: microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  • 63. A thin and substantially flexible circuit comprising: a thinned monocrystalline semiconductor layer of one piece formed from a semiconductor wafer;a silicon-based dielectric layer formed on the thinned semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile; andcircuitry supported by the thinned semiconductor layer and the dielectric layer defining an integrated circuit die having an area, wherein the thinned semiconductor layer extends throughout a substantial portion of the area of the integrated circuit die.
  • 64. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer has a thickness of 50 microns or less.
  • 65. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer is made flexible by the combination of first removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.
  • 66. The thin and substantially flexible circuit of claim 63, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the thinned semiconductor layer.
  • 67. The thin and substantially flexible circuit of claim 63, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 68. The thin and substantially flexible circuit of claim 63, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 69. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 70. The thin and substantially flexible circuit of claim 69, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
  • 71. The thin and substantially flexible circuit of claim 63, comprising at least one conductive interconnection that passes vertically through the thinned semiconductor layer and is insulated from the thinned semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×108 dynes/cm2 tensile.
  • 72. The thin and substantially flexible circuit of claim 63, comprising a logic layer for performing at least one of the following functions: microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  • 73. A structure comprising: a monocrystalline semiconductor layer of one piece formed from a semiconductor wafer; anda silicon-based dielectric layer formed on the semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile;wherein the monocrystalline semiconductor layer is capable of being thinned to obtain a thinned and substantially flexible substrate.
  • 74. The structure of claim 73, wherein the monocrystalline semiconductor layer has a thickness of 50 microns or less.
  • 75. The structure of claim 73, wherein the monocrystalline semiconductor layer is made flexible by the combination of first removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polished to form a polished surface.
  • 76. The structure of claim 73, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the monocrystalline semiconductor layer.
  • 77. The structure of claim 73, further comprising a plurality of integrated circuits in a stacked relationship to the monocrystalline semiconductor layer, wherein each of said plurality of integrated circuits comprises a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 78. The structure of claim 73, further comprising a plurality of integrated circuits in a stacked relationship to the monocrystalline semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 79. The structure of claim 73, wherein the monocrystalline semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 80. The structure of claim 79, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
  • 81. The structure of claim 73, comprising at least one conductive interconnection that passes vertically through the monocrystalline semiconductor layer and is insulated from the monocrystalline semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×108 dynes/cm2 tensile.
  • 82. The structure of claim 73, comprising a logic layer for performing at least one of the following functions: microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  • 83. A thin and substantially flexible integrated circuit comprising: a thinned, substantially flexible monocrystalline semiconductor layer of one piece formed from a semiconductor wafer and comprising integrated circuit devices; anda silicon-based dielectric layer formed on the monocrystalline semiconductor layer and having a stress of less than 5×108 dynes/cm2 tensile.
  • 84. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer has a thickness of 50 microns or less.
  • 85. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer is made flexible by the combination of first removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.
  • 86. The thin and substantially flexible integrated circuit of claim 83, further comprising a plurality of memory cell layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said memory cell layers in a stacked relationship to the thinned semiconductor layer.
  • 87. The thin and substantially flexible integrated circuit of claim 83, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising an array of memory cells and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 88. The thin and substantially flexible integrated circuit of claim 83, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 89. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 90. The thin and substantially flexible integrated circuit of claim 89, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
  • 91. The thin and substantially flexible integrated circuit of claim 83, comprising at least one conductive interconnection that passes vertically through the thinned semiconductor layer and is insulated from the thinned semiconductor layer by a low stress silicon-based dielectric material having a stress of less than 5×108 dynes/cm2 tensile.
  • 92. The thin and substantially flexible integrated circuit of claim 83, comprising a logic layer for performing at least one of the following functions: microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  • 93. A thin and substantially flexible structure comprising: a thinned substantially flexible monocrystalline semiconductor layer of one piece formed from a semiconductor wafer;a plurality of deposited polysilicon layers; anda plurality of silicon-based dielectric layers formed on the thinned semiconductor layer and polysilicon layers and having a stress of less than 5×108 dynes/cm2 tensile.
  • 94. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer has a thickness of 50 microns or less.
  • 95. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer is made flexible by the combination of, first, removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.
  • 96. The thin and substantially flexible structure of claim 93, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said polysilicon layers in a stacked relationship to the thinned semiconductor layer.
  • 97. The thin and substantially flexible structure of claim 93, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 98. The thin and substantially flexible structure of claim 93, further comprising a plurality of integrated circuits in a stacked relationship to the thinned semiconductor layer, wherein each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 99. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 100. The thin and substantially flexible structure of claim 99, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
  • 101. The thin and substantially flexible structure of claim 93, comprising at least one conductive interconnection that passes vertically through at least one of the polysilicon layers and is insulated from the at least one of the polysilicon layers by a low stress silicon-based dielectric material having a stress of less than 5×108 dynes/cm2 tensile.
  • 102. The thin and substantially flexible structure of claim 93, comprising a logic layer for performing at least one of the following functions: microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  • 103. A structure comprising: a monocrystalline semiconductor layer of one piece formed from a semiconductor wafer;a plurality of memory layers; anda plurality of silicon-based dielectric layers formed on the semiconductor layer and memory layers and having a stress of less than 5×108 dynes/cm2 tensile;wherein the monocrystalline semiconductor layer is capable of being thinned to obtain a thinned and substantially flexible substrate.
  • 104. The structure of claim 103, wherein the monocrystalline semiconductor layer has a thickness of 50 microns or less.
  • 105. The structure of claim 103, wherein the monocrystalline semiconductor layer is made flexible by the combination of, first, removal of semiconductor material from a surface by at least one of abrasion, etching and parting, and second, polishing to form a polished surface.
  • 106. The structure of claim 103, further comprising at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile deposited on each of said memory layers in a stacked relationship to the monocrystalline semiconductor layer.
  • 107. The structure of claim 103, further comprising a plurality of integrated circuits in a stacked relationship to the monocrystalline semiconductor layer, wherein each of said plurality of integrated circuits comprising one of the memory layers and at least one low stress silicon-based dielectric layer with a stress of less than 5×108 dynes/cm2 tensile.
  • 108. The structure of claim 103, wherein the monocrstalline semiconductor layer is one of a logic layer and a memory layer, and further comprising another of a logic layer and a memory layer such that at least one memory layer is in a stacked relationship with a logic layer, wherein the logic layer and the at least one memory layer form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of circuit blocks stacks each with vertically interconnected circuit blocks, wherein a plurality of said circuit block stacks can independently perform memory operations.
  • 109. The structure of claim 108, wherein one of the logic layer and the at least one memory layer is formed using a different process technology than another of the logic layer and the at least one memory layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
  • 110. The structure of claim 103, comprising at least one conductive interconnection that passes vertically through at least one of the memory layers and is insulated from the at least one of the memory layers by a low stress silicon-based dielectric material having a stress of less than 5×108 dynes/cm2 tensile.
  • 111. The structure of claim 103, comprising a logic layer for performing at least one of the following functions: microprocessor instruction set, graphics instruction set, virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.
  • 112. The thin and substantially flexible structure of claim 1, wherein the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 113. The thin and substantially flexible circuit of claim 12, wherein the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 114. The structure of claim 22, wherein the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 115. The thin and substantially flexible integrated circuit of claim 24, wherein the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 116. The thin and substantially flexible structure of claim 53, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 117. The thin and substantially flexible circuit of claim 63, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 118. The structure of claim 73, wherein the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 119. The thin and substantially flexible integrated circuit of claim 83, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 120. The thin and substantially flexible structure of claim 93, wherein the thinned semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 121. The structure of claim 103, wherein the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 122. The thin and substantially flexible structure of claim 1, wherein at least three of: a vertical interconnect conductor extends vertically through the thin semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the thin semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer; the thin semiconductor layer is formed from a semiconductor wafer; the thin substrate has a thickness of 50 microns; the thin semiconductor layer is unitary; the thin semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the thin semiconductor layer; the thin semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 123. The thin and substantially flexible circuit of claim 12, wherein at least three of: a vertical interconnect conductor extends vertically through the thin semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the thin semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer; the thin semiconductor layer is formed from a semiconductor wafer; the thin substrate has a thickness of 50 microns or less; the thin semiconductor layer is unitary; the thin semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the thin semiconductor layer; the thin semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 124. The structure of claim 22, wherein at least three of: a vertical interconnect conductor extends vertically through the monocrystalline semiconductor layer, and a vertical dielectric insulator vertical silicon-based dielectric insulator extends vertically through the monocrystalline semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the monocrystalline semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the monocrystalline semiconductor layer; the monocrystalline semiconductor layer is formed from a semiconductor wafer; the monocrystalline substrate has a thickness of 50 microns or less; the monocrystalline semiconductor layer is unitary; the monocrystalline semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the monocrystalline semiconductor layer; the monocrystalline semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 125. The thin and substantially flexible integrated circuit of claim 24, wherein at least three of: a vertical interconnect conductor extends vertically through the thin semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thin semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the thin semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer; the thin semiconductor layer is formed from a semiconductor wafer; the thin substrate has a thickness of 50 microns or less; the thin semiconductor layer is unitary; the thin semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the thin semiconductor layer; the thin semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the thin semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 126. The thin and substantially flexible structure of claim 53, wherein at least three of: a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical dielectric insulator vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer; the thinned semiconductor layer is formed from a semiconductor wafer; the thinned substrate has a thickness of 50 microns or less; the thinned semiconductor layer is unitary; the thinned semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the thinned semiconductor layer; the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 127. The thin and substantially flexible circuit of claim 63, wherein at least three of: a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer; the thinned semiconductor layer is formed from a semiconductor wafer; the thinned substrate has a thickness of 50 microns or less; the thinned semiconductor layer is unitary; the thinned semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the thinned semiconductor layer; the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 128. The structure of claim 73, wherein at least three of: a vertical interconnect conductor extends vertically through the monocrystalline semiconductor layer, and a vertical dielectric insulator vertical silicon-based dielectric insulator extends vertically through the monocrystalline semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the monocrystalline semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the monocrystalline semiconductor layer; the monocrystalline semiconductor layer is formed from a semiconductor wafer; the monocrystalline substrate has a thickness of 50 microns or less; the monocrystalline semiconductor layer is unitary; the monocrystalline semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the monocrystalline semiconductor layer; the monocrystalline semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 129. The thin and substantially flexible integrated circuit of claim 83, wherein at least three of: a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer; the thinned semiconductor layer is formed from a semiconductor wafer; the thinned substrate has a thickness of 50 microns or less; the thinned semiconductor layer is unitary; the thinned semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the thinned semiconductor layer; the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 130. The thin and substantially flexible structure of claim 93, wherein at least three of: a vertical interconnect conductor extends vertically through the thinned semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the thinned semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the thinned semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thinned semiconductor layer; the thinned semiconductor layer is formed from a semiconductor wafer; the thinned substrate has a thickness of 50 microns or less; the thinned semiconductor layer is unitary; the thinned semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the thinned semiconductor layer; the thinned semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 131. The structure of claim 103, wherein at least three of: a vertical interconnect conductor extends vertically through the monocrystalline semiconductor layer, and a vertical silicon-based dielectric insulator extends vertically through the monocrystalline semiconductor layer and around the interconnect conductor and having a stress of less than 5×108 dynes/cm2 tensile; the monocrystalline semiconductor layer comprises vertical holes etched therethrough, and the vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the monocrystalline semiconductor layer; the monocrystalline semiconductor layer is formed from a semiconductor wafer; the monocrystalline substrate has a thickness of 50 microns or less; the monocrystalline semiconductor layer is unitary; the monocrystalline semiconductor layer extends from edge to edge of the dielectric layer; the dielectric layer extends from edge to edge of the monocrystalline semiconductor layer; the monocrystalline semiconductor layer comprises a polished surface formed by removing material during thinning of semiconductor material to expose a surface thereof and then polishing the exposed surface; the monocrystalline semiconductor layer comprises a frontside and a backside, further comprising integrated circuitry formed on the frontside and a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the backside.
  • 132. An integrated circuit comprising: at least one thin, substantially flexible integrated circuit layer comprising at least a thinned, substantially flexible monocrystalline semiconductor substrate of one piece having a backside; andat least one low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate, wherein the low-stress silicon-based dielectric layer has a stress of less than 5×108 dynes/cm2 tensile.
  • 133. The integrated circuit of claim 132, further comprising a polished or smoothed backside of the thinned, substantially flexible moncrystalline semiconductor substrate, wherein the polished or smoothed backside enables the thinned, substantially flexible monocrystalline semiconductor substrate to be substantially flexible, and the polished or smoothed backside reduces the vulnerability of the thinned, substantially flexible monocrystalline semiconductor substrate to fracture as a result of flexing.
  • 134. The integrated circuit of claim 133, wherein the integrated circuit structure is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, and the at least one low stress silicon-based dielectric layer.
  • 135. The integrated circuit of claim 133, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.
  • 136. The integrated circuit of claim 134, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.
  • 137. A substantially flexible integrated circuit comprising: at least one thin, substantially flexible integrated circuit layer comprising a thinned, substantially flexible monocrystalline semiconductor substrate of one piece having a backside, wherein the backside of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed, wherein the polished or smoothed backside enables the thinned, monocrystalline semiconductor substrate to be substantially flexible, and the polished or smoothed backside reduces the vulnerability of the thinned, substantially flexible monocrystalline semiconductor substrate to fracture as a result of flexing by reducing its vulnerability to fracture as a result of flexing; andat least one low-stress silicon-based dielectric layers formed above the thinned, substantially flexible monocrystalline semiconductor substrate, wherein the low-stress silicon-based dielectric layers have a stress of less than 5×108 dynes/cm2 tensile;wherein the substantially flexible integrated circuit is substantially flexible through combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, and the at least one low stress silicon-based dielectric layer.
  • 138. The substantially flexible stacked integrated circuit structure of claim 137, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×108 dynes/cm2 tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.
  • 139. The integrated circuit of claim 133, further comprising a plurality of memory circuit layers in a stacked relationship with the substantially flexible integrated circuit layer and vertical interconnections interconnecting said layers, wherein a plurality of vertical interconnections pass through at least one of the plurality of memory circuit layers, wherein at least one of the plurality of memory circuit layers comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×108 dynes/cm2 and an array of memory cells.
  • 140. The integrated circuit of claim 139, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate having the polished or smoothed backside, low stress of the at least one low stress silicon-based dielectric layer, and low stress of the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.
  • 141. The integrated circuit of claim 140, wherein a portion of the integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic block of the at least one thin, substantially flexible integrated circuit layer, a plurality of memory blocks one from each of the plurality of memory circuit layers and an array of vertical interconnections interconnecting the logic block and the plurality of memory blocks, wherein the array of vertical interconnections passes through at least one memory block of the plurality of memory blocks, wherein the at least one of the memory block stacks is able to perform memory operations through the array of vertical interconnections.
  • 142. The substantially flexible integrated circuit of claim 137, further comprising a plurality of memory circuit layers in a stacked relationship with the substantially flexible integrated circuit layer and vertical interconnections interconnecting said layers, wherein a plurality of vertical interconnections pass through at least one of the plurality of memory circuit layers, wherein at least one of the plurality of memory layers comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×108 dynes/cm2 and an array of memory cells.
  • 143. The substantially flexible integrated circuit of claim 142, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate having the polished or smoothed backside, low stress of the at least one low stress silicon-based dielectric layer, and low stress of the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.
  • 144. The substantially flexible integrated circuit of claim 143, wherein a portion of the substantially flexible integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic block of the at least one thin, substantially flexible integrated circuit layer, a plurality of memory blocks one from each of the plurality of memory circuit layers and an array of vertical interconnections interconnecting the logic block and the plurality of memory blocks, wherein the array of vertical interconnections passes through at least one memory block of the plurality of memory blocks, wherein the at least one of the memory block stacks is able to perform memory operations through the array of vertical interconnections.
  • 145. The thin and substantially flexible structure of claim 1, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 146. The thin and substantially flexible circuit of claim 12, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 147. The structure of claim 22, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 148. The thin and substantially flexible integrated circuit of claim 24, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 149. The thin and substantially flexible structure of claim 53, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 150. The thin and substantially flexible circuit of claim 63, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 151. The structure of claim 73, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 152. The thin and substantially flexible integrated circuit of claim 83, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 153. The thin and substantially flexible structure of claim 93, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 154. The structure of claim 103, wherein the semiconductor layer is thinned and polished such that the semiconductor layer is substantially flexible.
  • 155. The structure of claim 133, wherein the semiconductor substrate is thinned and polished such that the semiconductor substrate is substantially flexible.
  • 156. The integrated circuit of claim 139, wherein a process technology used to make the at least one thin, substantially flexible integrated circuit layer is different from a process technology used to make at least one of the plurality of memory circuit layers.
  • 157. The substantially flexible integrated circuit of claim 142, wherein a process technology used to make the at least one thin, substantially flexible integrated circuit layer is different from a process technology used to make at least one of the plurality of memory circuit layers.
  • 158. The thin and substantially flexible circuit of claim 13, wherein: the thin semiconductor layer comprises vertical holes etched therethrough; andthe vertical interconnect conductor and the vertical silicon-based dielectric insulator are formed in one of the vertical holes of the thin semiconductor layer.
  • 159. The structure of claim 23, further comprising: a bottomside surface and a topside surface;contacts formed on the bottomside surface and electrically connected to the vertical interconnect conductor; andinterconnects, contacts or circuits formed on or near the topside surface and electrically connected to the vertical interconnect conductors;wherein the interconnects, contacts or circuits are electrically connected to the contacts on the bottomside surface via the vertical interconnects.
  • 160. The integrated circuit of claim 133, further comprising a plurality of memory circuit layers, wherein a comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×108 dynes/cm2 and an array of memory cells.
  • 161. The integrated circuit of claim 139, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, the at least one low stress silicon-based dielectric layer, and the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.
  • 162. The integrated circuit of claim 140, wherein a portion of the integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic portion of the at least one thin, substantially flexible integrated circuit layer, a memory portion of at least one of the plurality of memory circuit layers and vertical interconnections interconnecting the logic portion and the memory portion, wherein the at least one of the memory block stacks is able to perform memory operations.
  • 163. The substantially flexible integrated circuit of claim 137, further comprising a plurality of memory circuit layers, wherein a comprises at least one low-stress silicon-based dielectric layer having a tensile stress of less than 5×108 dynes/cm2 and an array of memory cells.
  • 164. The substantially flexible integrated circuit of claim 142, wherein the integrated circuit is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate with polished or smoothed backside, the at least one low stress silicon-based dielectric layer, and the at least one low-stress silicon-based dielectric layer of each memory layer of the plurality of memory circuit layers.
  • 165. The substantially flexible integrated circuit of claim 143, wherein a portion of the substantially flexible integrated circuit is vertically partitioned into a plurality of memory block stacks, wherein at least one of the plurality of memory block stacks comprises a logic portion of the at least one thin, substantially flexible integrated circuit layer, a memory portion of at least one of the plurality of memory circuit layers and vertical interconnections interconnecting the logic portion and the memory portion, wherein the at least one of the memory block stacks is able to perform memory operations.
US Referenced Citations (407)
Number Name Date Kind
2915722 Foster Dec 1959 A
3202948 Farrand Aug 1965 A
3430835 Patzer et al. Mar 1969 A
3559282 Lesk Feb 1971 A
3560364 Burkhardt Feb 1971 A
3602982 Emmasingel Sep 1971 A
3615901 Medicus Oct 1971 A
3636358 Groschwitz Jan 1972 A
3716429 Napoli et al. Feb 1973 A
3777227 Krishna et al. Dec 1973 A
3780352 Redwanz Dec 1973 A
3868565 Kuipers Feb 1975 A
3922705 Yerman Nov 1975 A
3932932 Goodman Jan 1976 A
3997381 Wanlass Dec 1976 A
4028547 Eisenberger Jun 1977 A
4070230 Stein Jan 1978 A
4089063 Takezono et al. May 1978 A
4104418 Park et al. Aug 1978 A
4131985 Greenwood et al. Jan 1979 A
4142004 Hauser, Jr. et al. Feb 1979 A
4196232 Schnable et al. Apr 1980 A
4246595 Noyori et al. Jan 1981 A
4249302 Crepeau Feb 1981 A
4251909 Hoeberechts Feb 1981 A
4262631 Kubacki Apr 1981 A
4393127 Greschner et al. Jul 1983 A
4394401 Shioya et al. Jul 1983 A
4401986 Trenkler et al. Aug 1983 A
4416054 Thomas et al. Nov 1983 A
4464747 Groudan et al. Aug 1984 A
4500905 Shibata Feb 1985 A
4528072 Kurosawa et al. Jul 1985 A
4539068 Takagi et al. Sep 1985 A
4566037 Takatsu et al. Jan 1986 A
4585991 Reid et al. Apr 1986 A
4604162 Sobczak Aug 1986 A
4612083 Yasumoto et al. Sep 1986 A
4617160 Belanger et al. Oct 1986 A
4618397 Shimizu et al. Oct 1986 A
4618763 Schmitz Oct 1986 A
4622632 Tanimoto et al. Nov 1986 A
4633438 Kume et al. Dec 1986 A
4637029 Hayakawa et al. Jan 1987 A
4642487 Carter Feb 1987 A
4663559 Christensen May 1987 A
4684436 Burns et al. Aug 1987 A
4693770 Hatada Sep 1987 A
4702336 Seibert et al. Oct 1987 A
4702936 Maeda et al. Oct 1987 A
4706166 Go Nov 1987 A
4721938 Stevenson Jan 1988 A
4724328 Lischke Feb 1988 A
4761681 Reid Aug 1988 A
4766670 Gazdik et al. Aug 1988 A
4784721 Holmen et al. Nov 1988 A
4810673 Freeman Mar 1989 A
4810889 Yokomatsu et al. Mar 1989 A
4825277 Mattox et al. Apr 1989 A
4835765 Bergmans et al. May 1989 A
4841483 Furuyama Jun 1989 A
4849857 Butt et al. Jul 1989 A
4855867 Gazdik et al. Aug 1989 A
4857481 Tam et al. Aug 1989 A
4890157 Wilson Dec 1989 A
4892753 Wang et al. Jan 1990 A
4892842 Corrie et al. Jan 1990 A
4897708 Clements Jan 1990 A
4919749 Mauger et al. Apr 1990 A
4924589 Leedy May 1990 A
4928058 Williamson May 1990 A
2641129 Bull Jun 1990 A
4934799 Chu Jun 1990 A
4939568 Kato et al. Jul 1990 A
4939694 Eaton et al. Jul 1990 A
4940916 Borel et al. Jul 1990 A
4950987 Vranish et al. Aug 1990 A
4952446 Lee et al. Aug 1990 A
4954865 Rokos Sep 1990 A
4954875 Clements Sep 1990 A
4957882 Shinomiya Sep 1990 A
4965415 Young et al. Oct 1990 A
4966663 Mauger Oct 1990 A
4983251 Haisma et al. Jan 1991 A
4988423 Yamamoto Jan 1991 A
4990462 Sliwa Feb 1991 A
4994336 Benecke et al. Feb 1991 A
4994735 Leedy Feb 1991 A
5000113 Wang et al. Mar 1991 A
5008619 Keogh et al. Apr 1991 A
5010024 Allen et al. Apr 1991 A
5020219 Leedy Jun 1991 A
5045921 Lin et al. Sep 1991 A
5051326 Celler et al. Sep 1991 A
5059556 Wilcoxen Oct 1991 A
5062689 Koehler Nov 1991 A
5064275 Tsunoda et al. Nov 1991 A
5070026 Greenwald et al. Dec 1991 A
5071510 Findler et al. Dec 1991 A
5087585 Hayashi Feb 1992 A
5098865 Machado et al. Mar 1992 A
5103557 Leedy Apr 1992 A
5109360 Inazumi et al. Apr 1992 A
5110373 Mauger May 1992 A
5110712 Kessler et al. May 1992 A
5111278 Eichelberger May 1992 A
5116777 Chan et al. May 1992 A
5117282 Salatino May 1992 A
5119164 Sliwa et al. Jun 1992 A
5130894 Miller Jul 1992 A
5132244 Roy Jul 1992 A
5144142 Fueki et al. Sep 1992 A
5151775 Hadwin Sep 1992 A
5156909 Henager, Jr. et al. Oct 1992 A
5166962 Murooka et al. Nov 1992 A
5169805 Mok et al. Dec 1992 A
5188706 Hori et al. Feb 1993 A
5198965 Curtis et al. Mar 1993 A
5202754 Bertin et al. Apr 1993 A
5203731 Zimmerman Apr 1993 A
5225771 Leedy Jul 1993 A
5236118 Bower et al. Aug 1993 A
5240458 Linglain et al. Aug 1993 A
5241454 Ameen et al. Aug 1993 A
5245227 Furtek et al. Sep 1993 A
5245277 Nguyen Sep 1993 A
5255227 Haeffele Oct 1993 A
5259247 Bantien Nov 1993 A
5262341 Fueki et al. Nov 1993 A
5262351 Bureau et al. Nov 1993 A
5270261 Bertin et al. Dec 1993 A
5273940 Sanders Dec 1993 A
5274270 Tuckerman Dec 1993 A
5278839 Matsumoto et al. Jan 1994 A
5279865 Chebi et al. Jan 1994 A
5283107 Bayer et al. Feb 1994 A
5284796 Nakanishi et al. Feb 1994 A
5284804 Moslehi Feb 1994 A
5293457 Arima et al. Mar 1994 A
5321884 Ameen et al. Jun 1994 A
5323035 Leedy Jun 1994 A
5323060 Fogal et al. Jun 1994 A
5324687 Wojnarowski Jun 1994 A
5338975 Cole et al. Aug 1994 A
5343366 Cipolla et al. Aug 1994 A
5343406 Freeman Aug 1994 A
5347428 Carson et al. Sep 1994 A
5354695 Leedy Oct 1994 A
5357473 Mizuno et al. Oct 1994 A
5358909 Hashiguchi et al. Oct 1994 A
5363021 MacDonald Nov 1994 A
5374564 Bruel Dec 1994 A
5374569 Yilmaz et al. Dec 1994 A
5374920 Evens Dec 1994 A
5374940 Corio Dec 1994 A
5385632 Goossen Jan 1995 A
5385909 Nelson et al. Jan 1995 A
5397747 Angiulli et al. Mar 1995 A
5399505 Dasse et al. Mar 1995 A
RE34893 Fujii et al. Apr 1995 E
5420458 Shimoji May 1995 A
5424920 Miyake Jun 1995 A
5426072 Finnila Jun 1995 A
5426363 Akagi et al. Jun 1995 A
5426378 Ong Jun 1995 A
5432444 Yasohama et al. Jul 1995 A
5432681 Linderman Jul 1995 A
5432719 Freeman Jul 1995 A
5432729 Carson et al. Jul 1995 A
5432999 Capps et al. Jul 1995 A
5434500 Hauck et al. Jul 1995 A
5448106 Fujitsu Sep 1995 A
5450603 Davies Sep 1995 A
5451489 Leedy Sep 1995 A
5457879 Gurtler et al. Oct 1995 A
5463246 Matsunami Oct 1995 A
5468606 Bogart et al. Nov 1995 A
5470693 Sachdev et al. Nov 1995 A
5476813 Naruse Dec 1995 A
5478781 Bertin et al. Dec 1995 A
5480842 Clifton et al. Jan 1996 A
5481133 Hsu Jan 1996 A
5489554 Gates Feb 1996 A
5502667 Bertin et al. Mar 1996 A
5512397 Leedy Apr 1996 A
5514628 Enomoto et al. May 1996 A
5517457 Sakui et al. May 1996 A
5527645 Pati et al. Jun 1996 A
5529829 Koskenmaki et al. Jun 1996 A
5534465 Frye et al. Jul 1996 A
5552995 Sebastian Sep 1996 A
5555212 Toshiaki et al. Sep 1996 A
5563084 Ramm et al. Oct 1996 A
5571741 Leedy Nov 1996 A
5572689 Gallup et al. Nov 1996 A
5574729 Kinoshita et al. Nov 1996 A
5577050 Bair et al. Nov 1996 A
5580687 Leedy Dec 1996 A
5581498 Ludwig et al. Dec 1996 A
5582939 Pierrat Dec 1996 A
5583688 Hornbeck Dec 1996 A
5583749 Tredennick Dec 1996 A
5592007 Leedy Jan 1997 A
5592018 Leedy Jan 1997 A
5595933 Heijboer Jan 1997 A
5606186 Noda Feb 1997 A
5615163 Sakui et al. Mar 1997 A
5620915 Chen et al. Apr 1997 A
5626137 Dumoulin et al. May 1997 A
5627112 Tennant et al. May 1997 A
5629137 Leedy May 1997 A
5633209 Leedy May 1997 A
5637536 Val Jun 1997 A
5637907 Leedy Jun 1997 A
5654127 Leedy Aug 1997 A
5654220 Leedy Aug 1997 A
5656552 Hudak et al. Aug 1997 A
5661339 Clayton Aug 1997 A
5666288 Jones et al. Sep 1997 A
5675185 Chen et al. Oct 1997 A
5691945 Liou et al. Nov 1997 A
5694588 Ohara et al. Dec 1997 A
5703747 Voldman et al. Dec 1997 A
5715144 Ameen et al. Feb 1998 A
5719438 Beilstein, Jr. et al. Feb 1998 A
5725995 Leedy Mar 1998 A
5733814 Flesher et al. Mar 1998 A
5736448 Saia et al. Apr 1998 A
5745076 Turlington et al. Apr 1998 A
5745673 Di Zenzo et al. Apr 1998 A
5750211 Weise et al. May 1998 A
5753536 Sugiyama et al. May 1998 A
5760478 Bozso et al. Jun 1998 A
5763943 Baker et al. Jun 1998 A
5764577 Johnston et al. Jun 1998 A
5764878 Kablanian et al. Jun 1998 A
5773152 Okonogi Jun 1998 A
5777379 Karavakis et al. Jul 1998 A
5786116 Rolfson Jul 1998 A
5786628 Beilstein, Jr. et al. Jul 1998 A
5786629 Faris Jul 1998 A
5787445 Daberko Jul 1998 A
5793115 Zavracky et al. Aug 1998 A
5818748 Bertin et al. Oct 1998 A
5831280 Ray Nov 1998 A
5834162 Malba Nov 1998 A
5834334 Leedy Nov 1998 A
5840593 Leedy Nov 1998 A
5847929 Bernier et al. Dec 1998 A
5856695 Ito et al. Jan 1999 A
5861761 Kean Jan 1999 A
5868949 Sotokawa et al. Feb 1999 A
5869354 Leedy Feb 1999 A
5870176 Sweatt et al. Feb 1999 A
5880010 Davidson Mar 1999 A
5882532 Field et al. Mar 1999 A
5892271 Takeda et al. Apr 1999 A
5902118 Hubner May 1999 A
5907178 Baker et al. May 1999 A
5907248 Bauer May 1999 A
5914504 Augusto Jun 1999 A
5915167 Leedy Jun 1999 A
5930150 Cohen et al. Jul 1999 A
5940031 Turlington et al. Aug 1999 A
5946559 Leedy Aug 1999 A
5976953 Zavracky et al. Nov 1999 A
5985693 Leedy Nov 1999 A
5998069 Cutter et al. Dec 1999 A
6002268 Sasaki Dec 1999 A
6008126 Leedy Dec 1999 A
6008530 Kano Dec 1999 A
6017658 Rhee et al. Jan 2000 A
6020257 Leedy Feb 2000 A
6023098 Higshiguchi et al. Feb 2000 A
6027958 Vu et al. Feb 2000 A
RE36623 Wang et al. Mar 2000 E
6045625 Houston Apr 2000 A
6050832 Lee et al. Apr 2000 A
6084284 Adamic, Jr. Jul 2000 A
6087284 Brix et al. Jul 2000 A
6092174 Roussakov Jul 2000 A
6097096 Gardner et al. Aug 2000 A
6133626 Hawke et al. Oct 2000 A
6133640 Leedy Oct 2000 A
6154809 Ikenaga et al. Nov 2000 A
6166559 McClintock Dec 2000 A
6166711 Odake Dec 2000 A
6194245 Tayanaka Feb 2001 B1
6197456 Aleshin et al. Mar 2001 B1
6208545 Leedy Mar 2001 B1
6230233 Lofgren et al. May 2001 B1
6236602 Patti May 2001 B1
6239495 Sakui et al. May 2001 B1
6261728 Lin Jul 2001 B1
6288561 Leedy Sep 2001 B1
6294909 Leedy Sep 2001 B1
6300935 Sobel et al. Oct 2001 B1
6301653 Mohamed et al. Oct 2001 B1
6320593 Sobel et al. Nov 2001 B1
6335491 Alagaratnam et al. Jan 2002 B1
6355976 Faris Mar 2002 B1
RE37637 Clifton et al. Apr 2002 E
6376909 Forbes et al. Apr 2002 B1
6392304 Butler May 2002 B1
6417027 Akram Jul 2002 B1
6437990 Degani et al. Aug 2002 B1
6445006 Brandes et al. Sep 2002 B1
6511857 Kono et al. Jan 2003 B1
6517027 Abruzzese Feb 2003 B1
6518073 Momohara Feb 2003 B2
6551857 Leedy Apr 2003 B2
6563224 Leedy May 2003 B2
6617671 Akram Sep 2003 B1
6632706 Leedy Oct 2003 B1
6682981 Leedy Jan 2004 B2
6707160 Yamaji Mar 2004 B2
6713327 Leedy Mar 2004 B2
6714625 Leedy Mar 2004 B1
6734539 Degani et al. May 2004 B2
6740964 Sasaki May 2004 B2
6747347 Farrar et al. Jun 2004 B2
6765279 Leedy Jul 2004 B2
6838896 Leedy Jan 2005 B2
6867486 Hong Mar 2005 B2
6873057 Chen et al. Mar 2005 B2
6891387 Leedy May 2005 B2
6894392 Gudesen et al. May 2005 B1
6979895 Akram et al. Dec 2005 B2
7106646 Schoenfeld et al. Sep 2006 B2
7138295 Leedy Nov 2006 B2
7176545 Leedy Feb 2007 B2
7176579 Konishi et al. Feb 2007 B2
7193239 Leedy Mar 2007 B2
7223696 Leedy May 2007 B2
7230316 Yamazaki et al. Jun 2007 B2
7242012 Leedy Jul 2007 B2
7307020 Leedy Dec 2007 B2
7354798 Pogge et al. Apr 2008 B2
7385835 Leedy Jun 2008 B2
7402897 Leedy Jul 2008 B2
7474004 Leedy Jan 2009 B2
7479694 Leedy Jan 2009 B2
7485571 Leedy Feb 2009 B2
7485955 Kang et al. Feb 2009 B2
7489025 Chen et al. Feb 2009 B2
7504732 Leedy Mar 2009 B2
7521785 Damberg et al. Apr 2009 B2
7550805 Leedy Jun 2009 B2
7615837 Leedy Nov 2009 B2
7670893 Leedy Mar 2010 B2
7705466 Leedy Apr 2010 B2
7736948 Dekker et al. Jun 2010 B2
7763948 Leedy Jul 2010 B2
7820469 Leedy Oct 2010 B2
7911012 Leedy Mar 2011 B2
8080442 Leedy Dec 2011 B2
8410617 Leedy Apr 2013 B2
20010002711 Gonzalez Jun 2001 A1
20010013423 Dalal et al. Aug 2001 A1
20010014051 Watanabe et al. Aug 2001 A1
20010025364 Kaneko Sep 2001 A1
20010033030 Leedy Oct 2001 A1
20020117689 Akimoto Aug 2002 A1
20020127775 Haba et al. Sep 2002 A1
20020132465 Leedy Sep 2002 A1
20030011032 Umebayashi Jan 2003 A1
20030173608 Leedy Sep 2003 A1
20030184976 Brandenburg et al. Oct 2003 A1
20030197253 Gann et al. Oct 2003 A1
20030218182 Leedy Nov 2003 A1
20030223535 Leedy Dec 2003 A1
20040000708 Rapport et al. Jan 2004 A1
20040021212 Hamaguchi et al. Feb 2004 A1
20040070063 Leedy Apr 2004 A1
20040140547 Yamazaki et al. Jul 2004 A1
20040197951 Leedy Oct 2004 A1
20040245617 Damberg et al. Dec 2004 A1
20040251557 Kee Dec 2004 A1
20050023656 Leedy Feb 2005 A1
20050051841 Leedy Mar 2005 A1
20050051904 Kim et al. Mar 2005 A1
20050082641 Leedy Apr 2005 A1
20060231927 Ohno Oct 2006 A1
20070035033 Ozguz et al. Feb 2007 A1
20070176297 Zohni Aug 2007 A1
20080237591 Leedy Oct 2008 A1
20080254572 Leedy Oct 2008 A1
20080284611 Leedy Nov 2008 A1
20080302559 Leedy Dec 2008 A1
20090014897 Ohno Jan 2009 A1
20090067210 Leedy Mar 2009 A1
20090174082 Leedy Jul 2009 A1
20090175104 Leedy Jul 2009 A1
20090194768 Leedy Aug 2009 A1
20090218700 Leedy Sep 2009 A1
20090219742 Leedy Sep 2009 A1
20090219743 Leedy Sep 2009 A1
20090219744 Leedy Sep 2009 A1
20090219772 Leedy Sep 2009 A1
20090230501 Leedy Sep 2009 A1
20100148371 Kaskoun et al. Jun 2010 A1
20100171224 Leedy Jul 2010 A1
20100171225 Leedy Jul 2010 A1
20100172197 Leedy Jul 2010 A1
20100173453 Leedy Jul 2010 A1
20110042829 Kaskoun et al. Feb 2011 A1
20110198672 Leedy Aug 2011 A1
Foreign Referenced Citations (76)
Number Date Country
3233195 Mar 1983 DE
189976 Aug 1986 EP
201380 Dec 1986 EP
224418 Jun 1987 EP
238089 Sep 1987 EP
314437 May 1989 EP
419898 Apr 1991 EP
455455 Nov 1991 EP
487302 May 1992 EP
503816 Sep 1992 EP
0 518 283 Dec 1992 EP
0 518 774 Dec 1992 EP
518283 Dec 1992 EP
518774 Dec 1992 EP
526551 Feb 1993 EP
0531723 Mar 1993 EP
0 554 063 Aug 1993 EP
0 555 252 Aug 1993 EP
554063 Aug 1993 EP
555252 Aug 1993 EP
703618 Mar 1996 EP
703619 Mar 1996 EP
731525 Sep 1996 EP
1233444 Dec 2002 EP
2641129 Jun 1990 FR
2125168 Feb 1984 GB
2215168 Sep 1989 GB
6074643 Apr 1985 JP
60126871 Jul 1985 JP
6130059 Feb 1986 JP
62277556 Nov 1987 JP
63076484 Apr 1988 JP
1199476 Sep 1988 JP
63229862 Sep 1988 JP
1157561 Jun 1989 JP
H01-199476 Aug 1989 JP
2027600 Jan 1990 JP
2037655 Feb 1990 JP
2082564 Mar 1990 JP
2239627 Sep 1990 JP
3127816 May 1991 JP
3174715 Jul 1991 JP
3284871 Dec 1991 JP
4010649 Jan 1992 JP
4042957 Feb 1992 JP
4076946 Mar 1992 JP
4083371 Mar 1992 JP
4107964 Apr 1992 JP
456956 Dec 1992 JP
5109977 Apr 1993 JP
05-250900 Sep 1993 JP
5283607 Oct 1993 JP
06-251172 Sep 1994 JP
06-291250 Oct 1994 JP
08-017962 Jan 1996 JP
8017962 Jan 1996 JP
08-083884 Mar 1996 JP
08-504060 Apr 1996 JP
4196263 Jul 1996 JP
9152979 Jun 1997 JP
10107065 Apr 1998 JP
10209371 Aug 1998 JP
261001 Sep 1999 JP
8910255 Nov 1989 WO
9009093 Aug 1990 WO
9105366 Apr 1991 WO
9203848 Mar 1992 WO
9217901 Oct 1992 WO
9413121 Jun 1994 WO
9509438 Apr 1995 WO
9641204 Dec 1996 WO
9641264 Dec 1996 WO
9641624 Dec 1996 WO
9819337 May 1998 WO
0105366 Jan 2001 WO
03078305 Sep 2003 WO
Non-Patent Literature Citations (58)
Entry
Bollmann et al., Three Dimensional Metallization for Vertically Integrated Circuits, MAM'97—Materials for Advanced Metallization.
“Christensens Physics of Diagnostic Radiology,” Currey et al., pp. 29-33, 1990.
“IC Tower Patent: Simple Technology Receives Patent on the IC Tower, a Stacked Memory Technology”, http://ww-w.simpletech.com/whatsnew/memory/@60824.htm (1998).
“Miniature Electro Microscopes Without Vacuum Pumps, Self-Contained Microfabricated Devices with Short Working Distances, Enable Operation in Air,” NASA Tech Briefs, 39-40 (1998).
“Partitioning Function and Packaging of Integrated Circuits for Physical Security of Data,” IBM Technical Disclosure Bulletin, IBM Corp., 32(1):46-49 (Jun. 1989).
Aboaf, J.A., “Stresses in SiO.sub.2 Films Obtained from the Thermal Decomposition of Tetraethylorthosilicate—Effect of Heat Treatment and Humidity,” J. Electrochem. Soc.: Solid State Science; 116(12): 1732-1736 (Dec. 1969).
Allen, Mark G., and Senturia, Stephen D., “Measurement of Polyimide Interlayer Adhesion Using Microfabricated Structures”; Sep. 25-30, 1988.
Alloert, K., et al., “A Comparison Between Silicon Nitride Films Made by PCVD of N.sub.2-SiH.sub.4/Ar and N.sub.2-SiH.sub.4/He,” Journal of the Electrochemical Society, vol. 132, No. 7, pp. 1763-1766, (Jul. 1985).
Bailey, R., “Glass for Solid-State Devices: Glass film has low intrinsic compressive stress for isolating active layers of magnetic-bubble and other solid-state devices,” NASA Tech Brief (1982).
Boyer, P.K.; Collins, G.J.; Moore, C.A.; Ritchie, W.K,; Roche, G. A.; Solanski, R. (A); Tang, C.C.; “Microelectronic thin film deposition by ultraviolet laser photolysis Monograph Title—Laser processing of semiconductor devices”; 1983; pp. 120-126.
Chang, E.Y.; Cibuzar, G.T.; Pande, K.P.; “Passivation of GaAs FETs with PECVD silicon nitride films of different stress states”; Sep. 1988; pp. 1412-1418.
Chen, Y.S.; Fatemi, H.; “Stress measurements on multilevel thin film dielectric layers used in Si integrated circuits”; May-Jun. 1986; pp. 645-649.
Chu et al., ed., 3D Packaging for Integrated Circuit Systems, Sandia Report SAND96-2801, UC-704, Nov. 1996.
Draper, B. L.; Hill, T.A.; “Stress and stress relaxation in integrated circuit metals and dielectrics”; Jul.-Aug. 1991; pp. 1956-1962.
European Search Report for Application No. EP 02 00 9643 (date completed: Oct. 8, 2002).
Garino, T.J.; Harrington, H. M.; “Residual stress in PZT thin films and its effect on ferroelectric properties”; 1992; pp. 341-347.
Guckel, H.; “Surface micromachined pressure transducers”; 1991; pp. 133-146.
Hayashi et al., A New Three Dimensional IC Fabrication Technology, Stacking Thin Film Dual-CMOS Layers, NEC Microelectronics Research Laboratories, 1991 IEEE.
Hendricks et al., “Polyquinoline Coatings and Films: Improved Organic Dielectrics for ICs and MCMs,” Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium, pp. 361-365 (1991).
Hsieh, et al., “Directional Deposition of Dielectric Silicon Oxide by Plasma Enhanced TEOS Process,” 1989 Proceedings, Sixth International IEEE VLSI Multilevel Interconnection Conference, pp. 411-415 (1989).
Jones, R.E., Jr. “An evaluation of methods for passivating silicon integrated circuits”, Apr. 1972; pp. 23-28.
Knolle, W.R., et al., “Characterization of Oxygen-Doped, Plasma-Deposited Silicon Nitride,” Journal of the Electrochemical Society, vol. 135, No. 5, pp. 1211-1217, (May 1988).
Kochugova, I.V.; Nikolaeva, L.V.; Vakser, N.M., (M.I. Kalinin Leningrad Polytechnic Institute (USSR); “Electrophysical investigation of thin-layered inorganic coatings”; 1989: pp. 826-828.
Koyanagi, Different Approaches to 3D Chips, Dept. of Bioengineering and Robotics, Tohoku University, Japan, pp. 10, 11, 13, 14, 16, 19.
Krishnamoorthy, et al., “3-D Integration of MQW Modulators Over Active Submicron CMOS Circuits: 375 Mb/s Transimpedance Receiver-Transmitter Circuit,” IEEE Photonics Technology Letters, 2(11): 1288-1290 (Nov. 1991.
Maw, T.; Hopla, R.E.; “Properties of a photoimageable thin polyimide film”; Nov. 26-29, 1990; pp. 71-76.
Mitsumasa Koyanagi et al., “Design of 4-KBIT X 4-layer Optically Coupled Three-Dimensional Common Memory for Parallel Processor System,” IEEE Journal of Solid-State Circuits, vol. 25. No. 1, Feb. 1, 1990.
Nguyen, S.V., Plasma Assisted Chemical Vapor Deposited Thin Films for Microelectronic Applications, J. Vac. Sci. Technol. vol. B4, No. 5, pp. 1159-1167, (Sep.-Oct. 1986).
Olmer, et al., “Intermetal Dielectric Deposition by Plasma Enhanced Chemical Vapor Deposition,” Fifth IEEE/CHMT International Electronic Manufacturing Technology Symposium—Design-to-Manufacturing Transfer Cycle, pp. 98-99 (1998).
Pai, Pei-Lin; “Multilevel Interconnection Technologies—A Framework and Examples”; 1987; pp. 1871.
Partial European Search Report for Application No. EP 02009643 (Oct. 8, 2002).
Pei-Lin Pai; Chetty, A.; Roat, R.; Cox, N.; Chiu Ting; “Material characteristics of spin-on glasses for interlayer dielectric applications”; Nov. 1987, pp. 2829-2834.
Phys. Rev. B., Condens, Matter Mater. Phys. (USA), Physical Review B (Condensed Matter and Materials Physics), Mar. 15, 2003, APS through AIP, USA.
Reche, J.J. H.; “Control of thin film materials properties used in high density multichip interconnect”; Apr. 24-28, 1989; p. 494.
Riley, P.E.; Shelley, A.; “Characterization of a spin-applied dielectric for use in multilevel metallization”: May 1988; pp. 1207-1210.
Runyan, W. R., “Deposition of Inorganic Thin Films”, Semiconductor Integrated Circuit Processing Technology, p. 142 (1990).
S Wolf, Silicon Processing for the VLSI Era, 1990, Lattice Press, vol. 2, p. 191.
Salazar, M.; Wilkins, C.W., Jr.; Ryan, V.W.: Wang, T.T.; “Low stress films of cyclized polybutadiene dielectrics by vacuum annealing”; Oct. 21-22, 1986; pp. 96-102.
Scheuerman, R.J., “Fabrication of Thin Dielectric Films with Low Internal Stresses,” J. Vac. Sci. and Tech., 7(1): 143-146 (1970).
Smith et al., Generation of Minimal Vertex Covers for Row/Column Allocation in Self-Repairable Arrays, IEEE Transactions on Computers, vol. 45, No. 1, Jan. 1996, pp. 109-115.
Sun, R.C.; Tisone, T.C.: Cruzan, P.D.; “Internal stresses and resistivity of low-voltage sputtered tungsten films (microelectronic cct. conductor)”; Mar. 1973; pp. 1009-1016.
Sung et al., “Well-aligned carbon nitride nanotubes synthesized in anodic alumina by electron cyclotron resonance chemical vapor deposition,” Applied Physics Letters, vol. 74, No. 2, 197, 1999, Jan. 11, 1999.
Svechnikov, S.V.; Kobylyatskaya, M.F.: Kimarskii, V.I.; Kaufman, A.P.; Kuzolvlev, Yu.I.; Cherepov, Ye. I.; Fomin, B.I.; “A switching plate with aluminum membrane crossings of conductors”; 1972.
Sze, S. M., “Surface Micromaching”, Semiconductor Sensors, pp. 58-63 (1994).
Tamura, H.; Nishikawa, T.; Wakino, K.; Sudo, T.; “Metalized MIC substrates using high K dielectric resonator materials”: Oct. 1988; pp. 117-126.
Tessier, et al., “An Overview of Dielectric Materials for Multichip Modules,” SPE, Electrical & Electronic Div., (6):260-269 (1991).
Tielert et al., “Benefits of Vertically Stacked Integrated Circuits for Sequential Logic,” IEEE, XP-000704550, 121-124 (Dec. 5, 1996).
Townsend, P.H.; Huggins, R.A.; “Stresses in borophosphosilicate glass films during thermal cycling”; Oct. 21-22, 1986; pp. 134-141.
Treichel, et al., “Planaized Low-Stress Oxide/Nitride Passivation for ULSI Devices,” J. Phys IV, Colloq. (France), 1 (C2): 839-846 (1991).
Vossen, John L., “Plasma-Enhanced Chemical Vapor Deposition”, Thin Film Processes II, pp. 536-541 (1991).
Wade, T.E.; “Low temperature double-exposed polyimide/oxide dielectric for VLSI multilevel metal interconnection”: 1982: pp. 516-519.
Wolf, Stanley and Richard N. Tauber; Silicon Processing for the VLSI Era, vol. 1: Process Technology; Sunset Beach, CA: Lattice Press, 1986, pp. 191-194.
Wolf, Stanley, “Basics of Thin Films”, Silicon Processing for the VLSI Era, pp. 115, 192-193 and 199 (1986).
Wolf, Stanley; Silicon Processing for the VLSI Era, 1990, Lattice Press, vol. 2, p. 191.
Bollmann et al., Three Dimensional Metallization for Vertically Integrated Circuits, Materials for Advanced Metallization, 1997, European Workshop; Date of Conference: Mar. 16-19, 1997.
Krisbnamoorthy, et al., “3-D Integration of MQW Modulators Over Active Submicron CMOS Circuits: 375 Mb/s Transimpedance Receiver-Transmitter Circuit,” IEEE Photonics Technology Letters, 2(11): 1288-1290 (Nov. 1995).
Boyer et al., “Microelectronic Thin Film Deposition by UV Laser Photolysis” Proc. Soc. of Photo-Instrumentation Eng., Jan. 1983.
Olmer, et al., “Intermetal Dielectric Deposition by Plasma Enhanced Chemical Vapor Deposition,” Fifth IEEE/CHMT International Electronic Manufacturing Technology Symposium—Design-to-Manufacturing Transfer Cycle, pp. 98-99; OCt. 10, 1988.
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20130187290 A1 Jul 2013 US
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Child 08971565 US
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Parent 12788618 May 2010 US
Child 13734874 US
Parent 10143200 May 2002 US
Child 12788618 US
Parent 09607363 Jun 2000 US
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