Patent Application
20240322040
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. For example, as device sizes shrink, undesirable diffusion of elements between adjacent device components could occur more easily, and the unintended negative effects may be more pronounced. In some cases, an unintended aluminum diffusion between a gate dielectric layer and a metal gate electrode could interfere with the proper tuning of threshold voltages. As a result, the device performance may not be optimal.
Therefore, although conventional methods of fabricating semiconductor devices have generally been adequate, they have not been satisfactory in all aspects.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc., as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as three-dimensional fin-shaped FETs (FinFETs) or gate-all-around (GAA) devices. In that regard, a FinFET device is a fin-like field-effect transistor device, and a GAA device is a multi-channel field-effect transistor device. FinFET devices and GAA devices have both been gaining popularity recently in the semiconductor industry, since they offer several advantages over traditional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices (e.g., “planar” transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processing that is compatible with the fabrication processing of planar devices. Thus, it may be desirable to design an integrated circuit (IC) chip using FinFET devices or GAA devices for a portion of, or the entire IC chip.
However, in spite of the advantages offered by the FinFET devices and/or GAA devices, certain challenges may still remain in IC applications in which FinFET or GAA devices are implemented. For instance, conventional threshold voltage (Vt) tuning may be done at least in part by a dipole drive-in method, in which a gate dielectric layer becomes doped by the dipole drive-in. For certain IC applications, the dipole drive-in may allow the transistors to achieve a different threshold voltage than the transistors for which the dipole drive-in process was not performed. The transistor for which the dipole drive-in process was performed may be referred to as a dipole drive-in transistor, and the other transistor for which the dipole drive-in was not performed may be referred to as a counterpart transistor, and their differently-tuned threshold voltages are specifically configured as such to facilitate their intended functionalities in different circuit applications.
However, in some cases, the dipole drive-in dopant (e.g., aluminum) may be present in the metal gate electrode formed over the gate dielectric layer (which is supposed to be undoped) of the counterpart transistor. When the gate dielectric comes into direct contact with the metal electrode, the atoms of the dipole drive-in dopant (e.g., aluminum atoms) may diffuse from the metal gate electrode into the gate dielectric layer, thereby causing the gate dielectric layer of the counterpart transistor to become partially doped, which is not intended. For example, the dipole drive-in process may use aluminum oxide (AlOx), titanium aluminum nitride (TixAlyNz), or aluminum nitride (AlNx) as a dopant source. The aluminum from these materials may diffuse into the gate dielectric layer. This unintentional diffusion may lessen the threshold voltage difference between the dipole drive-in transistor and the counterpart transistor, which is undesirable, because it may adversely interfere with the intended functioning of the counterpart and/or dipole drive-in transistors in their circuit applications.
To address the issues discussed above, the present disclosure implements an aluminum-free conductive layer between the gate dielectric layers and the metal gate electrodes. Such a layer can block (or at least reduce) the undesirable diffusion of aluminum discussed above, which helps the dipole drive-in transistors and the counterpart transistors to maintain their intended threshold voltage differences. Since such a layer is also conductive, its implementation would not unduly increase parasitic resistance either. Consequently, device performance may be optimized. The various aspects of the present disclosure will now be discussed below in more detail.
Referring to
Three-dimensional active regions 120 are formed on the substrate 110. The active regions 120 are elongated fin-like structures that protrude upwardly out of the substrate 110. As such, the active regions 120 may be interchangeably referred to as fin structures 120 hereinafter. The fin structures 120 may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer overlying the substrate 110, exposing the photoresist to a pattern, performing post-exposure bake processes, and developing the photoresist to form a masking element (not shown) including the resist. The masking element is then used for etching recesses into the substrate 110, leaving the fin structures 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. In some embodiments, the fin structure 120 may be formed by double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned layer using a self-aligned process. The layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin structures 120.
The IC device 90 also includes source/drain features 122 formed over the fin structures 120. The source/drain features 122 may include epi-layers that are epitaxially grown on the fin structures 120. The IC device 90 further includes isolation structures 130 formed over the substrate 110. The isolation structures 130 electrically separate various components of the IC device 90. The isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable materials. In some embodiments, the isolation structures 130 may include shallow trench isolation (STI) features. In one embodiment, the isolation structures 130 are formed by etching trenches in the substrate 110 during the formation of the fin structures 120. The trenches may then be filled with an isolating material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structure such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures may also be implemented as the isolation structures 130. Alternatively, the isolation structures 130 may include a multi-layer structure, for example, having one or more thermal oxide liner layers.
The IC device 90 also includes gate structures 140 formed over and engaging the fin structures 120 on three sides in a channel region of each fin 120. The gate structures 140 may be dummy gate structures (e.g., containing an oxide gate dielectric and a polysilicon gate electrode), or they may be HKMG structures that contain a high-k gate dielectric and a metal gate electrode, where the HKMG structures are formed by replacing the dummy gate structures. Though not depicted herein, the gate structure 140 may include additional material layers, such as an interfacial layer over the fin structures 120, a capping layer, other suitable layers, or combinations thereof.
Referring to
It is also understood that the various aspects of the present disclosure discussed below may apply to multi-channel devices such as Gate-All-Around (GAA) devices.
A plurality of nano-structures 170 is disposed over each of the fin structures 120. The nano-structures 170 may include nano-sheets, nano-tubes, or nano-wires, or some other type of nano-structure that extends horizontally in the X-direction. Portions of the nano-structures 170 under the gate structure 140 may serve as the channels of the GAA device 150. Dielectric inner spacers 175 may be disposed between the nano-structures 170. In addition, although not illustrated for reasons of simplicity, each of the nano-structures 170 may be wrapped around circumferentially by a gate dielectric as well as a gate electrode. In the illustrated embodiment, the portions of the nano-structures 170 outside the gate structure 140 may serve as the source/drain features of the GAA device 150. However, in some embodiments, continuous source/drain features may be epitaxially grown over portions of the fin structures 120 outside of the gate structure 140. Regardless, conductive source/drain contacts 180 may be formed over the source/drain features to provide electrical connectivity thereto. An interlayer dielectric (ILD) 185 is formed over the isolation structures 130 and around the gate structure 140 and the source/drain contacts 180.
Regardless of whether the transistors of an IC are implemented as a FinFET of
Referring now to
The vertical stacks 210 and 211 each include one or more n-type transistors (e.g., NFETs) and one or more p-type transistors (e.g., PFETs). For example, the vertical stack 210 includes an NFET and a PFET that is disposed vertically over the NFET. The NFET may include a plurality of channel components 120A-120B, and the PFET may include a plurality of channel components 120C-120D. The channel components 120A-120D are portions of active regions. The channel components 120A-120D may be patterned into nano-structure channels, for example, as nano-sheets, nano-tubes, nano-wires, nano-bars, etc. The channel components 120A-120D may each include a semiconductive material, for example, a silicon (Si) material, a silicon germanium (SiGe) material, or a III-V group compound (e.g., a compound that includes an element from the III-group of the periodic table as well as an element from the V-group of the periodic table).
Similar to the vertical stack 210, the vertical stack 211 also includes an NFET and a PFET disposed over the NFET. The NFET of the vertical stack 211 may include a plurality of channel components 120E-120F, and the PFET of the vertical stack 211 may include a plurality of channel components 120G-120H, where each of the channel components 120E-120H may be patterned as nano-structure channels that contain a semiconductive material, such as nano-sheets, nano-tubes, nano-wires, nano-bars, etc.
It is understood that each of the NFETs and the PFETs of the vertical stacks 210 and 211 may optionally include more than two channel components. For example, the NFET of the vertical stack 210 may optionally include additional channel components between the channel component 120A and 120B, and the PFET of the vertical stack 210 may optionally include additional channel components between the channel component 120C and 120D, and the same is true for the NFET and the PFET of the vertical stack 211. These optional additional channel components are conceptually represented as a plurality of vertical dots in
The channel components 120A-120H are circumferentially wrapped around (e.g., in 360 degrees) by gate dielectric layers 230A-230H, respectively. The gate dielectric layers 230A-230H include high-k dielectric materials, which are dielectric materials whose dielectric constant is greater than a dielectric constant of silicon dioxide. In some embodiments, the gate dielectric layers 230A-230H include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or combinations thereof.
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In some embodiments, the deposition process 280 may include ALD, CVD, PVD, or combinations thereof. The parameters of the deposition process 280 may be carefully configured to accurately control a thickness 310 of each of the aluminum-free conductive layers 300A-300H. In some embodiments, the thickness 310 is in a range between about 0.3 and about 2.5 nanometers. The thickness 310 is also correlated with the thicknesses of one or more other components of the IC device 200. For example, the gate dielectric layers 300A-300H may each have a thickness 320, and the gate dielectric layers 230E-230H may each have a thickness 321, which are directly correlated with the thickness 310 of the aluminum-free conductive layers 300A-300D. In some embodiments, a ratio between the thickness 310 and the thickness 320 is in a range between about 0.1:1 and about 5:1, and a ratio between the thickness 310 and the thickness 321 is in a range between about 0.1:1 and about 5:1.
The above ranges are not randomly chosen but rather specifically configured to optimize the performance of the IC device 200. For example, as will be discussed in more detail below, the aluminum-free conductive layers 300A-300H are implemented to prevent or reduce undesirable diffusion (e.g., diffusion of aluminum) between the gate dielectric layers 230A-230H and the metal gate electrodes that will be formed in a subsequent process. If the aluminum-free conductive layers 300A-300H are too thin, they may not adequately serve their intended purposes of blocking the undesirable aluminum diffusion. On the other hand, if the aluminum-free conductive layers 300A-300H are too thick, they may consume an excessive amount of chip space, which is valuable as device sizes continue to shrink. Furthermore, if the aluminum-free conductive layers 300A-300H are too thick, they could also adversely interfere with the threshold voltage tuning of their respective transistors. Here, the above ranges ensure that the aluminum-free conductive layers 300A-300H are thick enough to adequately block the undesirable diffusion, while thin enough to conserve chip space and not interfere with the tuning of threshold voltages.
Referring now to
The metal gate electrode layer 350 contains an n-type work function metal layer to tune a threshold voltage of the NFET of the vertical stack 210 and the NFET of the vertical stack 211. In some embodiments, the n-type work function metal layer includes an aluminum-containing metal, such as titanium aluminum carbide (TixAlyCz). A fill metal layer is formed over the work function metal layer and may serve as a main conductive portion of the gate electrode. In some embodiments, the fill metal layer may include titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), cobalt (Co), etc.
As discussed above, the gate dielectric layers 230E-230H of the vertical stack 211 are doped with aluminum due to the performance of the dipole drive-in process 260 (see
Referring now to
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At this stage of fabrication, the following transistors are formed: a counterpart NFET (the NFET of the vertical stack 210), a counterpart PFET (the PFET of the vertical stack 210), a drive-in NFET (the NFET of the vertical stack 211), and a drive-in PFET (the PFET of the vertical stack 211). The threshold voltage of the counterpart NFET is tuned by a combination of the following components: the n-type work function metal layer of the metal gate electrode layer 350A, the undoped gate dielectric layer 230A and 230B, and the aluminum-free conductive layers 300A and 300B. The threshold voltage of the drive-in NFET is tuned by a combination of the following components: the n-type work function metal layer of the metal gate electrode layer 350E, the p-type doped gate dielectric layer 230E and 230F, and the aluminum-free conductive layers 300E and 300F. The threshold voltage of the counterpart PFET is tuned by a combination of the following components: the p-type work function metal layer of the metal gate electrode layer 380C, and the undoped gate dielectric layer 230C and 230D. The threshold voltage of the drive-in PFET is tuned by a combination of the following components: the p-type work function metal layer of the metal gate electrode layer 380G, and the p-type doped gate dielectric layer 230G and 230H.
These transistors (along with their distinct structural arrangements of the respective components) are formed as an inherent result of the fabrication processes of
Note that although aluminum is used herein as an example p-type dipole material, it is not intended to be limiting unless otherwise claimed. In other embodiments where the p-type dipole material is another element that is not aluminum, then the layers 300A-300H may be implemented as conductive layer that is free of that other non-aluminum element as well.
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At this stage of fabrication, the following transistors are formed: a counterpart NFET (the NFET of the vertical stack 210), a counterpart PFET (the PFET of the vertical stack 210), a drive-in NFET (the NFET of the vertical stack 211), and a drive-in PFET (the PFET of the vertical stack 211). The threshold voltage of the counterpart NFET is tuned by a combination of the following components: the n-type work function metal layer of the metal gate electrode layer 350A, the undoped gate dielectric layer 230A and 230B, and the aluminum-free conductive layers 300A and 300B. The threshold voltage of the drive-in NFET is tuned by a combination of the following components: the n-type work function metal layer of the metal gate electrode layer 350E, the p-type doped gate dielectric layer 230E and 230F. Note that unlike the first embodiment illustrated in
These transistors (along with their distinct structural arrangements of the respective components) are formed as an inherent result of the fabrication processes of
As discussed above,
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At this stage of fabrication, the following transistors are formed: a counterpart NFET (the NFET of the vertical stack 210), a counterpart PFET (the PFET of the vertical stack 210), a drive-in NFET (the NFET of the vertical stack 211), and a drive-in PFET (the PFET of the vertical stack 211). The threshold voltage of the counterpart NFET is tuned by a combination of the following components: the n-type work function metal layer of the metal gate electrode layer 350A, the undoped gate dielectric layer 230A and 230B. Note that unlike the first embodiment illustrated in
These transistors (along with their distinct structural arrangements of the respective components) are formed as an inherent result of the fabrication processes of
It is understood that although
It is also understood that the various aspects of the present disclosure (e.g., implementing the aluminum-free conductive layers to block aluminum diffusion) may apply not to just GAA and FinFET devices, but also to complementary field effect transistors (CFET). In that regard,
Referring to
Portions of the semiconductor layers 431 are patterned into nano-structure channels 431, for example, as nano-sheets, nano-tubes, nano-wires, nano-bars, etc. Dummy gate structures 440 are formed over the uppermost one of the nano-structure channels 431. In some embodiments, the dummy gate structures 440 may include a polysilicon dummy gate electrode. Each dummy gate structure 440 may be patterned by one or more hard mask layers 450, which may include one or more dielectric materials. Gate spacers 460 are formed on sidewalls of the dummy gate structure 440. The gate spacers 460 may also include a suitable dielectric material. In some embodiments, each of the gate spacers 460 may include a plurality of gate spacer layers, but this is not specifically illustrated herein for reasons of simplicity. Note that a plurality of openings 470 are formed to divide the components of the CFET 400 into separate stacks, where each stack has its own dummy gate structure 440.
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An etching stop layer 520 is formed over the top source/drain regions 510 in the openings 470. An interlayer dielectric (ILD) 530 is formed over in the opening 470 over the etching stop layer 520. The ILD 530 may also be referred to as an ILDO. The etching stop layer 520 and the ILD 530 may include different types of dielectric materials. The etching stop layer 520 and the ILD 530 may be planarized by a chemical mechanical polishing (CMP) process to flatten their upper surfaces.
Still referring to
The semiconductor layers 430 (e.g., containing SiGe) are also removed, for example, using one or more etching processes. Thereafter, gate structures 640 for the bottom device of the CFET 400 are formed. For example, the gate structures 640 may include gate dielectric structures 650 and gate electrodes 660 are formed to replace the removed semiconductor layers 430 and the removed dummy gate structures 440 for the bottom device. Note that portions of the gate dielectric structure 650 may also serve as the gate dielectric structures of the top tier device of the CFET 400. However, the gate electrodes of the top device of the CFET 400 are not formed yet. For example, one or more etch back processes may be performed to etch back the gate electrodes 660 that are located in the top device regions, such that empty spaces occupy (at this time) what will eventually become the gate electrodes of the top device of the CFET.
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The processes discussed above with reference to
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It is understood that additional processes may be performed to continue the fabrication of the CFET 400. for example, conductive gate contacts may be formed (e.g., extending vertically through the SAC 780) to provide electrical connectivity to the gate structures 740. Packaging processes may also be formed to continue the packaging of the CFET 400.
In an embodiment, the entity 902 represents a service system for manufacturing collaboration; the entity 904 represents an user, such as product engineer monitoring the interested products; the entity 906 represents an engineer, such as a processing engineer to control process and the relevant recipes, or an equipment engineer to monitor or tune the conditions and setting of the processing tools; the entity 908 represents a metrology tool for IC testing and measurement; the entity 910 represents a semiconductor processing tool, such an EUV tool that is used to perform lithography processes to define the gate spacers of an SRAM device; the entity 912 represents a virtual metrology module associated with the processing tool 910; the entity 914 represents an advanced processing control module associated with the processing tool 910 and additionally other processing tools; and the entity 916 represents a sampling module associated with the processing tool 910.
Each entity may interact with other entities and may provide integrated circuit fabrication, processing control, and/or calculating capability to and/or receive such capabilities from the other entities. Each entity may also include one or more computer systems for performing calculations and carrying out automations. For example, the advanced processing control module of the entity 914 may include a plurality of computer hardware having software instructions encoded therein. The computer hardware may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), input/output device (e.g., mouse and keyboard). The software instructions may be written in any suitable programming language and may be designed to carry out specific tasks.
The integrated circuit fabrication system 900 enables interaction among the entities for the purpose of integrated circuit (IC) manufacturing, as well as the advanced processing control of the IC manufacturing. In an embodiment, the advanced processing control includes adjusting the processing conditions, settings, and/or recipes of one processing tool applicable to the relevant wafers according to the metrology results.
In another embodiment, the metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on the process quality and/or product quality. In yet another embodiment, the metrology results are measured from chosen fields and points of the subset of processed wafers according to an optimal sampling field/point determined based on various characteristics of the process quality and/or product quality.
One of the capabilities provided by the IC fabrication system 900 may enable collaboration and information access in such areas as design, engineering, and processing, metrology, and advanced processing control. Another capability provided by the IC fabrication system 900 may integrate systems between facilities, such as between the metrology tool and the processing tool. Such integration enables facilities to coordinate their activities. For example, integrating the metrology tool and the processing tool may enable manufacturing information to be incorporated more efficiently into the fabrication process or the APC module, and may enable wafer data from the online or in site measurement with the metrology tool integrated in the associated processing tool.
The method 1000 includes a step 1020 to form a p-dipole dopant source layer over the second gate dielectric layer but not over the first gate dielectric layer.
The method 1000 includes a step 1030 to perform a dipole drive-in process. Atoms of the p-dipole dopant source layer are driven into the second gate dielectric layer by the dipole drive-in process, such that the second gate dielectric layer becomes doped.
The method 1000 includes a step 1040 to remove the p-dipole dopant source layer after the dipole drive-in process has been performed.
The method 1000 includes a step 1050 to deposit an aluminum-free conductive layer over at least one of the first gate dielectric layer or the second gate dielectric layer after the removing of the p-dipole dopant source layer.
In some embodiments, the step 1050 comprises depositing a first aluminum-free conductive layer that circumferentially wraps around the first gate dielectric layer in a cross-sectional side view and depositing a second aluminum-free conductive layer that circumferentially wraps around the second gate dielectric layer in the cross-sectional side view. In some embodiments, a gate electrode layer is formed that circumferentially wraps around both the first aluminum-free conductive layer and the second aluminum-free conductive layer in the cross-sectional side view, where the gate electrode layer contains an n-type work function metal.
In some embodiments, the step 1050 comprises depositing the aluminum-free conductive layer that circumferentially wraps around the first gate dielectric layer but not over the second gate dielectric layer in a cross-sectional side view. In some embodiments, a gate electrode layer is formed that circumferentially wraps around both the aluminum-free conductive layer and the second gate dielectric layer in the cross-sectional side view, where the gate electrode layer contains an n-type work function metal.
In some embodiments, the step 1050 comprises depositing the aluminum-free conductive layer that circumferentially wraps around the second gate dielectric layer but not over the first gate dielectric layer in a cross-sectional side view. In some embodiments, a gate electrode layer is formed that circumferentially wraps around both the aluminum-free conductive layer and the first gate dielectric layer in the cross-sectional side view, where the gate electrode layer contains an n-type work function metal.
In some embodiments, the step 1050 comprises depositing a titanium nitride layer as the aluminum-free conductive layer.
In some embodiments, the first channel component and the first gate dielectric layer are portions of a first n-type transistor, and the second channel component and the second gate dielectric layer are portions of a second n-type transistor. In some embodiments, a first p-type transistor is formed over the first n-type transistor, a second p-type transistor is formed over the second n-type transistor, a third gate dielectric layer is formed over a third channel component of a first p-type transistor, and a fourth gate dielectric layer is formed over a fourth channel component of the second p-type transistor.
It is understood that the method 1000 may include further steps performed before, during, or after the steps 1010-1050. For example, the method 1000 may include a step of forming an n-type metal gate electrode that circumferentially surrounds the first n-type transistor, the second n-type transistor, the first p-type transistor, and the second p-type transistor in a cross-sectional side view. The method 1000 may further include a step of removing portions of the n-type metal gate electrode that circumferentially surrounds the first p-type transistor and the second p-type transistor. The method 1000 may also include a step of forming a p-type metal gate electrode over a remaining portion of the n-type metal gate electrode. The p-type metal gate electrode circumferentially surrounds both the first p-type transistor and the second p-type transistor in the cross-sectional side view. As another example, the method 1000 may further include a step of forming an n-type metal gate electrode that circumferentially surrounds both the first n-type transistor and the second n-type transistor, but not the first p-type transistor or the second p-type transistor, in a cross-sectional side view. The method 1000 may also include a step of forming a p-type metal gate electrode that circumferentially surrounds both the first p-type transistor and the second p-type transistor in the cross-sectional side view. The p-type metal gate electrode is formed over the n-type metal gate electrode. For reasons of simplicity, other additional steps are not discussed herein in detail.
In summary, the present disclosure involves implementing an aluminum-free conductive layer between the gate dielectric layer and the metal gate electrode of NFET devices. The aluminum-free conductive layer may include a conductive material (other than aluminum) that is configured to block aluminum diffusion. In some embodiments, the aluminum-free conductive layer is implemented for both a dipole drive-in device and a counterpart device. In some other embodiments, the aluminum-free conductive layer is implemented for just the dipole drive-in device but not for the counterpart device. In yet other embodiments, the aluminum-free conductive layer is implemented for just the counterpart device but not for the dipole drive-in device. In some embodiments, the aluminum-free conductive layer is implemented for NFET devices but not for PFET devices that are formed in a same vertical stack as the NFET device, for example, as a part of a CFET.
The embodiments of the present disclosure offer advantages over conventional CFET devices. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is the reduction in aluminum diffusion. In more detail, aluminum is commonly used as a dipole material to provide the tuning of different threshold voltages for different transistors. However, n-type work function metal layers may also include aluminum. If a gate dielectric layer that is not intended to be doped with aluminum is in direct contact with an aluminum-containing n-type work function metal layer, then undesirable aluminum diffusion could occur between the gate dielectric layer and the n-type work function metal layer of the metal gate electrode. This undesirable diffusion could adversely interfere with the threshold voltage tuning, and/or lead to insufficient differences between threshold voltages between a drive-in transistor and a counterpart transistor. Here, the insertion of the aluminum-free conductive layer between the gate dielectric layers and the aluminum-containing metal gate electrode (e.g., the aluminum-containing work function metal layer) helps reduce or eliminate the undesirable aluminum diffusion. As a result, the devices fabricated according to the present disclosure can still achieve their intended tuning of threshold voltages, thereby improving device performance. Other advantages include compatibility with existing fabrication processes and the ease and low cost of implementation.
One aspect of the present disclosure pertains to a device. The device includes a first n-type transistor and a second n-type transistor. The first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. The second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.
Another aspect of the present disclosure pertains to a device. The device includes a first vertical stack of transistors. The first vertical stack of transistors includes a first n-type transistor and a first p-type transistor. The device includes a second vertical stack of transistors. The second vertical stack of transistors includes a second n-type transistor and a second p-type transistor. The first n-type transistor and the first p-type transistor include undoped gate dielectric layers. The second n-type transistor and the second p-type transistor include doped gate dielectric layers. At least one of the first n-type transistor or the second n-type transistor, but not the first p-type transistor or the second p-type transistor, is circumferentially surrounded by an aluminum-free conductive layer. An n-type metal gate electrode circumferentially surrounds the aluminum-free conductive layer.
Another aspect of the present disclosure pertains to a method. A first gate dielectric layer is formed over a first channel component, and a second gate dielectric layer is formed over a second channel component. The first gate dielectric layer and the second gate dielectric layer are each undoped. A p-dipole dopant source layer is formed over the second gate dielectric layer but not over the first gate dielectric layer. A dipole drive-in process is performed. Atoms of the p-dipole dopant source layer are driven into the second gate dielectric layer by the dipole drive-in process, such that the second gate dielectric layer becomes doped. The p-dipole dopant source layer is removed after the dipole drive-in process has been performed. An aluminum-free conductive layer is deposited over at least one of the first gate dielectric layer or the second gate dielectric layer after the removing of the p-dipole dopant source layer.
The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
The present application is a utility patent application of provisional U.S. Patent Application No. 63/491,294, filed on Mar. 21, 2023, and entitled “NFET THRESHOLD VOLTAGE TUNING OF ALUMINUM-BASED P-DIPOLES”, the disclosure of which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63491294 | Mar 2023 | US |
