Tile for an active electronically scanned array (AESA)

Abstract
In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.
Description
BACKGROUND

As is known in the art, a phased array antenna includes a plurality of active circuits spaced apart from each other by known distances. Each of the active circuits is coupled through a plurality of phase shifter circuits, amplifier circuits and/or other circuits to either or both of a transmitter and receiver. In some cases, the phase shifter, amplifier circuits and other circuits (e.g., mixer circuits) are provided in a so-called transmit/receive (T/R) module and are considered to be part of the transmitter and/or receiver.


The phase shifters, amplifier and other circuits (e.g., T/R modules) often require an external power supply (e.g., a DC power supply) to operate correctly. Thus, the circuits are referred to as “active circuits” or “active components.” Accordingly, phased array antennas which include active circuits are often referred to as “active phased arrays.” An active phased array radar is also known as an active electronically scanned array (AESA).


Active circuits dissipate power in the form of heat. High amounts of heat can cause active circuits to be inoperable. Thus, active phased arrays should be cooled. In one example heat-sink(s) are attached to each active circuit to dissipate the heat.


SUMMARY

In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.


The aspect above may have one or more of the following features. The RF signal path through the oxide-bonded wafers may include a third portion that propagates away from the beam former. The RF signal path further may include a third path that extends into the beam former and out of the beam former. The oxide-bonded wafers may be fused silica. The oxide-bonded wafers may include metal posts wherein a metal post from one wafer may be connected to a metal post of another wafer. The beam former may include at least one of a phase shifter, an amplifier or an application-specific integrated circuit (ASIC). The beam former may be fabricated on silicon germanium (SiGe) wafer. The radiator structure may provide radiation shielding for the beam former. The RF manifold may propagate RF signals and not propagate any DC signals. The beam former may include a redistribution layer to allow for surface mounting to a printed circuit board. Power, signal and RF may be routed from the PWB through the beam former by a wafer via. The oxide-bonded semiconductor wafers may be made of high resistivity silicon. The RF signal may be routed using at least one of a stripline, a coplanar waveguide (CPW), a buried microstrip and a coaxial RF structure. The tile may include time delay structures and filtering structures. Active element spacing fits within Lambda/2 to enable wide scan to 60 degrees. The number of active elements between sixteen to sixty-four active elements. The tiles are scalable to an N×N array of active elements where N>1.





DESCRIPTION OF THE DRAWINGS


FIG. 1 is a diagram of one example of an array of active electronically scanned array (AESA) disposed on a mobile platform.



FIG. 2 is a diagram of an example of the AESA.



FIG. 3 is a cross-sectional view of an example of the AESA with a tile.



FIG. 4 is a cross-sectional view of an example of two oxide-bonded wafers.



FIG. 5 is a diagram of an example of a radio frequency (RF) manifold.





DETAILED DESCRIPTION

Described herein is a millimeter-wave radio frequency (RF) tile used as an active electronically scanned array (AESA) and scalable to form larger N×N AESA, for example. The tile, as described herein, incorporates a low loss glass RF manifold that is wafer level bonded directly to the beamforming circuit and a radiation shielding radiator.


As is understood in the art, higher frequencies require tighter lattice spacing between the active elements, which leaves less room for the active circuitry. This becomes even tighter when lambda/2 (half wavelength at transmitted frequency) spacing is required for a wide scan angle. The tile structures described herein enable signals to traverse a Z-axis using vias, for example, thereby allowing for higher frequencies such as Ka band and above to be achieved. One or more tiles may be mounted to a printed circuit board, which enables scalability. For example, the tile provides high density RF packaging and interconnects. In one example, the tile includes an RF-only manifold in a low-loss fused silica. In one example, the tile provides beam former functionality in silicon germanium (SiGe) and the SiGe beam former may be placed in close proximity to a coolant to provide thermal management. In one example, an RF radiator may also provide shielding of the SiGe beam former, for example, from radiation effects. In other examples, the beam former may be fabricated in other semiconductors such as high resistivity silicon, silicon carbide, gallium arsenide and so forth. In other examples, other functionality may be included in the RF manifold layer such as filtering and time delay. In one example, time delay functionality includes routing longer trace lengths to delay a signal. These other functions may be added into additional wafers incorporated in the stack.


Referring to FIG. 1, an AESA may be used in a number of applications. For example, as shown in FIG. 1, an array 12 of AESA 100 may be used in a mobile environment such as in a mobile platform unit 10. In this example, the AESA 100 are arranged in a 4×4 array. Though FIG. 1 depicts AESA 100 that are in a shape of a rectangle, the AESA 100 may be constructed to be a circle, triangle or any polygon shape. Also, though the array 12 is in a shape of a square the array may be a rectangle, circle, triangle or any polygon arrangement. Further, the number of AESA 100 may be one to any number of AESA 100.


In other applications, one or more AESA 100 may be used on the side of naval vessels, on ground structures, ground vessels, air vessels, space vessels and so forth. In one particular example, AESA 100 may be placed on a stellar or planetary probe. As will be shown herein, an AESA 100 is a “building block” for forming an AESA system that is modular and scalar. In one particular example, the AESA 100 is a millimeter-wave AESA.


Referring to FIG. 2, in one particular example, the AESA 100 includes an array of tiles 200 (e.g., a 9×9 array of tiles 200). The tiles 200 are also known as “known good tiles” (KGT). The AESA 100 also includes a cooling plate 204 and a printed circuit board (PCB) 206. In one example, each tile 200 is attached to the PCB 206, which is cooled by the cold plate 204. Each tile 200 includes active elements 222 that transmit and receive signals. In one example, the active elements 222 are arranged in an 8×8 array. As will be further described herein, the tiles 200 are fabricated from a stack of oxide-bonded wafers, which are interconnected using radio frequency direct bond hybridization (RF-DBH) and through wafer vias.


Referring to FIG. 3, the tile 200 includes wafers (e.g., a wafers 304a, a wafer 304b, a wafer 304c and a wafer 304d), a beam former 312 and a radiator/shielding structure 324. The wafers 304a-304d are oxide bonded. For example, an oxide 306a of the wafer 304a is bonded with the oxide 306b of the wafer 304b, an oxide 306c of the wafer 304b is bonded with the oxide 306d of the wafer 304c and an oxide 306e of the wafer 304c is bonded with the oxide 306f of the wafer 304d. Oxide is also used to bond the beam former 312 to the wafer stack (e.g., an oxide 306g on the wafer 304d is bonded with an oxide 306h of the beam former 312).


An RF manifold 320 is disposed within the wafers 304a-304d. In one particular example, the RF manifold is in the middle of the wafers 304a-304d as depicted in FIG. 3, but may be located in other wafers than shown in FIG. 3. The RF manifold 320 functions as an RF combiner/divider. For example, with sixty-four active elements the manifold would be a 64:1 RF combiner/divider. In one example, within the wafers 304a-304d the manifold 320 routes only RF signals and, in particular, there is no routing of DC power or control signals in the wafers 304a-304d. The manifold 320 extends in the XY-Plane (i.e., into the FIG. 3) and an example of the manifold 320 is depicted in the XY plane in FIG. 5. In one example, the manifold 320 includes layers that are made of high resistivity silicon.


In one example, the wafers 304a-304d are fused silica wafers. In one particular example, each silica wafer is 100 microns thick. In one particular example, the fused silica is a low loss fused silica, where k=3.82 and the loss tangent is equal to 0.0007 at 60 GHz. In one example, the wafers 304a-304d may be low loss, high resistivity silicon. In further examples, wafers 304a-304d may be more or less than four wafers.


Vias are used to provide an electrical path through the tile 200. For example, the wafer 304a includes vias (e.g., a via 308a and a via 308b), the wafer 304b includes vias (e.g., a via 308c and a via 308d), the wafer 304c includes vias (e.g., a via 308e, a via 308f, a via 308g, a via 308h, and a via 308i) and the wafer 304d includes vias (e.g., a via 308j, a via 308k, a via 308l, a via 308m, and a via 308n).


Vias may be connected to metal traces which are connected to metal posts. For example, the wafer 304a includes a metal post 313 and a metal trace 314. As further described in FIG. 4, the metal posts provide electrical connectivity from one wafer to another wafer.


The oxide-bonded wafers 304a-304d include metallization layers used for electrical interconnections. In one example, metal layer 310a provides an interconnect between via 308j and via 308k. In another example, the oxide 306h includes metal layer interconnect 310b providing an electrical connection between the via 308f, the via 308g and the via 308h. In a further example, the oxide 306h includes an interconnect 310c providing an electrical connection between the via 308m and the via 308n. The via 308 connects the metal on both sides of a wafer 304 and the interconnect between metal pads on the wafer are made during oxide bonding with the metal post shown in metal post 313.


The beam former 312 includes at least one control application-specific integrated circuit ASIC (e.g., an ASIC 340), amplifiers (e.g., an amplifier 344a and an amplifier 344b) and phase shifters (e.g., a phase shifter 346a and a phase shifter 346b). In one example, the beam former 312 is fabricated on a silicon germanium (SiGe) wafer. In other examples, the beam former 312 provides RF attenuation and RF switches.


The beam former 312 also includes backside redistribution layers (RDL) (e.g., RDLs 348a) which includes interconnect pads, 348b to enable attachment to the PCB 206 using standard surface mount technology. The beam former 312 is attached to the PCB 206 by solder bumps (e.g., solder bumps 350a-350e). In one example, the solder bump 350a carries control signals, the solder bumps 350b, 350d are attached to ground, the solder bump 350c carries RF signals and the solder bump 350e carries power.


The radiator/shielding structure 324 is bonded to the wafers by a metal interconnect. In one example, the interconnect may be a solder bumps. In another example, it could be an indium bump. For example, the radiator/shielding structure 324 is bonded to the vias 308a of the wafer 304a by a solder bumps 380a and the radiator/shielding structure 324 is bonded to the vias 308b of the wafer 304a by a solder bumps 380a. In one example, the radiator/shielding structure 324 is designed to propagate an RF signal through the radiator and provide a radiation shield for the beam former 312. In one example, the radiator is made of a metal with low coefficient of expansion like invar to lessen the stress of connection to the wafer stack and thick enough to provide the correct amount of radiation shielding.


In one particular example, an RF signal path 370 starts at the radiator/shielding structure 324 and continues through connection 380b, the via 308b of the wafer 304a, through the via 308d of the wafer 304b, through the via 308i of the wafer 304c and through the via 308n of the wafer 304d. The RF signal path 370 continues in the beam former 312 by going through the amp 344b and the phase shifter 346. The RF signal path 370 continues back away from the beam former 312 and into the wafers 304c, 304d by going through the via 308m of the wafer 304d, through the via 308h of the wafer 304c. The RF signal path 370 continues through the interconnect 310b through the via 308g of the wafer 304c, through the via 308i of the wafer 304d. The RF signal path 370 propagates back into the beam former 312 and through the via 304c to the PCB 206 through bump 350c.


The RF signal path 370 moves in at least two axes within the wafers. For example, the RF signal path 370 moves along two axes (e.g., it moves along the X-axis and the Z-axis (i.e., in an X-Z plane)). In other examples, the RF signal path 370 may also move in the Y-axis (not shown in FIG. 3, but depicted in FIG. 5). In other examples, the RF signal path may flow in opposite direction to the RF signal path 370. Other RF signal paths are not limited by the RF signal path 370. That is, other RF signal paths and combinations are possible and that the RF signal path 370 is just one example of the many RF signal paths possible in FIG. 3.



FIG. 4 depicts one example of two wafers that are oxide bonded, for example, in a manner that the oxide-bonded wafers 304a-304d are configured. For example, an oxide 406a of a wafer 404a is bonded to an oxide 406b of a wafer 404b. In one example, the oxide bond is a molecular bond formed at room temperature. The DBH includes metal posts such as a post 412a of the wafer 404a bonded to a post 412c of the wafer 404b and a post 412b of the wafer 404a bonded to a post 412d of the wafer 404b. In one example, the posts 412a-412d are made of metal. In one particular example, the posts 412a-412d are copper posts. In another particular example, the posts 412a-412d are nickel posts. In a further particular example, the posts 412a-412d are aluminum posts. In one example the posts 412a-412d have less than 10 microns of pitch capability.


Posts may be connected by a metal trace layer (e.g., post 412c is connected to a post 412d by a metal trace layer 414). The metal trace layer may be connected to vias (e.g., the metal trace layer 414 is connected to the via 408). In one example, the via 408 may be about 25 microns in diameter. In one example, the via 408 may be a copper via.



FIG. 5 depicts an example of the RF manifold 320, an RF manifold 520 in an X-Y plane, for example. In this example, the RF manifold 520 is a 16:1 RF combiner/divider for sixteen elements (e.g., active elements 522a-522p). In one example, the RF manifold 520 is fabricated in wafers 304a-304d that are low loss, high resistivity silicon.


The processes described herein are not limited to the specific embodiments described. Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Other embodiments not specifically described herein are also within the scope of the following claims.

Claims
  • 1. An active electronically scanned array (AESA) tile comprising: a radiator structure; andoxide-bonded semiconductor wafers attached to the radiator structure and comprising a low loss glass radio frequency (RF) manifold and a beam former, wherein the RF manifold is not in direct contact with the beam former;wherein an RF signal path through the oxide-bonded semiconductor wafers comprises a first portion that propagates toward the beam former, a second portion that propagates parallel to the beam former, a third portion that propagates away from the beam former, and a fourth portion that extends into the beam former and out of the beam former;wherein the RF signal path moves along three axes,wherein the first portion, the third portion and the fourth portion of the RF signal move in a Z-axis direction,wherein the second portion of the RF signal moves in an X-axis direction, anda fifth portion of the RF signal moves in a Y-axis direction.
  • 2. The AESA tile of claim 1, wherein the oxide-bonded semiconductor wafers are fused silica.
  • 3. The AESA tile of claim 1, wherein the oxide-bonded semiconductor wafers comprise metal posts, and wherein a metal post from one wafer is connected to a metal post of another wafer.
  • 4. The AESA tile of claim 1, wherein the beam former comprises at least one of a phase shifter, an amplifier or an application-specific integrated circuit (ASIC).
  • 5. The AESA tile of claim 1, wherein the beam former is fabricated on silicon germanium (SiGe) wafer.
  • 6. The AESA tile of claim 1, wherein the radiator structure provides radiation shielding for the beam former.
  • 7. The AESA tile of claim 1, wherein the RF manifold propagates RF signals and no DC signals.
  • 8. The AESA tile of claim 1, wherein the beam former includes a redistribution layer to allow for surface mounting to a printed circuit board.
  • 9. The AESA tile of claim 1, wherein power, signal and RF are routed from the PWB through the beam former by a wafer via.
  • 10. The AESA tile of claim 1, where the oxide-bonded semiconductor wafers are made of high resistivity silicon.
  • 11. The AESA tile of claim 1 where the RF signal is routed using at least one of a stripline, a coplanar waveguide (CPW), a buried microstrip and a coaxial RF structure.
  • 12. The AESA tile of claim 1, wherein the tile comprises time delay structures and filtering structures.
  • 13. The AESA tile of claim 1, further comprising active elements, wherein active element spacing fits within Lambda/2 to enable wide scan to 60 degrees.
  • 14. The AESA tile of claim 13, wherein the number of active elements between sixteen to sixty-four active elements.
  • 15. The AESA tile of claim 13, wherein the tiles are scalable to an N×N array of active elements where N>1.
  • 16. The AESA tile of claim 1 further comprising one or more time delay structures having a trace length selected to achieve a certain time delay.
  • 17. The AESA tile of claim 1 further comprising a cooling plate that is positioned to cool the beamformer.
  • 18. The AESA tile of claim 1 wherein the oxide-bonded semiconductor wafers are a stack of oxide-bonded wafers that are interconnected using RF direct bond hybridization (RF-DBH) and wafer vias.
  • 19. The AESA tile of claim 1 wherein the fifth portion of the RF signal moves in the Y-axis direction in the RF manifold.
US Referenced Citations (92)
Number Name Date Kind
2015028 Gillete Sep 1935 A
3528050 Hindenburg Sep 1970 A
4690471 Marabotto et al. Sep 1987 A
5172082 Livingston et al. Dec 1992 A
5410281 Blum Apr 1995 A
5434575 Jelinek et al. Jul 1995 A
5453751 Tsukamoto et al. Sep 1995 A
5455546 Frederick et al. Oct 1995 A
5603620 Hinze et al. Feb 1997 A
5644277 Gulick et al. Jul 1997 A
5745079 Wang et al. Apr 1998 A
5880694 Wang et al. Mar 1999 A
5886590 Quan et al. Mar 1999 A
5995047 Freyssinier et al. Nov 1999 A
6100775 Wen Aug 2000 A
6114997 Lee et al. Sep 2000 A
6147648 Granholm et al. Nov 2000 A
6184832 Geyh et al. Feb 2001 B1
6320542 Yamamoto et al. Nov 2001 B1
6429816 Whybrew et al. Aug 2002 B1
6459415 Pachal et al. Oct 2002 B1
6512487 Taylor et al. Jan 2003 B1
6664867 Chen Dec 2003 B1
6686885 Barkdoll et al. Feb 2004 B1
6856297 Durham et al. Feb 2005 B1
6867742 Irion et al. Mar 2005 B1
6876336 Croswell et al. Apr 2005 B2
6882247 Allison et al. Apr 2005 B2
6935866 Kerekes et al. Aug 2005 B2
6977623 Durham et al. Dec 2005 B2
7012572 Schaffner et al. Mar 2006 B1
7084827 Strange et al. Aug 2006 B1
7113142 McCarville et al. Sep 2006 B2
7132990 Stenger et al. Nov 2006 B2
7138952 Mcgrath et al. Nov 2006 B2
7193390 Shimoda Mar 2007 B2
7221322 Durham et al. May 2007 B1
7272880 Pluymers et al. Sep 2007 B1
7315288 Livingston et al. Jan 2008 B2
7358921 Snyder et al. Apr 2008 B2
7411472 West et al. Aug 2008 B1
7414590 Bij De Vaate et al. Aug 2008 B2
7688265 Irion et al. Mar 2010 B2
7948441 Irion et al. May 2011 B2
8035992 Kushta et al. Oct 2011 B2
8325093 Holland et al. Dec 2012 B2
8753145 Lang et al. Jun 2014 B2
9136572 Carr et al. Sep 2015 B2
9402301 Paine et al. Jul 2016 B2
9437929 Isom et al. Sep 2016 B2
9490519 Lilly et al. Nov 2016 B2
9537208 Isom Jan 2017 B2
20030020654 Navarro et al. Jan 2003 A1
20030112200 Marino Jun 2003 A1
20030184476 Sikina et al. Oct 2003 A1
20050007286 Trott et al. Jan 2005 A1
20050156802 Livingston et al. Jul 2005 A1
20060097947 McCarville et al. May 2006 A1
20080036665 Schadler Feb 2008 A1
20080150832 Ingram Jun 2008 A1
20080169992 Ortiz et al. Jul 2008 A1
20090073075 Irion et al. Mar 2009 A1
20090091506 Navarro et al. Apr 2009 A1
20090121967 Cunningham May 2009 A1
20100164783 Choudhury Jul 2010 A1
20110089531 Hillman et al. Apr 2011 A1
20120034820 Lang et al. Feb 2012 A1
20120068906 Asher et al. Mar 2012 A1
20120098706 Lin et al. Apr 2012 A1
20120146869 Holland et al. Jun 2012 A1
20120212386 Massie et al. Aug 2012 A1
20120287581 Sauerbier et al. Nov 2012 A1
20120306698 Warnick et al. Dec 2012 A1
20120313818 Puzella et al. Dec 2012 A1
20130026586 Seok et al. Jan 2013 A1
20130050055 Paradiso et al. Feb 2013 A1
20130175078 Pai Jul 2013 A1
20130187830 Warnick et al. Jul 2013 A1
20130194754 Jung et al. Aug 2013 A1
20130207274 Liu et al. Aug 2013 A1
20130314292 Maley Nov 2013 A1
20140132473 Isom May 2014 A1
20140264759 Koontz Sep 2014 A1
20150015453 Puzella Jan 2015 A1
20150200460 Isom et al. Jul 2015 A1
20150353348 Vandemeer Dec 2015 A1
20160172755 Chen Jun 2016 A1
20160352023 Dang et al. Dec 2016 A1
20180040955 Vouvakis et al. Feb 2018 A1
20180090851 Feldman et al. Mar 2018 A1
20180337461 Kildal et al. Nov 2018 A1
20190044234 Isom Feb 2019 A1
Foreign Referenced Citations (17)
Number Date Country
103247581 Aug 2013 CN
204857954 Dec 2015 CN
1 970 952 Sep 2008 EP
1 970 952 Sep 2008 EP
U-1992027609 Mar 1992 JP
H07-106841 Apr 1995 JP
2000-312112 Nov 2000 JP
2006504375 Feb 2006 JP
6195935 Sep 2017 JP
2014-03765 Jan 2014 TW
2014-34203 Sep 2014 TW
2016-05017 Feb 2016 TW
WO 2009077791 Jun 2009 WO
WO 2014168669 Oct 2014 WO
WO 2015006293 Jan 2015 WO
WO 2016138267 Sep 2016 WO
WO 2016138267 Sep 2016 WO
Non-Patent Literature Citations (87)
Entry
Response to U.S. Non-Final Office Action dated May 18, 2017 for U.S. Appl. No. 14/881,582, filed Jun. 5, 2017; 7 Pages.
PCT International Search Report and Written Opinion dated Dec. 8, 2017 for International Application No. PCT/US2017/054836; 15 Pages.
PCT International Search Report and Written Opinion dated Jan. 3, 2018 for International Application No. PCT/US2017/055059; 17 Pages.
PCT International Search Report and Written Opinion dated Jan. 3, 2018 for International Application No. PCT/US2017/055222; 16 Pages.
Luo et al.; “Meander Line Coupled Cavity-Backed Slot Antenna for Broadband Circular Polarization”; IEEE Antennas and Wireless Propagation Letters; vol. 14; Feb. 2, 2015; 4 Pages.
U.S. Non-Final Office Action dated Apr. 5, 2018 for U.S. Appl. No. 15/379,761; 20 pages.
U.S. Non-Final Office Action dated Apr. 5, 2018 for U.S. Appl. No. 15/379,775; 16 pages.
Japanese Office Action dated Feb. 28, 2017 for Japanese Pat. App. No. 2015-541757 with English Translations; 4 Pages.
U.S. Appl. No. 14/881,582, dated Oct. 2015, Viscarra et al.
Non-Final Office Action dated Jun. 8, 2015 for U.S. Appl. No. 13/674,547; 23 pages.
Response to Office Action dated Jun. 8, 2015 for U.S. Appl. No. 13/674,547, filed Aug. 8, 2015; 18 pages.
U.S. Final Office Action dated Dec. 3, 2015 for U.S. Appl. No. 13/674,547; 22 Pages.
Non-Final Office Action dated Apr. 7, 2016 for U.S. Appl. No. 13/674,547; 27 Pages.
Response to Final Office Action dated Dec. 3, 2015 for U.S. Appl. No. 13/674,547, filed Feb. 22, 2016; 16 Pages.
Response to Office Action dated Apr. 7, 2016 for U.S. Appl. No. 13/674,547, filed Jun. 21, 2016; 16 Pages.
U.S. Final Office Action dated Jul. 1, 2016 for U.S. Appl. No. 13/674,547; 30 Pages.
Response to U.S Final Office Action dated Jul. 1, 2016 for U.S. Appl. No. 13/674,547, filed Aug. 18, 2016; 14 Pages.
Notice of Allowance dated Sep. 16, 2016 for U.S. Appl. No. 13/674,547; 17 Pages.
PCT International Search Report and Written Opinion for PCT/US2013/038408 dated Jun. 28, 2013; 14 Pages.
PCT International Preliminary Report on Patentability for PCT/US2013/038408 dated May 21, 2015; 9 Pages.
European 161/162 Communication for Application No. 13721516.6 dated Jul. 9, 2015; 2 Pages.
Response (with Amended Claims) to European 161/162 Communication dated Jul. 9, 2015, for Application No. 1372156.6: Response filed on Jan. 19, 2016; 34 Pages.
Korean Office Action (with English Translation) dated Feb. 27, 2016 for Application No. 10-2015-7010618; 4 Pages.
Response (with Foreign Associate Reporting Letter) to Korean Office Action dated Feb. 27, 2016 for Application No. 10-2015-7010618; Response filed on Apr. 27, 2016; 15 Pages.
Japanese Office Action (with English Translation) dated Jun. 21, 2016 for Application No. 2015-541757; 8 Pages.
Response (with Foreign Associate Reporting Letter) to Japanese Office Action dated Jun. 21, 2016, for Application No. 2015-2015-541757; Response filed on Sep. 21, 2016; 7 Pages.
PCT International Search Report and Written Opinion for PCT/US2016/034045 dated Aug. 30, 2016; 11 Pages.
Hotte et al., “Directive and high-efficiency slotted waveguide antenna array for V-band made by wire electrical discharge machining;” Electronic Letter vol. 51, No. 5; Mar. 5, 2015 ; 2 Pages.
Kasemodel et al., “Broadband Array Antenna Enhancement With Spatially Engineered Dielectrics;” U.S. Appl. No. 13/590,769, filed Aug. 21, 2012; 19 Pages.
Kasemodel et al., “Broadband Planar Wide-Scan Array Employing Tightly Coupled Elements and Integrated Balun;” Proceedings of the 2010 IEEE International Symposium on Phased Array Systems and Technology; Oct. 12-15, 2010; 6 Pages.
Kindt et al., “Polarization Correction in Dual-Polarized Phased Arrays of Flared Notches;” Proceedings of the 2011 IEEE International Symposium on Antennas and Propagation (APSURSI); Jul. 3-8, 2011; 4 Pages.
Mishra et al., “Array of SIW Resonant Slot Antenna for V Band Applications;” Proceedings of the 2013 IEEE International Conference on Microwave and Photonics (ICMAP); Dec. 13-15, 2013; 4 Pages.
Nesic et al., “Wideband Printed Antenna With Circular Polarization;” Proceedings of 1997 IEEE Antennas and Propagation Society International Symposium; Jul. 13-18, 1997; 4 Pages.
Wong et al., “Broad-Band Single-Patch Circularly Polarized Microstrip Antenna with Dual Capacitively Coupled Feeds;” Proceedings of the 2001 IEEE Transactions on Antennas and Propagation, vol. 49, No. 1; Jan. 2001; 4 Pages.
Wong et al., “Design of Dual-Polarized L-Probe Patch Antenna Arrays with High Isolation;” Proceedings of 2004 IEEE Transactions on Antennas and Propagation, vol. 50, No. 1; Jan. 2004; 8 Pages.
Wu et al., “A Wideband High-Gain High-Efficiency Hybrid Integrated Plate Array Antenna for V-Band Inter-Satellite Links;” Proceedings of 2015 IEEE Transactions on Antennas and Propagation, vol. 63, No. 4; Apr. 2015; 9 Pages.
PCT International Preliminary Report and Written Opinion dated Apr. 26, 2018 for International Application No. PCT/US2016/034045; 8 Pages.
U.S. Non-Final Office Action dated May 18, 2017 for U.S. Appl. No. 14/881,582; 21 Pages.
Notice of Allowance dated Jun. 23, 2017 for U.S. Appl. No. 14/881,582; 8 Pages.
Response to U.S. Non-Final Office Action dated Apr. 5, 2018 for U.S. Appl. No. 15/379,761, filed Aug. 1, 2018; 23 Pages.
Response to U.S. Non-Final Office Action dated Apr. 5, 2018 for U.S. Appl. No. 15/379,775, filed Aug. 1, 2018; 17 Pages.
Response (with English Translation of Response, Current Claims and Amended Specification) to Taiwan Office Action dated Jun. 19, 2018 for Taiwan Application No. 106135418; Response filed on Sep. 12, 2018; 40 Pages.
U.S. Final Office Action dated Sep. 14, 2018 for U.S. Appl. No. 15/379,761; 20 Pages.
U.S. Final Office Action dated Sep. 21, 2018 for U.S. Appl. No. 15/379,775; 19 Pages.
Taiwan Office Action (with Search Report) dated Jun. 19, 2018 for Taiwan Application No. 106135418; 18 pages.
Taiwan Examination Report (with English Translation) dated Oct. 31, 2018 for Taiwan Application No. 106135617; 23 Pages.
Taiwan Examination Report (with English Translation) dated Nov. 2, 2018 for Taiwan Application No. 106135613; 20 Pages.
Response to U.S. Final Office Action dated Sep. 14, 2018 for U.S. Appl. No. 15/379,761, filed Dec. 14, 2018; 11 Pages.
Response to U.S. Final Office Action dated Sep. 21, 2018 for U.S. Appl. No. 15/379,775, filed Dec. 21, 2018; 13 Pages.
Taiwan Examination Report (with English Translation) dated Nov. 26, 2018 for Taiwan Application No. 106135418; 8 Pages.
U.S. Non-Final Office Action dated Jan. 11, 2019 for U.S. Appl. No. 15/379,761; 20 Pages.
U.S. Non-Final Office Action dated Jan. 14, 2019 for U.S. Appl. No. 15/379,775; 22 Pages.
Response (with English Translation, Claims and Specification) to Taiwan Examination Report dated Oct. 31, 2018 for Taiwan Application No. 106135617; Response filed Jan. 7, 2019; 22 Pages.
Response (with English Translation and Specification) to Taiwan Examination Report dated Nov. 2, 2018 for Taiwan Application No. 106135613; Response filed Jan. 8, 2019; 9 Pages.
Taiwan Statement of Reasons for Re-Examination (with Reporting Letter dated Jan. 8, 2019 and English Translation) dated Jan. 8, 2019 for Taiwan Application No. 106135418; 7 Pages.
Chang-Chien et al., “MMIC Compatible Wafer-Level Packaging Technology;” Proceedings of the International Conference on Indium Phosphide and Related Materials (19th IPRM); May 14-18, 2007; 4 Pages.
Chang-Chien et al., “MMIC Packaging and Heterogeneous Integration Using Wafer-Scale Assembly;” Proceedings of the CS MANTECH Conference; May 14-17, 2007; 4 Pages.
Chang-Chien, “Wafer-Level Packaging and Wafer-Scale Assembly Technologies;” Presentation by Northrop Grumman Aerospace Systems (NGAS); Proceedings of the CS MANTECH Workshop 6; May 17, 2010; 43 Pages.
Green, “DARPA's Heterogeneous Integration Vision and Progress on Modular Design;” Presentation by DARPA; Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference (ASIP); Dec. 17, 2015; 17 Pages.
Gu et al., “W-Band Scalable Phased Arrays for Imaging and Communications;” Integrated Circuits for Communications, IEEE Communications Magazine; Apr. 2015; 9 Pages.
Popovic, “Micro-coaxial Micro-fabricated Feeds for Phased Array Antennas;” Proceedings of the 2010 IEEE International Symposium on Phased Array Systems and Technology (ARRAY); Oct. 12-15, 2010; 10 Pages.
Shin et al., “A 108-114 GHz 4x4 Wafer-Scale Phased Array Transmitter with High-Efficiency On-Chip Antennas;” IEEE Journal of Solid-State Circuits, vol. 48, No. 9; Sep. 2013; 15 Pages.
Urteaga, “3D Heterogeneous Integration of III-V Devices and Si CMOS;” Presentation by Teledyne Scientific Company; Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference (ASIP); Dec. 17, 2015; 26 Pages.
Zihir et al., “A 60 GHz 64-element Wafer-Scale Phased-Array with Full-Reticle Design;” Proceedings of the 2015 IEEE MTT-S International Microwave Symposium; May 17-22, 2015; 3 Pages.
Japanese Final Office Action (with English Translation) dated Feb. 28, 2017 for Japanese Application No. 2015-541757; 4 Pages.
European Examination Report dated Jun. 21, 2018 for European Application No. 13721516.6; 6 Pages.
Response to European Examination Report dated Jun. 21, 2018 for European Application No. 13721516.6; Response filed Oct. 26, 2018; 16 Pages.
U.S. Non-Final Office Action dated Oct. 9, 2018 for U.S. Appl. No. 15/731,906; 13 Pages.
Response to U.S. Non-Final Office Action dated Oct. 9, 2018 for U.S. Appl. No. 15/731,906, filed Nov. 16, 2018; 12 Pages.
U.S. Notice of Allowance dated Dec. 14, 2018 for U.S. Appl. No. 15/731,906; 9 Pages.
PCT International Search Report dated Apr. 26, 2018 for International Application No. PCT/US2018/015421; 15 Pages.
Tong et al., “Novel Sequential Rotation Technique for Broadband Circularly Polarized Microstrip Ring Anennas;” Proceedings of the 2008 Loughborough Antennas & Propagation Conference; Mar. 17, 2008; 4 Pages.
Taiwan Allowance Decision (with English Translation) dated Mar. 20, 2019 for Taiwan Application No. 106135613; 4 Pages.
U.S. Notice of Allowance dated Apr. 4, 2019 for U.S. Appl. No. 15/731,906; 5 Pages.
Response to U.S. Non-Final Office Action dated Jan. 14, 2019 for U.S. Appl. No. 15/379,775, filed Apr. 25, 2019; 10 Pages.
Response to U.S. Non-Final Office Action dated Jan. 11, 2019 for U.S. Appl. No. 15/379,761, filed May 13, 2019; 14 Pages.
Taiwan Examination Report and Search Report (with English Translation) dated Apr. 15, 2019 for Taiwan Application No. 106135617; 21 Pages.
PCT International Preliminary Report dated Jun. 27, 2019 for International Application No. PCT/US2017/055059; 13 Pages.
PCT International Preliminary Report dated Jun. 27, 2019 for International Application No. PCT/US2017/055222; 9 Pages.
Response (with Machine English Translation from Google Translator) to Taiwan Examination Report dated Apr. 15, 2019 for Taiwan Application No. 106135617; Response filed Jul. 4, 2019; 18 Pages.
PCT International Preliminary Report dated Jun. 27, 2019 for International Application No. PCT/US2017/054836; 9 Pages.
European Communication Pursuant to Rules 161(1) and 162 EPC dated Jul. 23, 2019 for European Application No. 17791226.8; 3 Pages.
European Communication Pursuant to Rules 161(1) and 162 EPC dated Jul. 23, 2019 for European Application No. 17784814.0; 3 Pages.
European Communication Pursuant to Rules 161(1) and 162 EPC dated Jul. 23, 2019 for European Application No. 17785128.4; 3 Pages.
Taiwan Allowance Decision (with English Translation) dated Aug. 30, 2019 for Taiwan Application No. 106135617; 4 Pages.
European Examination Report dated Sep. 9, 2019 for European Application No. 13721516.6; 4 Pages.
Taiwan Office Action (with English Translation) dated Sep. 20, 2019 for Taiwan Application No. 106135418; 14 Pages.
Related Publications (1)
Number Date Country
20180175476 A1 Jun 2018 US