Claims
- 1. A semiconductor device comprising:
a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate film; a gate dielectric formed on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body; and a gate electrode formed on said gate dielectric on said top of surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body.
- 2. The device of claim 1 wherein said semiconductor body is silicon.
- 3. The device of claim 1 wherein said semiconductor body is a single crystalline film.
- 4. The device of claim 2 wherein said semiconductor body is intrinsic single crystalline silicon.
- 5. The device of claim 1 wherein said semiconductor body is a semiconductor selected from the group consisting of silicon (Si) germanium (Ge), silicon germanium (SixGey), gallium arsenide (GaAs), InSb, GaP, GaSb as well as carbon nanotubes.
- 6. The semiconductor device of claim 1 wherein said substrate is an insulating substrate.
- 7. The semiconductor of claim 1 wherein said substrate is a semiconductor substrate.
- 8. A tri-gate transistor comprising:
a single crystalline silicon body formed on an insulating substrate, said silicon body having a top surface and first and second laterally opposite sidewalls; a gate dielectric formed on said top surface of said silicon body and on said first and second laterally opposite sidewalls of said silicon body; a gate electrode formed on said gate dielectric on said top surface of said silicon body and adjacent to said gate dielectric on said first and said second laterally opposite sidewalls of said silicon body; and a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrode.
- 9. The tri-gate transistor of claim 8 wherein said transistor has a gate length (Lg) approximately equal to the distance between said first and second laterally opposite sidewalls of said silicon body.
- 10. The tri-gate transistor of claim 8 wherein said transistor has a gate length (Lg) approximately equal to the distance from said insulating film to the top surface of said silicon body.
- 11. The tri-gate transistor of claim 8 wherein the distance between said laterally opposite sidewalls of said silicon body is approximately equal to the distance from said insulating substrate to the top surface of said silicon body.
- 12. The trigate transistor of claim 8 wherein the distance between said laterally opposite sidewalls of said semiconductor is between ½ to two times the thickness of said silicon body on said insulating surface.
- 13. The tri-gate transistor of claim 8 wherein said single crystalline silicon body is intrinsic silicon.
- 14. The tri-gate transistor of claim 8 wherein said single crystalline silicon body is doped to a first conductivity type with a concentration of between 1×1016-1×1020 atoms/cm3.
- 15. The tri-gate transistor of 14 wherein said single crystalline silicon body is doped to a first conductivity type with a concentration of 1×1016-1×1018 atoms/cm3.
- 16. The tri-gate transistor of claim 8 further comprising a pair of sidewall spacer formed along laterally opposite sidewalls of said gate electrode.
- 17. The tri-gate transistor of claim 8 wherein said pair of source/drain regions further comprise silicon formed on and around said silicon body.
- 18. The tri-gate transistor of claim 15 wherein said silicon on said source/drain regions is epitaxial silicon.
- 19. A transistor comprising:
a plurality of semiconductor bodies each having a top surface and a pair of laterally opposite sidewalls formed on a substrate film; a gate dielectric formed on the top surface and sidewalls of each of said semiconductor bodies; a gate electrode formed on the gate dielectric on the top surface of each of said plurality of semiconductor bodies and adjacent to said gate dielectrics formed on each of said first and second laterally opposite sidewalls of each of said silicon bodies; and a pair of source/drain regions formed in each of said semiconductor bodies on opposite sides of said gate electrode.
- 20. The transistor of claim 19 wherein said gate width of said transistor is approximately the sum of the gate widths of each of said semiconductor bodies wherein the gate width of a semiconductor body is two times the height of the semiconductor body plus the distances between the laterally opposite sidewalls.
- 21. The tri-gate transistor of claim 19 wherein the distance between the laterally opposite sidewalls of each of said silicon bodies is approximately the same.
- 22. The transistor of claim 19 wherein each of said source regions are coupled together and each of said drain regions are coupled together.
- 23. The transistor of claim 19 wherein said substrate is an insulating substrate.
- 24. The transistor of claim 19 wherein said substrate is a semiconductor substrate.
- 25. A fully depleted semiconductor on insulator transistor comprising:
a silicon body formed on an insulating film; a gate dielectric formed on and around said silicon body; a gate electrode formed on said gate dielectric on and around said silicon body; a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrodes; wherein said gate length of said transistor is less than or equal to the width of said silicon body; and when said transistor is turned “ON” said silicon body between said source/drain regions is fully depleted.
- 26. The transistor of claim 25 wherein said gate length is less than 60 nanometers.
- 27. The transistor of claim 25 wherein said gate length is less than 30 nanometers.
- 28. The transistor of claim 25 wherein said gate length is less than 20 nanometers.
- 29. The transistor of claim 25 wherein said gate length is less than or equal to the height of said semiconductor body on said insulating film.
- 30. The transistor of claim 25 wherein said semiconductor body is a single crystalline silicon film.
- 31. The transistor of claim 30 wherein said single crystralline silicon film is intrinsic silicon.
- 32. A fully depleted silicon on insulator transistor comprising:
a silicon body formed on an insulating substrate; a gate dielectric formed on and around said silicon body; a gate electrode formed on and adjacent to said gate dielectric formed on and around said silicon body; a pair of source/drain regions formed on opposite sides of said gate electrode in said silicon body; and wherein said transistor has a very sharp sub-threshold slope of less than 80 mV/decade and a drain induced barrier lowering of less than 100 mV/V.
- 33. The transistor of claim 32 wherein said drain induced barrier lowering is less than 80 mV/V.
- 33. The transistor of claim 32 wherein said sub-threshold slope is about 60 mV/decade.
- 35. A method of forming a semiconductor device comprising:
forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate film; forming a gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body; and forming a gate electrode on said gate dielectric and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body.
- 36. The method of claim 35 wherein said semiconductor body comprises single crystalline silicon.
- 37. The method of claim 36 wherein said single crystalline silicon body is intrinsic silicon.
- 38. The method of claim 35 wherein said semiconductor body is selected from the group consisting of silicon (Si) germanium (Ge), silicon germanium (SixGey), gallium arsenide (GaAs), InSb, GaP, GaSb as well as carbon nanotubes.
- 38. The method of forming the device of claim 35 wherein the thickness of said semiconductor body from said insulating film to said semiconductor body top surface is approximately equal to the distance between said laterally opposite sidewalls of said silicon body.
- 40. The method of claim 35 wherein the thickness of said silicon body from said insulating layer to said top surface is between two times to ½ the distance between the laterally opposite sidewalls.
- 41. The method of claim 35 wherein said substrate is an insulating substrate.
- 42. The method of claims 35 wherein said substrate is a semiconductor substrate.
- 43. A method of forming a silicon on insulator transistor comprising:
patterning a silicon film formed on an insulating substrate into a silicon body having a top surface opposite a bottom surface formed on said insulating film, and a first and second laterally opposite sidewalls; forming a gate dielectric layer on said top surface of said silicon body and on said sidewalls of said silicon body; depositing a gate material over said silicon body and over said insulating substrate; patterning said gate material to form a gate electrode on said gate dielectric layer on said top surface of said silicon body and adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to the laterally opposite sidewalls of said silicon body; and forming a pair of source/drain regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode.
- 44. The method of claim 43 wherein said distance between said laterally opposite sidewalls of said silicon body is approximately equal to the thickness of said silicon body on said insulating substrate.
- 45. The method of claim 43 wherein the distance between said laterally opposite sidewalls of said gate electrode (gate length) is less than or equal to the distance between laterally opposite sidewalls of said silicon body.
- 46. The method of claim 43 wherein the distance between said laterally opposite sidewalls of said gate electrode (gate length) is less than or equal to the thickness of said silicon body on said insulating film.
- 47. The method of claim 43 wherein said silicon film is single crystalline silicon.
- 48. The method of claim 47 wherein said single crystalline silicon film is intrinsic silicon.
- 49. The method of claim 43 further comprising forming a pair of sidewall spacers on opposite sides of laterally opposite sidewalls of said gate electrode; and
forming a silicon film on and around said silicon body and adjacent to said sidewall spacers.
- 50. The method of claim 43 further comprising forming a silicide on said silicon film formed on said silicon body.
- 51. The method of claim 43 wherein said silicon film is formed by a selective deposition process.
- 52. A semiconductor device comprising:
a semiconductor body having a top surface and a laterally opposite sidewall formed on a substrate; a gate dielectric formed on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body, wherein said gate dielectric formed on said laterally opposite sidewalls of said semiconductor body is thicker than said gate dielectric on said top surface of said semiconductor body; and a gate electrode formed on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body.
- 53. The semiconductor device of claim 52 wherein said gate dielectric layer on said laterally opposite sidewalls of said semiconductor body is at least 1.3 times the thickness of said gate dielectric layer on the top surface of said semiconductor body.
- 54. The semiconductor device of claim 53 wherein said gate dielectric layer is a grown oxide formed on a silicon body having a top surface with (100) crystal orientation and laterally opposite sidewalls with a (110) orientation.
- 55. The semiconductor device of claim 52 wherein said gate dielectric on said laterally opposite sidewall of said semiconductor body includes a grown oxide and a deposited dielectric wherein the gate dielectric layer on the top surface of said semiconductor body includes only a deposited dielectric film.
- 56. The semiconductor device of claim 55 wherein said deposited dielectric is a high K dielectric.
- 57. The semiconductor device of claim 56 wherein said high K dielectric is selected from the group consisting of PZT, BST, tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide and silicates thereof.
- 58. A method of forming a semiconductor device comprising:
forming an oxidation resistant film on a semiconductor body film formed on an insulating substrate; patterning said oxidation resistant film and said semiconductor body film to form an oxidation resistant mask a semiconductor body having a top surface opposite a bottom surface formed on said insulating film, and a first and a second laterally opposite sidewalls, wherein said oxidation resistant mask is formed on said top surface of said semiconductor body; growing an oxide on the laterally opposite sidewalls of said semiconductor body while said top surface of said semiconductor body is covered by said oxidation resistant mask; removing said oxidation resistant mask from said top surface of said semiconductor body; depositing a dielectric film adjacent to said grown oxide on said sidewalls of said semiconductor body and on the top surface of said semiconductor body; and forming a gate electrode above said gate dielectric on said top surface of said semiconductor body and adjacent to said deposited oxide on said laterally opposite sidewalls of said semiconductor body.
- 59. The semiconductor device of claim 58 wherein said deposited dielectric is a high K dielectric.
- 60. The semiconductor device of claim 58 wherein said high K dielectric is selected from the group consisting of PZT, BST, tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide and silicates thereof.
- 61. A method of forming a semiconductor device comprising:
forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate; growing a first dielectric layer over said laterally opposite sidewalls of said semiconductor body and on the top surface of said semiconductor body; removing said first dielectric layer from said top surface of said semiconductor body and leaving said first dielectric layer on said sidewalls of said semiconductor body; forming a second dielectric layer directly adjacent to said first dielectric layer on said sidewalls of said semiconductor body and forming said second dielectric layer on said top surface of said semiconductor body; and forming a gate electrode on said second dielectric on said top surface of said semiconductor body and adjacent to said second dielectric on said laterally opposite sidewalls of said semiconductor body.
- 62. The method of claim 61 wherein said first dielectric layer is a grown oxide.
- 63. The method of claim 61 wherein said second dielectric layer is a deposited high K dielectric layer.
- 64. The method of claim 61 where said second dielectric layer has a higher dielectric constant than said first dielectric layer.
- 65. The method of claim 61 wherein said step of removing said first dielectric layer from said top surface of said semiconductor body removes said first dielectric layer from corners between said top surface of said semiconductor body and said laterally opposite sidewalls of said semiconductor body.
- 66. A method of forming a semiconductor device comprising:
forming a semiconductor body having a top surface and laterally opposite sidewalls; altering said laterally opposite sidewalls of said semiconductor body to enhance the oxidation rate of said sidewalls of said semiconductor body; and growing an oxide on said sidewalls of said semiconductor body and on the top surface of said semiconductor body wherein the thickness of said oxide on said sidewalls of said semiconductor body is greater than the thickness of said oxide on said top surface of said semiconductor body.
- 67. The method of claim 66 wherein said sidewalls of said semiconductor body are altered by roughening said sidewalls by sputtering.
- 68. The method of claim 66 wherein said gate dielectric layer on said laterally opposite sidewalls of said semiconductor body is at least 1.3 times the thickness of said gate dielectric layer on the top surface of said semiconductor body.
- 69. A method of forming a semiconductor device comprising:
forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate; altering the top surface of said semiconductor body to impede the oxidation rate of said top surface of said semiconductor body; oxidizing said top surface of said semiconductor body and said laterally opposite sidewalls of said semiconductor body wherein the thickness of said oxide on said top surface of said semiconductor body is greater than the thickness of said oxide on said sidewalls of said semiconductor body; and forming a gate electrode on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body.
- 70. The method of claim 69 wherein the oxidation rate of said top surface of said semiconductor body is impeded by ion implanting nitrogen atoms in the top surface of said semiconductor body.
- 71. The method of claim 69 wherein gate dielectric layer on said laterally opposite sidewalls of said semiconductor body is at least 1.3 times the thickness of said gate dielectric layer on the top surface of said semiconductor body.
- 72. A semiconductor device comprising:
a semiconductor body having a top surface and laterally opposite sidewalls formed on an insulating substrate; a gate dielectric formed on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body wherein said gate dielectric on the top surface of the said semiconductor body has a higher effective dielectric constant than said gate dielectric layer on said sidewalls of said semiconductor body; and a gate electrode formed on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body.
- 73. The semiconductor device of claim 72 wherein said gate dielectric layer on said sidewalls of said semiconductor body comprises a first grown dielectric layer and a second deposited dielectric layer.
- 74. The semiconductor device of claim 73 wherein said gate dielectric layer on said top surface of said semiconductor body consist only of said second deposition dielectric layer.
- 75. A semiconductor device comprising:
a semiconductor body having a top surface and laterally opposite sidewalls formed on an insulating substrate; a gate dielectric formed on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body, wherein said gate dielectric layer formed on said top surface of said semiconductor body provide a higher gate capacitance per gate width than said gate dielectric layer on said sidewalls of said semiconductor body.
- 76. The semiconductor device of claim 75 wherein said gate dielectric layer on said sidewalls of said semiconductor body comprises a first grown dielectric layer and a second deposited dielectric layer.
- 77. The semiconductor device of claim 76 wherein said gate dielectric layer on said top surface of said semiconductor body consist only of said second deposition dielectric layer.
Parent Case Info
[0001] This is a Continuation-In-Part of prior application Ser. No. 10/227,068 filed on Aug. 23, 2002.
Divisions (1)
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Number |
Date |
Country |
Parent |
10367263 |
Feb 2003 |
US |
Child |
10887609 |
Jul 2004 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
10227068 |
Aug 2002 |
US |
Child |
10367263 |
Feb 2003 |
US |