Wafer level fan out semiconductor device and manufacturing method thereof

Abstract

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Description

TECHNICAL FIELD

The present application relates to a wafer level fan out semiconductor device and a manufacturing method thereof.

BACKGROUND

To cope with the trend towards smaller, lighter and higher-functionality electronic products, demand for smaller, lighter and higher-functionality electronic components integrated therein is being driven. Such demand has brought advances in various semiconductor packaging techniques along with semiconductor designing and manufacturing techniques, representative examples thereof may include an area array type, a ball grid array (BGA) type based on a surface mount type packaging technique, a flip-chip type, a chip size package (CSP) type, a wafer level fan out semiconductor device, and so on.

In the conventional wafer level fan out semiconductor device, a warpage phenomenon may undesirably occur to the completed device.

Further, in the conventional wafer level fan out semiconductor device, solder balls may be easily detached during thermal expansion or shrinkage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a wafer level fan out semiconductor device according to an embodiment;

FIG. 2 is a cross-sectional view of a wafer level fan out semiconductor device according to another embodiment;

FIG. 3 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment;

FIG. 4 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment;

FIG. 5 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment;

FIG. 6 is a cross-sectional view of a wafer level fan out semiconductor device according to still another embodiment;

FIG. 7 is a flowchart illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment;

FIGS. 8A, 8B, 8C, and 8D are cross-sectional views sequentially illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment;

FIG. 9 is a flowchart illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment; and

FIGS. 10A, 10B, 10C, 10D, and 10E are cross-sectional views sequentially illustrating a manufacturing method of a wafer level fan out semiconductor device according to still another embodiment.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements.

DETAILED DESCRIPTION

As an overview and in accordance with one embodiment, referring to FIG. 1, a wafer level fan out semiconductor device 100 includes a semiconductor die 110 having a first surface 111, a second surface 112, third surfaces 113 between the first surface 111 and the second surface 112, bond pads 114 coupled to the first surface 111, and a passivation layer 115 coupled the first surface 111 and having openings therein exposing the bond pads 114.

A first sealing part 120 is coupled to the third surfaces 113 of the semiconductor die 110. Redistribution layers 130 have first ends coupled to the bond pads 114 and extend on to at least the passivation layer 115. Solder balls 140 are coupled to ball lands 131 of the redistribution layers 130. Further, a second sealing part 150 encapsulates the passivation layer 115, the first sealing part 120, the redistribution layers 130, and lower portions of the solder balls 140.

In one embodiment, the first sealing part 120 and the second sealing part 150 have the same thermal expansion coefficient thus minimizing warpage of the wafer level fan out semiconductor device 100. Further, since the solder balls 140 are fixed and locked by the second sealing part 150 to the ball lands 131 of the redistribution layers 130, detachment between the redistribution layers 130 and the solder balls 140 is suppressed. In addition, since the second surface 112 of the semiconductor die 110 is exposed to the outside, heat dissipation efficiency of the semiconductor die 110 is maximized.

Now in more detail, referring to FIG. 1, a cross-sectional view of a wafer level fan out semiconductor device 100 is illustrated.

As illustrated in FIG. 1, the wafer level fan out semiconductor device 100 includes a semiconductor die 110, a first sealing part 120, a plurality of redistribution layers 130, a plurality of solder balls 140, and a second sealing part 150.

The semiconductor die 110 includes a first surface 111 that is approximately planar, a second surface 112 that is approximately planar and opposite to the first surface 111, and a plurality of third surfaces 113 that are disposed between the first surface 111 and the second surface 112 and are substantially planar. In addition, the semiconductor die 110 may further include a plurality of bond pads 114 formed on the first surface 111. First surface 111, second surface 112 and third surfaces 113 are sometimes called an active surface 111, an inactive surface 112, and sides 113.

Further, the semiconductor die 110 includes a passivation layer 115 formed at the outer periphery of the plurality of bond pads 114 on the first surface 111. Stated another way, the passivation layer 115 has bond pad openings formed therein that expose the bond pads 114 except for the outer periphery of the bond pads 114 that may remain covered by the passivation layer 115. The passivation layer 115 may be made of at least one selected from the group consisting of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimideTriazine (BT), phenolic resin, epoxy, silicone, oxide (SiO₂), nitride (Si₃N₄), and equivalents thereof. However, the kinds of materials for the passivation layer 115 are not limited to those specifically listed herein.

The first sealing part 120 is formed on each of the third surfaces 113 of the semiconductor die 110. Like the semiconductor die 110, the first sealing part 120 may include a first surface 121 that is substantially coplanar with a surface of the passivation layer 115 formed on the semiconductor die 110 and a second surface 122 that is substantially coplanar with the second surface 112 of the semiconductor die 110.

The first sealing part 120 allows the second surface 112 of the semiconductor die 110 to be directly exposed to the outside. In addition, the first sealing part 120 may be made of at least one selected from the group consisting of an epoxy-molding compound, a liquid encapsulant, and equivalents thereof. However, the kinds of materials for the first sealing part 120 are not limited to those specifically listed herein. In practice, the first sealing part 120 may be made of an epoxy molding compound using a mold.

The plurality of redistribution layers 130 are formed on the semiconductor die 110 and the first sealing part 120. That is to say, first ends of the plurality of redistribution layers 130 are electrically connected to the plurality of bond pads 114 of the semiconductor die 110 and second ends thereof extend to the passivation layer 115 or to the first surface 121 of the first sealing part 120. That is to say, the redistribution layers 130 redistribute the plurality of bond pads 114 that are peripherally distributed or the plurality of bond pads 114 that are centrally distributed in a matrix configuration to be distributed not only on the first surface 111 of the semiconductor die 110 but also on the first surface 121 of the first sealing part 120 positioned at the sides 113 of the semiconductor die 110.

In addition, a ball land 131 having an approximately circular shape is formed at the end of each of the redistribution layers 130, thereby allowing the solder balls 140 to be easily connected to the redistribution layers 130.

The redistribution layers 130 may be made of titanium (Ti), tungsten (W) and copper (Cu). However, the kinds of materials for the redistribution layers 130 are not limited to those specifically listed herein. In practice, the titanium (Ti) and tungsten (W) may serve as a seed layer allowing copper (Cu) to be firmly adhered to the passivation layer 115 or the first sealing part 120 while allowing copper (Cu) to be plated thickly in the manufacture of the semiconductor device 100.

The plurality of solder balls 140 are electrically connected to the ball lands 131 provided in the redistribution layers 130, respectively. The solder balls 140 electrically connect the semiconductor die 110 to external devices. The solder balls 140 may be made of at least one selected from the group consisting of Sn—Pb, Sn—Pb—Ag, Sn—Pb—Bi, Sn—Cu, Sn—Ag, Sn—Bi, Sn—Ag—Cu, Sn—Ag—Bi, Sn—Zn, and equivalents thereof. However, the kinds of materials for the solder balls 140 are not limited to those specifically listed herein.

The second sealing part 150 encapsulates the semiconductor die 110, the redistribution layers 130 and the first sealing part 120. In particular, the second sealing part 150 encapsulates some portions of the solder balls 140. Preferably, the second sealing part 150 encapsulates approximately 10% to approximately 50% a diameter of each of the solder balls 140. Stated another way, the second sealing part 150 covers 10% to 50% of the total height of the solder balls 140, i.e., directly contacts the lower 10% to 50% of the solder balls 140.

That is to say, the solder balls 140 are electrically connected to the redistribution layers 130 and some parts, i.e., the lower 10-50%, of the solder balls 140 are fixed and locked to the redistribution layers 130 by the second sealing part 150. Therefore, detachment between the redistribution layers 130 and the solder balls 140 can be suppressed.

Meanwhile, the second sealing part 150 may have a coefficient of thermal expansion that is the same as or similar to that of the first sealing part 120. In order to minimize warpage of the semiconductor device 100, the first sealing part 120 and the second sealing part 150 are preferably made of materials having the same thermal expansion coefficient. In addition, the second sealing part 150 may be made of a material that is the same as or similar to that of the first sealing part 120. Likewise, in order to minimize warpage of the semiconductor device 100, the first sealing part 120 and the second sealing part 150 are preferably made of the same material.

In addition, the second sealing part 150 may also be made of at least one selected from the group consisting of an epoxy-molding compound, a liquid encapsulant, and equivalents thereof. However, the kinds of materials for the second sealing part 150 are not limited to those specifically listed herein. In practice, the second sealing part 150 may be made of a liquid encapsulant using a dispenser.

As described above, in the wafer level fan out semiconductor device 100, since the solder balls 140 are electrically connected to the redistribution layers 130 and fixed and locked by the second sealing part 150, detachment between the redistribution layers 130 and the solder balls 140 can be suppressed.

In addition, in the wafer level fan out semiconductor device 100, since the first sealing part 120 is formed at the lateral third surface 113 of the semiconductor die 110, and the second sealing part 150 having the same thermal expansion coefficient or made of the same material as that of the first sealing part 120 is formed on the semiconductor die 110 and the first sealing part 120, occurrence of warpage to the semiconductor device 100 may be suppressed.

In addition, since the second surface 112 of the semiconductor die 110 is exposed to the outside, heat dissipation efficiency of the semiconductor die 110 can be further enhanced.

Referring to FIG. 2, a cross-sectional view of a wafer level fan out semiconductor device 200 according to another embodiment is illustrated.

As illustrated in FIG. 2, the wafer level fan out semiconductor device 200 includes the second surface 112 of the semiconductor die 110 encapsulated by a first sealing part 220. That is to say, lateral and bottom surfaces 113, 112 of the semiconductor die 110 are encapsulated by the first sealing part 220, and a top surface 111 of the semiconductor die 110 is encapsulated by the second sealing part 150.

Thus, whereas a first surface 221 of the first sealing part 220 is substantially coplanar with the passivation layer 115, a second surface 222 of the first sealing part 220 is positioned below a level of the second surface 112 of the semiconductor die 110. That is to say, the second surface 112 of the semiconductor die 110 is encapsulated by the second surface 222 of the first sealing part 220.

As described above, in the wafer level fan out semiconductor device 200, since the second surface 112 of the semiconductor die 110 is encapsulated by the first sealing part 220, it is possible to safely protect the second surface 112 of the semiconductor die 110 against external impacts.

In addition, since the first sealing part 220 is formed at the lateral and bottom surfaces 113, 112 of the semiconductor die 110 and the second sealing part 150 is formed at the top surface 111 of the semiconductor die 110, warpage can be further prevented from occurring to the wafer level fan out semiconductor device 200.

Referring to FIG. 3, FIG. 3 is a cross-sectional view of a wafer level fan out semiconductor device 300 according to still another embodiment.

As illustrated in FIG. 3, the wafer level fan out semiconductor device 300 includes the second surface 112 of the semiconductor die 110 and the second surface 122 of the first sealing part 120 encapsulated by a third sealing part 330. The third sealing part 330 may have a thermal expansion coefficient that is the same as or similar to that of the first or second sealing part 120 or 150. In addition, the third sealing part 330 may be made of a material that is the same as or similar to that of the first or second sealing part 120 or 150.

In an exemplary embodiment, the third sealing part 330 may be made of at least one selected from the group consisting of a generally used dry insulation film, polymer, and equivalents thereof. However, the kinds of materials for the third sealing part 330 are not limited to those specifically listed herein.

As described above, in the wafer level fan out semiconductor device 300, since the second surface 112 of the semiconductor die 110 is encapsulated by the third sealing part 330, it is possible to safely protect the second surface 112 of the semiconductor die 110 against external impacts.

In addition, since the first sealing part 120 is formed at the lateral surfaces 113 of the semiconductor die 110, the second sealing part 150 is formed at the top surface 111 of the semiconductor die 110, and the third sealing part 330 is formed at the bottom surface 112 of the semiconductor die 110, warpage can be more effectively prevented from occurring to the wafer level fan out semiconductor device 300.

Referring to FIG. 4, a cross-sectional view of a wafer level fan out semiconductor device 400 according to still another embodiment is illustrated.

As illustrated in FIG. 4, the wafer level fan out semiconductor device 400 further includes a dielectric layer 410 between the passivation layer 115 and the redistribution layers 130, and between the first sealing part 120 and the second sealing part 150. The redistribution layers 130 extend through openings in the dielectric layer 410 to be electrically connected to the bond pads 114 of the semiconductor die 110.

Since the dielectric layer 410 has a relatively low dielectric constant compared to the first sealing part 120 or the second sealing part 150, it may suppress signal interference between the redistribution layers 130. In addition, since the dielectric layer 410 is relatively soft, compared to the first sealing part 120 or the second sealing part 150, it may absorb external impacts applied to the solder balls 140, thereby suppressing damages to the semiconductor die 110.

The dielectric layer 410 may be made of at least one selected from the group consisting of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimideTriazine (BT), phenolic resin, epoxy, silicone, oxide (SiO₂), nitride (Si₃N₄), and equivalents thereof. However, the kinds of materials for the dielectric layer 410 are not limited to those specifically listed herein.

In addition, the dielectric layer 410 may be formed to have a thickness of approximately 3 μm to approximately 15 μm. If the thickness of the dielectric layer 410 is less than 3 μm, the efficiency of absorbing or dampening mechanical stresses externally applied to the solder balls 140 may be lowered. If the thickness of the dielectric layer 410 is greater than 15 μm, a thickness of the wafer level fan out semiconductor device 400 may excessively increase.

Referring to FIG. 5, a cross-sectional view of a wafer level fan out semiconductor device 500 according to still another embodiment is illustrated.

As illustrated in FIG. 5, the wafer level fan out semiconductor device 500 includes the second surface 112 of the semiconductor die 110 encapsulated by a first sealing part 520. That is to say, lateral and bottom surfaces 113, 112 of the semiconductor die 110 are encapsulated by the first sealing part 520, and a top surface 111 of the semiconductor die 110 is encapsulated by the second sealing part 150.

Thus, whereas a first surface 521 of the first sealing part 520 is substantially coplanar with the passivation layer 115, a second surface 522 of the first sealing part 520 is positioned below a level of the second surface 112 of the semiconductor die 110.

As described above, in the wafer level fan out semiconductor device 500, since the second surface 112 of the semiconductor die 110 is encapsulated by the first sealing part 520, it is possible to safely protect the second surface 112 of the semiconductor die 110 against external impacts.

In addition, since the first sealing part 520 is formed at the lateral and bottom surfaces 113, 112 of the semiconductor die 110, and the second sealing part 150 is formed at the top surface 111 of the semiconductor die 110, warpage can be more effectively prevented from occurring to the wafer level fan out semiconductor device 500.

Referring to FIG. 6, a cross-sectional view of a wafer level fan out semiconductor device 600 according to still another embodiment is illustrated.

As illustrated in FIG. 6, the wafer level fan out semiconductor device 600 includes the second surface 112 of the semiconductor die 110 and the second surface 122 of the first sealing part 120 encapsulated by a third sealing part 630.

The third sealing part 630 may have a thermal expansion coefficient that is the same as or similar to that of the first or second sealing part 120 or 150. In addition, the third sealing part 630 may be made of a material that is the same as or similar to that of the first or second sealing part 120 or 150.

In an exemplary embodiment, the third sealing part 630 may be made of at least one selected from the group consisting of a generally used dry insulation film, polymer, and equivalents thereof. However, the kinds of materials for the third sealing part 630 are not limited to those specifically listed herein.

As described above, in the wafer level fan out semiconductor device 600, since the second surface 112 of the semiconductor die 110 is encapsulated by the third sealing part 630, it is possible to safely protect the second surface 112 of the semiconductor die 110 against external impacts.

In addition, since the first sealing part 120 is formed at the lateral surfaces 113 of the semiconductor die 110, the second sealing part 150 is formed at the top surface 111 of the semiconductor die 110, and the third sealing part 630 is formed at the bottom surface 112 of the semiconductor die 110, warpage can be more effectively prevented from occurring to the wafer level fan out semiconductor device 600.

Referring to FIG. 7, a flowchart illustrating a manufacturing method of the wafer level fan out semiconductor device 100 according to still another embodiment is illustrated.

As illustrated in FIG. 7, the manufacturing method of a wafer level fan out semiconductor device 100 includes a firstly seal operation S1, a form redistribution layers operation S2, an attach solder balls operation S3, and a secondly seal operation S4.

Referring to FIGS. 8A through 8D, cross-sectional views sequentially illustrating a manufacturing method of the wafer level fan out semiconductor device 100 according to still another embodiment are illustrated.

As illustrated in FIG. 8A, in the firstly seal operation S1, a first sealing part 120 is formed on lateral surfaces 113 of a semiconductor die 110. Here, the semiconductor die 110 includes a first surface 111, a second surface 112, a plurality of third surfaces 113 formed between the first surface 111 and the second surface 112, a plurality of bond pads 114 formed on the first surface 111, and a passivation layer 115 formed on the first surface 111 corresponding to the outer periphery of the plurality of bond pads 114.

The semiconductor die 110 is placed in a mold (not shown) having cavities (not shown) formed at regions corresponding to the third surfaces 113, and a high-temperature, and high-pressure epoxy molding compound is injected into the cavities, thereby forming the first sealing part 120 having a first surface 121 and a second surface 122.

Here, the passivation layer 115 of the semiconductor die 110 is coplanar with the first surface 121 of the first sealing part 120, and the second surface 112 of the semiconductor die 110 is coplanar with the second surface 122 of the first sealing part 120. Thus, the second surface 112 of the semiconductor die 110 is exposed to the outside. Although the method of forming the first sealing part 120 using a mold has been illustrated herein, the first sealing part 120 may also be formed using a dispenser.

As illustrated in FIG. 8B, in the form redistribution layers operation S2, a plurality of redistribution layers 130 are formed on the passivation layer 115 of the semiconductor die 110 and on the first surface 121 of the first sealing part 120. That is to say, the redistribution layers 130 are formed in this stage, the redistribution layers 130 having first ends electrically connected to the plurality of bond pads 114 of the semiconductor die 110 and second ends extending to the passivation layer 115 or the first surface 121 of the first sealing part 120 by a predetermined length, and including circular ball lands 131 provided at distal ends thereof.

More specifically, a seed layer is formed on the passivation layer 115 of the semiconductor die 110 and on the first surface 121 of the first sealing part 120 using titanium and tungsten. Next, photoresist is coated, and exposure and developing processes are performed on the resultant structure, thereby defining a pattern so that a predetermined region of the seed layer is exposed outside the photoresist.

Next, copper (Cu) is relatively thickly plated on the seed layer inside the pattern formed of the photoresist, thereby forming the redistribution layers 130. Subsequently, the photoresist and the seed layer disposed outside the redistribution layers 130 are completely etched to then be removed. Since the seed layer or photoresist and the etching are all known very well in the art, they are not illustrated.

As illustrated in FIG. 8C, in the attach solder balls operation S3, the solder balls 140 each having an approximately circular shape are attached to the redistribution layers 130 formed on the passivation layer 115 or the first sealing part 120.

Viscous flux, for example, is first coated on the ball lands 131, and the solder balls 140 are then positioned on the flux. Next, when the semiconductor die 110 is introduced into a furnace maintained at a temperature ranging from 150° C. to 300° C., and taken out from the furnace, the flux is volatilized to then be eliminated and the circular-shaped solder balls 140 are fused to the ball lands 131 of the redistribution layers 130.

As illustrated in FIG. 8D, in the secondly seal operation S4, some regions of the solder balls 140 are encapsulated by a second sealing part 150. A liquid encapsulant is dispensed on the passivation layer 115, the redistribution layers 130, the first sealing part 120 and the solder balls 140 using, for example, a dispenser, followed by curing for a predetermined time.

In addition to the method using the dispenser, the second sealing part 150 may also be formed by a method using a mold. Meanwhile, the second sealing part 150 encapsulates approximately 10% to approximately 50% a diameter of each of the solder balls 140 as explained above. In such a manner, the solder balls 140 are locked by the second sealing part 150.

As described above, in the wafer level fan out semiconductor device 100, the first sealing part 120 is formed on the lateral surface 113 of the semiconductor die 110, and the second sealing part 150 having the same thermal expansion coefficient as that of the first sealing part 120 is formed on the top surface 111 of the semiconductor die 110, occurrence of warpage to the semiconductor device 100 may be suppressed.

In addition, in the wafer level fan out semiconductor device 100, since the solder balls 140 are attached not only to the redistribution layers 130 but also to the second sealing part 150, detachment between the redistribution layers 130 and the solder balls 140 can be suppressed.

Referring to FIG. 9, a flowchart illustrating a manufacturing method of the wafer level fan out semiconductor device 400 according to still another embodiment is illustrated.

As illustrated in FIG. 9, the manufacturing method of the wafer level fan out semiconductor device 400 includes a firstly seal operation S11, a form dielectric layer operation S12, a form redistribution layers operation S13, an attach solder balls operation S14, and a secondly seal operation S15.

Referring to FIGS. FIGS. 10A through 10E, cross-sectional views sequentially illustrating a manufacturing method of the wafer level fan out semiconductor device 400 according to still another embodiment are illustrated.

The firstly seal operation S11, the attach solder balls operation S14, and the secondly seal operation S15 illustrated in FIGS. 10A, 10D and 10E are the same or similar as the firstly seal operation S1, the attach solder balls operation S3, and the secondly seal operation S4 illustrated in FIGS. 8A, 8C and 8D and described in the previous embodiment, descriptions thereof will not be given.

As illustrated in FIG. 10B, in the form dielectric layer operation S12, a dielectric layer 410 having a predetermined thickness is formed on the passivation layer 115 of the semiconductor die 110 and on the first surface 121 of the first sealing part 120. Here, a plurality of bond pads 114 of the semiconductor die 110 extend through the dielectric layer 410 to then be exposed to the outside.

To this end, after forming the dielectric layer 410 having a predetermined thickness on the passivation layer 115 of the semiconductor die 110 and on the first surface 121 of a first sealing part 120, photoresist is coated and exposure and development processes are performed thereon. As a result, the dielectric layer 410 corresponding to the plurality of bond pads 114 is exposed to the outside. Next, an etching process is performed using the photoresist as a mask, thereby etching and removing the exposed dielectric layer 410. Accordingly, the plurality of bond pads 114 are exposed to the outside. The photoresist is removed in a subsequent process.

As illustrated in FIG. 10C, in the form redistribution layers operation S13, a plurality of redistribution layers 130 are formed on a surface of the dielectric layer 410. That is to say, the redistribution layers 130 are formed in this stage, the redistribution layers 130 having first ends electrically connected to the plurality of bond pads 114 of the semiconductor die 110 and second ends extending to the dielectric layer 410 by a predetermined length, and including circular ball lands 131 provided at distal ends thereof.

More specifically, a seed layer is formed on the plurality of bond pads 114 and the dielectric layer 410 using titanium and tungsten. Next, photoresist is coated, and exposure and developing processes are performed on the resultant structure, thereby defining a pattern so that a predetermined region of the seed layer is exposed outside the photoresist. Next, copper (Cu) is relatively thickly plated on the seed layer inside the pattern formed of the photoresist, thereby forming the redistribution layers 130. Subsequently, the photoresist and the seed layer disposed outside the redistribution layers 130 are completely etched to then be removed.

Although specific embodiments were described herein, the scope of the invention is not limited to those specific embodiments. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material are possible. The scope of the invention is at least as broad as given by the following claims.

Claims

1. A semiconductor device, comprising: a semiconductor die comprising a first surface, a second surface, third surfaces between the first surface and the second surface, a bond pad coupled to the first surface, and a passivation layer having a lower surface contacting the first surface, the passivation layer having an opening in an upper surface that exposes the bond pad;a first sealing part coupled to the third surfaces of the semiconductor die;a dielectric layer having a lower surface, an upper surface opposite the lower surface, and side surfaces joining the lower surface to the upper surface, wherein the lower surface of the dielectric layer is on and in contact with the upper surface of the passivation layer and an upper surface of the first sealing part, and wherein the lower surface of the dielectric layer extends no lower than the upper surface of the passivation layer;a conductive path having a lower surface contacting the upper surface of the dielectric layer, the conductive path extending from a first end coupled to the bond pad toward a second end coupled to a conductive land that is above the upper surface of the first sealing part and beyond the third surfaces of the semiconductor die;a conductive, interconnection structure coupled to the conductive land such that the interconnection structure is peripherally distributed beyond the third surfaces of the semiconductor die; anda second sealing part comprising a single layer having a lower surface, an upper surface opposite the lower surface, and side surfaces joining the lower surface to the upper surface, wherein the lower surface of the single layer from the second sealing part is on an upper surface of the dielectric layer and an upper surface of the conductive path, wherein the second sealing part contacts and encapsulates at least 10% of a total height of the interconnection structure.

2. The semiconductor device of claim 1, wherein the second sealing part does not encapsulate more than 50% of the total height of the interconnection structure.

3. The semiconductor device of claim 1, wherein a thermal expansion coefficient of the first sealing part is equal to a thermal expansion coefficient of the second sealing part.

4. The semiconductor device of claim 1, wherein: the conductive path comprises a trace contacting and extending along the upper surface of the dielectric layer from the bond pad to beyond the third surfaces of the semiconductor die; andthe lower surface of the single layer from the second sealing part is in contact with the upper surface of the dielectric layer and the upper surface of the conductive path.

5. The semiconductor device of claim 1, wherein the first sealing part further comprises a surface that is coplanar with the second surface of the semiconductor die.

6. The semiconductor device of claim 5, wherein the second surface of the semiconductor die defines an external surface of the semiconductor device.

7. The semiconductor device of claim 5, further comprising a third sealing part that encapsulates the surface of the first sealing part and the second surface of the semiconductor die.

8. The semiconductor device of claim 1, wherein the first sealing part encapsulates the second surface of the semiconductor die.

9. The semiconductor device of claim 1, wherein: a dielectric constant of the dielectric layer is lower than a dielectric constant of the first sealing part; andthe dielectric constant of the dielectric layer is lower than a dielectric constant of the second sealing part.

10. A semiconductor device, comprising: a semiconductor die comprising a first surface, a second surface, third surfaces between the first surface and the second surface, a bond pad coupled to the first surface, and a passivation layer contacting the first surface, the passivation layer having a passivation layer lower surface, a passivation layer upper surface opposite the passivation layer lower surface, a passivation layer side surface between passivation layer lower surface and the passivation layer upper surface, and an opening in the passivation layer upper surface that exposes the bond pad;a first sealing part coupled to the third surfaces of the semiconductor die and in direct contact with the passivation layer side surface;a dielectric layer having a lower surface on and in contact with the first sealing part;a conductive path having a lower surface contacting an upper surface of the dielectric layer, the conductive path extending from a first end coupled to the bond pad toward a second end coupled to a conductive land that is positioned peripherally beyond the third surfaces of the semiconductor die;a conductive, interconnection structure coupled to the conductive land such that the interconnection structure is peripherally distributed beyond the third surfaces of the semiconductor die; anda second sealing part comprising a single layer on a first surface of the first sealing part and the conductive path, wherein the second sealing part contacts and encapsulates at least 10% of a total height of the interconnection structure.

11. The semiconductor device of claim 10, wherein a thermal expansion coefficient of the first sealing part is equal to a thermal expansion coefficient of the second sealing part.

12. The semiconductor device of claim 10, wherein the first sealing part further comprises a second surface opposite the first surface that is coplanar with the second surface of the semiconductor die.

13. The semiconductor device of claim 12, wherein the second surface of the semiconductor die defines an external surface of the semiconductor device.

14. The semiconductor device of claim 12, further comprising a third sealing part that encapsulates the surface of the first sealing part and the second surface of the semiconductor die.

15. The semiconductor device of claim 10, wherein the first sealing part encapsulates the second surface of the semiconductor die.

16. The semiconductor device of claim 10, wherein: the dielectric layer is softer than the first sealing part; andthe dielectric layer is softer than the second sealing part.

17. A method of forming a semiconductor device, the method comprising: forming a passivation layer over a first surface of a semiconductor die such that the passivation layer has a passivation layer lower surface, a passivation layer upper surface opposite the passivation layer lower surface, a passivation layer side surface between passivation layer lower surface and the passivation layer upper surface, and an opening in the passivation layer upper surface that exposes a bond pad on the first surface of the semiconductor die;encapsulating and directly contacting, with a first sealing part, third surfaces of the semiconductor die that adjoin the first surface of the semiconductor die to an opposite second surface of the semiconductor die;forming a dielectric layer having a lower surface on and in contact with the first sealing part;forming a conductive path having a lower surface contacting an upper surface of the dielectric layer such that the conductive path extends from a first end coupled to the bond pad toward a second end coupled to a conductive land that is positioned peripherally beyond the third surfaces of the semiconductor die;attaching a conductive, interconnection structure to the conductive land such that the interconnection structure is peripherally distributed beyond the third surfaces of the semiconductor die; andforming a second sealing part comprising a single layer on a first surface of the first sealing part and the conductive path such that the second sealing part contacts and encapsulates at least 10% of a total height of the interconnection structure.

18. The method of claim 17, wherein said forming the second sealing part comprises forming the second sealing part such that the second sealing part does not encapsulate more than 50% of the total height of the interconnection structure.

19. The method of claim 17, wherein said forming the second sealing part comprises forming the second sealing part from a material having a thermal expansion coefficient equal to a thermal expansion coefficient of the first sealing part.

20. The method of claim 17, further comprising encapsulating, with a third sealing part, a second surface of the first sealing part and the second surface of the semiconductor die.