Patent Application
20240153859
The present disclosure relates to a wiring body, a mounting substrate, a method for manufacturing a wiring body, and a method for manufacturing a mounting substrate, and in particular, to a wiring body or the like that can be used as a wiring layer or a redistribution layer (RDL) of a mounting substrate such as a semiconductor package substrate.
The demand for smaller, more highly integrated, and more sophisticated semiconductor devices has led to a variety of packaging techniques for semiconductor devices. In recent years, 2.5D semiconductor packages, in which a silicon interposer provided with a plurality of semiconductor devices of different types is mounted on a semiconductor package substrate, have become the mainstream packaging technique for semiconductor devices. In 2.5D semiconductor packages, signal connections between the plurality of semiconductor devices are connected by fine circuits on the silicon interposer, and the entire silicon interposer can be regarded as a single “system on chip” (SoC) with integrated functions.
The silicon interposer includes a silicon wafer. In a silicon interposer, a fine multilayer wiring layer is formed by a semiconductor process on the front of the silicon wafer where the semiconductor devices are mounted, and connection terminals and electrical circuits that are connected to the semiconductor package substrate are formed on the rear of the silicon wafer, and the circuits on the front and rear are electrically connected by “through silicon vias” (TSVs) that penetrate the silicon wafer.
However, silicon interposers, which require wafer-level manufacturing processes, are expensive to manufacture. As a result, silicon interposers are often limited to applications in servers, high-end PCs, high-end graphics, etc., where performance is more important than cost, which is an obstacle to their widespread use.
In addition, since silicon is a semiconductor, forming the wiring layer directly on the silicon wafer results in degradation of electrical characteristics. Furthermore, when semiconductor devices are mounted on a semiconductor package substrate with a silicon interposer, compared to when semiconductor devices are mounted directly on the semiconductor package substrate, the transmission distance from the semiconductor package substrate is longer by the size of the silicon interposer, and noise is easily added.
2.1D semiconductor package substrates have been proposed as a new packaging technique that is less expensive than silicon interposer. A 2.1D semiconductor package substrate is an organic semiconductor package substrate that does not require a silicon interposer by making the multilayer wiring layer on the device mounting side of a conventional organic semiconductor package substrate have a wiring density similar to that of a silicon interposer (for example, see PTL 1).
However, 2.1D semiconductor package substrates present a challenge in that they require the formation of multiple layers of thin-layer fine wiring similar to silicon interposers. For example, 2.1D semiconductor package substrates require thin-layer fine wiring with an L/S of at least 2/2 μm to 5/5 μm and a wiring layer thickness of 3 μm to 10 μm per layer.
In such cases, to form fine wiring using conventional techniques, it is necessary to polish and planarize, by chemical mechanical polishing (CMP), one layer of wiring on the top surface layer of the semiconductor device mounting surface of a semiconductor package substrate manufactured using a normal process by. However, polishing and planarizing by CMP is expensive, and thus difficult to simply apply to the field of semiconductor package substrates.
The semi additive process (SAP) and the modified semi additive process (MSAP) are examples of known technologies for using a plating method to form fine wiring of L/S=2/2 μm to 5/5 μm on mounting substrates, such as semiconductor package substrates, including multilayer wiring layers. However, when fine wiring is formed by SAP or MSAP, the physical stress caused by the roller laminator or the like when thermo-compression bonding the film-like insulating resin, which serves as the interlayer insulating layer, frequently causes the wiring to peel off, making it difficult to manufacture fine wiring with high yield.
Moreover, when the line width of wiring is miniaturized to 2 μm to 5 μm, the thickness of the interlayer insulating layer needs to be reduced from the viewpoint of impedance and fabrication, but when film-like insulating resin is used, either there is no insulating resin with the appropriate thickness, or even if there is, it is difficult to laminate and thermocompress the thin film-like insulating resin.
In view of this, in order to make the thickness of the interlayer insulating layer uniform, the use of liquid insulating resin instead of a film-like insulating resin as the insulating material of the interlayer insulating layer has been considered, but in such cases, it is difficult to maintain a constant thickness of the interlayer insulating layer because the thickness of the interlayer insulating layer, which is formed by curing a liquid insulating resin, is affected by the unevenness of the via electrodes and wiring. In order to mitigate the effect of such unevenness of the via electrodes and wiring, it is conceivable to use filled-via plating, in which plating is selectively deposited as via electrodes and wiring, but it is difficult to form via electrodes and wiring simultaneously by smooth plating due to the diameter of the via electrodes (via holes), width and thickness of the wiring, thickness of the interlayer insulating layer, etc.
[PTL 1] Japanese Unexamined Patent Application Publication No. 2020-107681
Thus, regarding semiconductor package substrates in which wiring bodies including via electrodes and wiring are used, it is difficult to make the lines of wiring finer and disposed at a narrower pitch using conventional manufacturing techniques such as SAP or MSAP. In particular, since the line width of fine wiring is smaller than the diameter of the via electrodes, the bottom portion of the wiring may be undercut by over-etching when forming the wiring by etching, resulting in wiring defects.
The present disclosure was conceived to overcome such problems and has an object to provide, for example, a wiring body and a mounting substrate, including via electrodes and wiring, in which the lines of the wiring can be made finer and disposed at a narrower pitch.
In order to achieve the above object, in one aspect, a wiring body according to the present disclosure is a wiring body that is disposed above a substrate including a conductor includes: a via electrode provided in a via hole formed in an insulating layer on the substrate, the via electrode connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. A material or structure of a lower layer in the via electrode and a material or structure of a lower layer in the wiring are different.
In one aspect, a mounting substrate according to the present disclosure includes: a substrate including a conductor; and the above-described wiring body above the substrate.
In one aspect, a method for manufacturing a wiring body according to the present disclosure is a method for manufacturing a wiring body disposed above a substrate including a conductor, and includes: disposing wiring above the substrate with an insulating layer interposed therebetween; after disposing the wiring, forming a via hole in the insulating layer so as to expose the conductor by removing a portion of the insulating layer; after forming the via hole, forming a seed film to cover the conductor that is exposed and the wiring; after forming the seed film, selectively forming a resist on the seed layer covering the wiring so as to expose a portion of the seed film covering the conductor; after selectively forming the resist, forming a via electrode body layer on the seed film that is exposed; and after forming the via electrode body layer and after removing the resist, removing a portion of the seed film covering the wiring.
In one aspect, a method for manufacturing a mounting substrate according to the present disclosure is a method for manufacturing a mounting substrate including a wiring body disposed above a substrate, and includes: disposing the wiring body on the substrate. The wiring body is manufactured by the above-described method.
In, for example, a wiring body and a mounting substrate, including via electrodes and wiring, the lines of the wiring can be made finer and disposed at a narrower pitch.
Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The embodiments described below each illustrate one specific example of the present disclosure. The numerical values, shapes, materials, elements, the arrangement and connection of the elements, etc., shown in the following embodiments are mere examples, and therefore do not limit the scope of the present disclosure. Therefore, among the elements in the following embodiments, those not recited in any of the independent claims defining the broadest concept of the present disclosure are described as optional elements.
Note that the drawings are represented schematically and are not necessarily precise illustrations. Accordingly, the scale, etc., is not necessarily the same in each figure. Additionally, like reference signs indicate like elements. As such, overlapping descriptions of like elements are omitted or simplified.
First, the configurations of wiring body 30 and mounting substrate 1 according to Embodiment 1 will be described with reference to
For example, mounting substrate 1 is a semiconductor package substrate, and includes a plurality of wiring layers in which wiring is formed. Therefore, as illustrated in
A plurality of via electrodes 31 and a plurality of lines of wiring 32 are formed in each wiring layer. As one example, mounting substrate 1 is a small, ultra-high-density mounting substrate densely provided with wiring 32. Wiring 32 is, for example, fine wiring characterized by L/S=5/5 μm or less. Wiring 32 is therefore formed in a complex wiring pattern so as to pass between two via electrodes 31. In such a configuration, the space between via electrodes (via pitch) is narrow, so lines of wiring 32 are formed at a narrow pitch such that lines of wiring 32 can pass through the narrow space between via electrodes.
As illustrated in
Substrate 10 includes conductor 11. Conductor 11 is, for example, wiring or an electrode formed in a different wiring layer than wiring 32. As one example, substrate 10 is a wiring substrate, which is a wiring-equipped substrate including wiring formed with, for example, copper foil, such as a build-up substrate, a multilayer wiring substrate, a double-sided wiring substrate, or a single-sided wiring substrate. Substrate 10 therefore includes a plurality of lines of wiring, etc., as conductors 11 over a single or a plurality of layers. Note that in
In the present embodiment, mounting substrate 1 is an ultra-high-density mounting substrate, and a build-up substrate is used as substrate 10. Substrate 10 is not limited to a wiring substrate such as a build-up substrate, and may be an IC package substrate or an IC chip itself, as long as it includes wiring or electrodes, etc., as conductors 11.
Insulating layer 20 is formed on substrate 10. More specifically, insulating layer 20 covers the entirety of substrate 10 so as to cover conductors 11 on the surface layer of substrate 10.
Insulating layer 20 is disposed between conductors 11 of substrate 10 and wiring 32. Accordingly, insulating layer 20 is an interlayer insulating layer. More specifically, as illustrated in
Via hole 21 is formed in insulating layer 20. Via hole 21 is a through-hole formed above conductor 11 of substrate 10. Via electrode 31 is formed in via hole 21. Via hole 21 has a truncated cone shape with a sloping (tapered) inner surface. Accordingly, the shape of the opening (the top view shape) of via hole 21 is circular, and the cross-sectional shape of via hole 21 is trapezoidal. Note that via hole 21 may have a polygonal frustum shape, such as a square frustum shape, or a columnar or prismatic shape.
Insulating layer 20 includes an insulating material. The insulating material of insulating layer 20 is, for example, an insulating resin. In such cases, the insulating resin material used to form insulating layer 20 may be a liquid insulating resin material with flowability including a photo-curable resin such as a UV-curable resin or a thermosetting resin, or a prepreg of a film-like insulating resin including a thermosetting resin or a thermoplastic resin. An insulating resin sheet can be used as the film-like insulating resin. In such cases, the insulating resin sheet should have adhesive properties. Note that the insulating material of insulating layer 20 is not limited to organic insulating materials such as insulating resin, and may also be an inorganic insulating material such as silicon oxide film or silicon nitride film.
Wiring body 30 is disposed above substrate 10 including conductors 11. More specifically, via electrodes 31 of wiring body 30 are disposed on conductors 11 of substrate 10, and wiring 32 of wiring body 30 is located above substrate 10 with insulating layer 20 interposed therebetween. More specifically, wiring 32 is disposed on insulating layer 20. As illustrated in
As will be described in detail below, wiring 32 is formed on insulating layer 20 by a transfer method using a wiring transfer plate. Note that all of wiring 32 need not be located above the main surface of insulating layer 20; the bottom portion of wiring 32 may be located within insulating layer 20.
Via electrode 31 is connected to conductor 11 of substrate 10 through via hole 21 in insulating layer 20. Via electrode 31 is a plug that connects the top and bottom wiring that sandwiches insulating layer 20. More specifically, via electrode 31 connects the wiring (conductor 11) of first wiring layer WL1 located directly below insulating layer 20 and the wiring (wiring 32) of second wiring layer WL2 located directly above insulating layer 20.
Via electrode 31 is at least partially provided in via hole 21. More specifically, via electrode 31 is seamlessly embedded in via hole 21. Via electrode 31 is formed not only inside via hole 21, but also protrudes out from the main surface of insulating layer 20. The height of via electrode 31 from the main surface of insulating layer is higher than the height of wiring 32 from the main surface of insulating layer 20.
As illustrated in
The shape of the portion of via electrode 31 embedded in via hole 21 is the same as the shape of via hole 21. Therefore, in the present embodiment, the portion of via electrode 31 embedded in via hole 21 has a truncated cone shape with a sloping (tapered) side surface. The minimum diameter of the portion of via electrode 31 embedded in via hole 21 is larger than the width of wiring 32.
Via electrode 31 includes seed layer 31a provided as a lower layer in via electrode 31 and via electrode body layer 31b provided above seed layer 31a. In the present embodiment, seed layer 31a is the lowest layer of via electrode 31.
Seed layer 31a is formed on conductor 11 of substrate 10 in via hole 21. More specifically, seed layer 31a is formed on the top surface of conductor 11 so as to contact conductor 11. Seed layer 31a is formed along the inner side surface of insulating layer 20 from on top of conductor 11 in via hole 21.
In the present embodiment, seed layer 31a is formed up to a location above the main surface of insulating layer 20. Stated differently, seed layer 31a is formed over conductor 11 of substrate and the main surface of insulating layer 20. Seed layer 31a has a constant thickness. Accordingly, seed layer 31a is formed so as to ride up from conductor 11 in via hole 21 onto the main surface of insulating layer 20.
Seed layer 31a is a seed electrode including conductive material for forming via electrode body layer 31b by a plating method or a sputtering method. Seed layer 31a should therefore include a conductive material with low electrical resistance. In the present embodiment, seed layer 31a is, for example, a metal film of a metallic material including, for example, copper, which is a low-resistance material. In such cases, seed layer 31a does not include only copper, and may include another metal such as nickel in addition to copper. Seed layer 31a may be a single film including only one metal film, or a multilayer film including a plurality of stacked metal films.
Via electrode body layer 31b is a plating film stacked on seed layer 31a. In the present embodiment, via electrode body layer 31b is an electrolytic plating film formed by an electrolytic plating method. More specifically, via electrode body layer 31b is an electrolytic Cu plating film including copper.
Via electrode body layer 31b is formed so as to be located above seed layer 31a and fill via hole 21. In the present embodiment, via electrode body layer 31b is formed up to a location above insulating layer 20. More specifically, via electrode body layer 31b is formed on seed layer 31a, over conductor 11 and insulating layer 20. Stated differently, via electrode body layer 31b is formed to ride up from the inside of via hole 21 in insulating layer 20 onto the main surface of insulating layer 20.
Via electrode body layer 31b constitutes the majority of via electrode 31. In the present embodiment, via electrode body layer 31b constitutes 90% or more of via electrode 31 in the cross-sectional view of
Wiring 32 includes adhesion layer 32a provided as a lower layer in wiring 32 and wiring body layer 32b provided on adhesion layer 32a. In the present embodiment, adhesion layer 32a is the lowest layer of wiring 32. Although adhesion layer 32a is exemplified as located within insulating layer 20, adhesion layer 32a may be provided on the main surface of insulating layer 20.
Wiring 32 further includes conductive layer 32c provided on wiring body layer 32b. Stated differently, wiring 32 has a stacked structure in which adhesion layer 32a, wiring body layer 32b, and conductive layer 32c are stacked in this order in the direction leading away from insulating layer 20. In other words, wiring body layer 32b is sandwiched between adhesion layer 32a and conductive layer 32c. The bottom portion of wiring body layer 32b has the same line width as adhesion layer 32a.
Adhesion layer 32a is provided to facilitate adhesion between wiring 32 and insulating layer 20. Stated differently, adhesion layer 32a has a function or structure for enhancing the adhesion between wiring 32 and insulating layer 20. In the present embodiment, adhesion layer 32a has, as a structure for enhancing the adhesion between wiring 32 and insulating layer 20, a fine-textured structure. Although the entire layer of adhesion layer 32a has a fine-textured structure, adhesion layer 32a is not limited to such a configuration; when only a portion of adhesion layer 32a has a fine-textured structure, the fine-textured structure is formed on the side of adhesion layer 32a that faces insulating layer 20. In this way, by providing adhesion layer 32a with a fine-textured structure, adhesion layer 32a can more easily adhere to insulating layer 20 via an anchoring effect.
The fine-textured structure of adhesion layer 32a is, for example, a needle-like uneven shape with a height of 500 nm or less. As one example, adhesion layer 32a includes a metal film containing copper. In such cases, the fine-textured structure of adhesion layer 32a includes copper and/or copper oxide. More specifically, the fine-textured structure can be formed by roughening the copper surface by forming copper oxide with needle-like crystals. Instead of forming copper oxide, micro-roughening etching may be used to roughen the copper surface by slightly etching the surface to form a fine-textured structure. Note that adhesion layer 32a may include metallic elements other than copper.
Wiring body layer 32b is a plating film stacked below conductive layer 32c. In the present embodiment, wiring body layer 32b is an electroless plating film formed by an electroless plating method. More specifically, wiring body layer 32b is an electroless Cu plating film including copper.
Thus, wiring body layer 32b of wiring 32 and via electrode body layer 31b of via electrode 31 are both Cu plating films, but wiring body layer 32b is an electroless Cu plating film and via electrode body layer 31b is an electrolytic Cu plating film. Accordingly, the crystal grain size of the copper included in via electrode body layer 31b and the crystal grain size of the copper included in wiring body layer 32b are different. More specifically, the average crystal grain size of the copper included in via electrode body layer 31b, which is an electrolytic Cu plating film, is larger than the average crystal grain size of the copper included in wiring body layer 32b, which is an electroless plating film. Stated differently, the average crystal grain size of the copper included in wiring body layer 32b, which is an electroless plating film, is smaller than the average crystal grain size of the copper included in via electrode body layer 31b, which is an electrolytic Cu plating film.
Moreover, wiring body layer 32b of wiring 32 and via electrode body layer 31b of via electrode 31 are both plating films, but wiring 32 does not include a seed layer as a lower layer. Stated differently, via electrode 31 includes seed layer 31a as a lower layer, but wiring 32 does not include a seed layer as a lower layer.
Wiring body layer 32b of wiring 32 constitutes the majority of wiring 32. In the present embodiment, wiring body layer 32b constitutes 90% or more of wiring 32 in the cross-sectional view of
Conductive layer 32c formed on top of wiring body layer 32b functions as part of the conductor of wiring 32 and as a protective layer that protects wiring body layer 32b. Stated differently, conductive layer 32c inhibits wiring body layer 32b from being etched and reduced when the seed film is etched and patterned to form seed layer 31a of via electrode 31. Stated differently, wiring body layer 32b can be protected by conductive layer 32c when etching the seed film. Thus, conductive layer 32c functions as a protective layer that protects wiring body layer 32b during etching.
Like wiring body layer 32b, conductive layer 32c is also an electroless plating film. However, conductive layer 32c includes a different conductive material than wiring body layer 32b. In the present embodiment, since wiring body layer 32b includes copper, conductive layer 32c includes a conductive material other than copper. For example, conductive layer 32c includes a material containing any of nickel (Ni), palladium (Pd), platinum (Pt), or silver (Ag). Stated differently, conductive layer 32c is an electroless plating film containing any of these materials.
Next, the method for manufacturing wiring body 30 and the method for manufacturing mounting substrate 1 according to the present embodiment will be described with reference to
In the present embodiment, wiring body 30 and mounting substrate 1 are fabricated using wiring transfer plate 100. Wiring transfer plate 100 is a wiring pattern plate for forming a predetermined pattern of wiring (transfer wiring) to be transferred to another component (transfer target component). More specifically, wiring transfer plate 100 according to the present embodiment is a pattern plate used in a plating process for forming an electroless plating film as the transfer wiring. The electroless plating film formed by wiring transfer plate 100 becomes at least part of the wiring that is transferred to another component.
Hereinafter, the method for manufacturing wiring body 30 and mounting substrate 1 using wiring transfer plate 100 will be described.
First, as illustrated in
More specifically, as illustrated in (a) in
Next, the method for fabricating wiring transfer plate 100 will be described with reference to
First, as illustrated in (a) in
Then, as illustrated in (b) in
Then, as illustrated in (c) and (d) in
Then, as illustrated in (e) in
Note that in wiring transfer plate 100 fabricated in this way, plating base material layer 130 functions as a release layer, but a release treatment may be performed on plating base material layer 130 to provide additional releasing properties. To give plating base material layer 130 releasing properties is to weaken the catalytic reaction effect of plating base material layer 130. For example, plating base material layer 130 exposed from insulating layer 120 can be oxidized to give plating base material layer 130 releasing properties. The release treatment of plating base material layer 130 is not limited to oxidation.
Moreover, in
Next, using wiring transfer plate 100 fabricated in this way, wiring 32, which will be the transfer wiring, is formed on wiring transfer plate 100.
More specifically, first, as illustrated in (b) and (c) in
Note that when conductive layer 32c is an electroless Ni film or an electroless silver plating film, since the electroless Ni film or the electroless silver plating film can be removed with almost no erosion of Cu when making the wiring body in a later process, the wiring body can be easily structured only of Cu. If electroless Ni film remains, there is concern that the wiring resistance of the wiring body will increase because the electroless Ni film generally includes substances such as boron and phosphorus, which have high resistance. There is also concern that the high-frequency characteristics, etc., will be degraded due to the electroless Ni film being magnetic. In addition, there is concern that reliability characteristics may be degraded because silver is a metal that is prone to ion migration. Therefore, if conductive layer 32c is an electroless Ni film or an electroless silver plating film, conductive layer 32c may be removed. In such cases, regarding wiring body 30A of the mounting substrate according to the variation where conductive layer 32c is removed, a cross-sectional view of wiring between vias in the mounting substrate corresponding to line II-II in
However, when conductive layer 32c is an electroless Pd film or an electroless Pt film, since the electroless Pd film or the electroless Pt film generally contains few impurities, the surface resistance of the wiring can be kept low, and it is also advantageous in regard to high-frequency characteristics because it is not magnetic. Moreover, the Pd or Pt included in the electroless Pd or the electroless Pt film is a stable metal compared to Cu, so it can also function as a barrier layer to inhibit ion migration.
As described in Embodiment 2 below, depending on the material of plating base material layer 130, it is possible to form only wiring body layer 32b including an electroless Cu plating film, without forming conductive layer 32c. Stated differently, at least wiring body layer 32b should be formed on plating base material layer 130. Conductive layer 32c is preferably an electroless plating film. By making conductive layer 32c an electroless plating film, conductive layer 32c can be formed uniform in thickness. However, conductive layer 32c may be an electrolytic plating film instead of an electroless plating film.
Next, as illustrated in (d) in
Wiring-equipped wiring transfer plate 200 fabricated in this way allows wiring 32 to be transferred to other components. Stated differently, conductive layer 32c and wiring body layer 32b, which are electroless plating films, and adhesion layer 32a constitute wiring 32, which is transfer wiring to be transferred to another component.
Note that wiring transfer plate 100 after transferring wiring 32 of wiring-equipped wiring transfer plate 200 to another component returns to the state illustrated in (a) in
In the present embodiment, wiring-equipped wiring transfer plate 200 is used to fabricate wiring body 30 and mounting substrate 1. This will be described next with reference to
First, as illustrated in (a) through (c) in
More specifically, as illustrated in (a) in
Next, as illustrated in (b) in
More specifically, an insulating material that will become insulating layer 20 is disposed on substrate 10 including conductor 11, and wiring-equipped wiring transfer plate 200 is placed on top of the insulating material. Stated differently, the insulating material of insulating layer 20 is inserted between substrate 10 and wiring-equipped wiring transfer plate 200. Here, wiring-equipped wiring transfer plate 200 is arranged so that the exposed wiring 32 is on the insulating layer 20 side.
For example, when a fluid liquid insulating resin material is used as the insulating material for insulating layer 20, the liquid insulating resin material is applied on substrate 10 including conductor 11, and wiring-equipped wiring transfer plate 200 is disposed on top thereof and the liquid insulating resin material is cured. If the liquid insulating resin material is a thermosetting resin, it is cured by heating or drying, and if the liquid insulating resin material is a photo-curable resin, it is cured by light irradiation. This allows insulating layer 20 to be formed between substrate 10 and wiring-equipped wiring transfer plate 200.
When a film-like insulating resin sheet is used as the insulating material for insulating layer 20, the film-like insulating resin sheet is disposed on substrate 10 including conductor 11, and wiring-equipped wiring transfer plate 200 is disposed on top thereof and thermocompression bonded. At this time, wiring-equipped wiring transfer plate 200 is pressed toward substrate 10. This allows insulating layer 20 to be formed between substrate 10 and wiring-equipped wiring transfer plate 200.
Next, as illustrated in (c) in
In the present embodiment, wiring 32 is easily separated from plating base material layer 130 of wiring transfer plate 100 because plating base material layer 130 has releasing properties, and adhesion layer 32a easily adheres to insulating layer 20 because adhesion layer 32a is formed on wiring 32 via an adhesion treatment. This allows wiring 32 to be easily transferred to insulating layer 20.
When a film-like insulating resin sheet is used as the insulating material for insulating layer 20, the insulating resin sheet should have adhesive properties. This makes it easier for adhesion layer 32a of wiring 32 to adhere to insulating layer 20, so wiring 32 can be transferred to insulating layer 20 more easily.
Next, as illustrated in (d) in
Next, as illustrated in (e) in
More specifically, after desmearing and removing the residue of insulating layer 20 by laser treatment, seed film 35 is formed over the entire upper surface of substrate 10 by an electroless plating method or sputtering. Therefore, seed film 35 is formed not only on the exposed surfaces of conductor 11 and wiring 32, but also on the exposed surface of exposed insulating layer 20.
Note that in the present embodiment, seed film 35 is, for example, a metal film of a metallic material including copper. In such cases, seed film 35 may include only copper, and, alternatively, may include copper and another metal such as nickel.
Next, as illustrated in (f) in
Next, as illustrated in (g) in
As illustrated in (g) in
Next, as illustrated in (h) in
Next, as illustrated in (i) in
In this way, wiring body 30 including via electrode 31 and wiring 32 is formed and mounting substrate 1 including wiring body can be fabricated. Stated differently, it is possible to fabricate wiring body 30 on substrate 10 including conductor 11 and also to fabricate mounting substrate 1 including wiring body 30 disposed above substrate 10.
Next, the features of the method for manufacturing wiring body 30 and the method for manufacturing mounting substrate 1 according to the present embodiment will be explained by comparison with a conventional method for manufacturing mounting substrate 1X, with reference to
In the conventional method for manufacturing mounting substrate 1X, first, as illustrated in (a) in
Next, after desmearing, seed film 35X including an electroless plating film is formed over the entire upper surface of substrate 10 by an electroless plating method, as illustrated in (c) in
Next, as illustrated in (d) in
Next, as illustrated in (e) in
Next, as illustrated in (f) in
Next, the exposed seed film 35X is removed by etching. This leaves seed film 35X under via electrode body layer 31b and this seed film 35X becomes seed layer 31a, forming via electrode 31X, as illustrated in (g) in
In this way, mounting substrate 1X including via electrode 31X and wiring 32X can be fabricated.
However, because the line width of wiring 32X is smaller than the diameter of via electrode 31X, with the conventional method for manufacturing mounting substrate 1X, the lower layer of wiring 32X is undercut by over-etching in the process of removing exposed seed film 35, as illustrated in (g) in
In contrast, in wiring body 30 according to the present embodiment, the material or structure of the lower layer in via electrode 31 and the material or structure of the lower layer in wiring 32 are different, as described above. In the present embodiment, the lower layer in via electrode 31 is seed layer 31a and the lower layer in wiring 32 is adhesion layer 32a, and the material or structure of seed layer 31a and the material or structure of adhesion layer 32a are different. In the present embodiment, seed layer 31a and adhesion layer 32a both include copper, but include different materials or structures. Stated differently, seed layer 31a and adhesion layer 32a are metal films including a same metal element, copper, but at least one of seed layer 31a or adhesion layer 32a includes a metal film including a metal element other than copper or is formed so that the copper surface has a fine-textured structure, whereby the material or structure of seed layer 31a and the material or structure of adhesion layer 32a are different.
Thus, in the present embodiment, the lower layer of wiring 32 is adhesion layer 32a, i.e., wiring 32, unlike via electrode 31, does not include a seed layer as a lower layer. Via electrode 31, however, does not include an adhesion layer as a lower layer.
As illustrated in (i) in
Therefore, with wiring body 30 and mounting substrate 1 according to the present embodiment, wiring 32 can be made finer and disposed at a narrower pitch even if it includes via electrode 31.
A method for manufacturing wiring body 30 and a method for manufacturing mounting substrate 1 according to the present embodiment includes: disposing wiring 32 above substrate 10 with insulating layer 20 interposed therebetween; after disposing wiring 32, forming via hole 21 in insulating layer 20 so as to expose conductor 11 of substrate 10 by removing a portion of insulating layer 20; after forming via hole 21, forming seed film 35 so as to cover the exposed conductor 11 and wiring 32; after forming seed film 35, selectively forming resist 40 on a portion of seed film 35 covering wiring 32 so as to expose a portion of seed film 35 covering conductor 11; after selectively forming resist 40, forming via electrode body layer 31b on the exposed seed film 35; and after forming via electrode body layer 31b, removing seed film 35 covering wiring 32 after removing resist 40.
With this, since wiring 32 can be protected by seed film 35 to form via electrode body layer 31b, even with wiring body 30 and mounting substrate 1 including via electrode 31, wiring 32 can be made finer and disposed at a narrower pitch. For example, wiring 32 that is finer and disposed at a narrower pitch can be built into the same wiring layer as via electrode 31.
In the present embodiment, wiring 32 includes adhesion layer 32a, which is provided as a lower layer in wiring 32 and includes a fine-textured structure, and wiring body layer 32b, which is provided on adhesion layer 32a.
Thus, by providing adhesion layer 32a on wiring 32, adhesion between wiring 32 and insulating layer 20 can be sufficiently ensured.
In the present embodiment, wiring 32 further includes conductive layer 32c provided on wiring body layer 32b and including conductive material different from that of wiring body layer 32b.
This allows conductive layer 32c to protect wiring body layer 32b when seed layer 31a of via electrode 31 is patterned by etching seed film 35. Stated differently, selective etching using the etching rate difference between seed film 35 and wiring body layer 32b becomes possible. This can inhibit the line width of wiring 32 from changing due to the thinning of film when etching seed film 35.
In the present embodiment, wiring 32 is formed by a transfer method. More specifically, wiring 32 is formed using wiring transfer plate 100.
This allows fine wiring 32 to be formed with high precision even if the surface (transfer target surface) of substrate 10, which is the transfer target component, has unevenness due to, for example, wiring or electrodes. Stated differently, when wiring is formed by a photolithography method, if there is unevenness on the surface of the portion where wiring is formed, the focus is shifted and fine wiring cannot be formed precisely. However, by forming wiring 32 using a transfer method like in the present embodiment, even if the surface of the area where wiring 32 has unevenness, i.e., is not flat, the effect that unevenness has can be reduced and fine wiring 32 can be formed with high precision.
Moreover, by using a rigid glass or metal substrate as base 110 of wiring transfer plate 100, wiring 32 can be formed with high positioning accuracy.
In the present embodiment, the crystal grain size of the copper included in via electrode body layer 31b and the crystal grain size of the copper included in wiring body layer 32b are different.
This allows via electrode body layer 31b and wiring body layer 32b to be formed using different manufacturing methods according to required characteristics other than low resistance. For example, via electrode body layer 31b and wiring body layer 32b can be formed by different plating methods.
In such cases, via electrode body layer 31b of via electrode 31 is an electrolytic plating film formed by an electrolytic plating method and constitutes 90% or more of via electrode 31 in a cross-sectional view.
Thus, by making via electrode body layer 31b a comparatively low-stress electrolytic plating film, it is possible to inhibit the occurrence of plating peeling and cracks in via electrode 31 due to internal stress.
In contrast, wiring body layer 32b of wiring 32 is an electroless plating film formed by an electroless plating method and constitutes 90% or more of wiring 32 in a cross-sectional view.
By using an electroless plating method, it is easy to form a plurality of lines of wiring 32 with a large surface area and uniform film thickness. This allows the formation of a plurality of lines of wiring 32 with high film thickness uniformity and uniform wiring resistance. Stated differently, it is possible to realize wiring body 30 and mounting substrate 1 including wiring 32 with uniform wiring resistance in all regions.
The line width of wiring 32 according to the present embodiment should be 5 μm or less, and more preferably 2 μm or less. By making wiring 32 fine wiring as described above, it is possible to pass a large number of lines of fine wiring between vias, enabling high-density mounting with a small number of wiring layers. Furthermore, variation in the thickness of wiring 32 according to the present embodiment is less than ±10% or ±1 μm. By forming wiring 32, which is fine wiring with such thickness variation, it is possible to inhibit variation in characteristic impedance.
Wiring body 30 fabricated in this way can be used as a wiring layer or redistribution layer (RDL) in a semiconductor package substrate.
For example, as illustrated in
As illustrated in
As another example, wiring body 30 can be used as a redistribution layer in a mounting substrate that is a Fan Out-Wafer Level Package (FO-WLP).
Mounting substrates 1A, 1B, and 1C illustrated in
Moreover, wiring body 30 can also be applied to a build-up layer (wiring layer) of a typical build-up substrate, rather than the redistribution layer. For example, wiring body 30 can be applied to the wiring layer of substrate 10, which is the build-up substrate illustrated in
Next, the configurations of wiring body 30D and mounting substrate 1D according to Embodiment 2 will be described with reference to
In wiring 32 in Embodiment 1 described above, conductive layer 32c is formed on top of wiring body layer 32b, but as illustrated in
In wiring body 30 and mounting substrate 1 in Embodiment 1 described above, seed layer 31a of via electrode 31 and wiring body layer 32b of wiring 32 included the same metal, but in wiring body 30D and mounting substrate 1D according to the present embodiment, seed layer 31aD of via electrode 31D and wiring body layer 32b of wiring 32D include different types of metals. More specifically, in Embodiment 1 described above, both seed layer 31a and wiring body layer 32b are metal films including copper, but in the present embodiment, wiring body layer 32b is a metal film including only copper, while seed layer 31aD is a metal film including a metal other than copper. Stated differently, in the present embodiment, wiring body layer 32b of wiring 32D is the same as in Embodiment 1 described above, but seed layer 31aD of via electrode 31D includes a metal other than copper, unlike in Embodiment 1 described above.
Note that wiring body 30D and mounting substrate 1D according to the present embodiment are the same as wiring body 30 and mounting substrate 1 according to Embodiment 1 described above except that wiring 32D does not include conductive layer 32c and that seed layer 31aD and wiring body layer 32b include different types of metals.
Wiring body 30D and mounting substrate 1D configured as described above are manufactured by the method illustrated in
Wiring-equipped wiring transfer plate 200D, in which wiring 32D is formed on wiring transfer plate 100, is also used in the present embodiment as well. Stated differently, in the present embodiment as well, wiring 32D is formed by a transfer method using wiring-equipped wiring transfer plate 200D that is prepared in advance. However, in wiring-equipped wiring transfer plate 200D, wiring 32D does not include conductive layer 32c. More specifically, wiring 32D includes wiring body layer 32b and adhesion layer 32a.
First, as illustrated in (a) through (c) in
More specifically, as illustrated in (a) in
Next, as illustrated in (b) in
Next, as illustrated in (c) in
Next, as illustrated in (d) in
Next, as illustrated in (e) in
Next, as illustrated in (f) in
Next, as illustrated in (g) in
Next, as illustrated in (h) in
Next, as illustrated in (i) in
In the present embodiment, since wiring body layer 32b of wiring 32D includes a different metal than seed film 35D, seed film 35D can be selectively etched without etching wiring body layer 32b. By etching seed film 35D in this way, only seed film 35D under via electrode body layer 31b remains, and this seed film 35D becomes seed layer 31aD. This allows the formation of via electrode 31D including stacked seed layer 31aD and via electrode body layer 31b.
In this way, wiring body 30D including via electrode 31D and wiring 32D is formed and mounting substrate 1D including wiring body 30D can be fabricated. Stated differently, it is possible to fabricate wiring body 30D on substrate 10 including conductor 11 and also to fabricate mounting substrate 1D including wiring body 30D disposed above substrate 10.
In this way, in wiring body 30D according to the present embodiment, as in wiring body 30 according to the above embodiment, the lower layer in via electrode 31D and the lower layer in wiring 32D include different conductive materials. More specifically, in the present embodiment as well, seed layer 31aD, which is the lower layer in via electrode 31D, and adhesion layer 32a, which is the lower layer in wiring 32D, include different conductive materials. Moreover, in the present embodiment as well, the lower layer of wiring 32D is adhesion layer 32a, and wiring 32D does not include a seed layer as a lower layer. Moreover, via electrode 31D does not include an adhesion layer as a lower layer.
This inhibits the undercutting of the lower layer of wiring 32D in the etching and patterning of seed film 35D to form seed layer 31aD, which becomes the lower layer of via electrode 31D, and thus inhibits the line width of the lower layer of wiring 32D from being reduced.
Therefore, in wiring body 30D and mounting substrate 1D according to the present embodiment as well, wiring 32D can be made finer and disposed at a narrower pitch.
In the present embodiment, although wiring 32D does not include conductive layer 32c, and wiring body layer 32b is not protected by conductive layer 32c when seed film 35D is etched, since seed film 35D and wiring body layer 32b include different types of metals, it is possible to selectively etch using the etching rate difference between seed film 35D and wiring body layer 32b. Stated differently, although conductive layer 32c is not formed on top of wiring body layer 32b, when seed layer 31aD is etched with an etchant, wiring body layer 32b can be prevented from being removed by the etchant. This can inhibit the line width of wiring 32D from changing due to the thinning of film when etching seed film 35D.
In the present embodiment, wiring 32D does not include conductive layer 32c, but wiring 32D may include conductive layer 32c.
Next, the configurations of wiring body 30E and mounting substrate 1E according to Embodiment 3 will be described with reference to
In Embodiment 1 described above, via electrode 31 includes seed layer 31a and via electrode body layer 31b, which is an electrolytic plating film stacked on seed layer 31a, but this example is non-limiting.
More specifically, as illustrated in
Note that except for the configuration of via electrode 31E, wiring body 30E and mounting substrate 1E according to the present embodiment are the same as wiring body 30 and mounting substrate 1 according to Embodiment 1 described above.
Wiring body 30E and mounting substrate 1E configured as described above are manufactured by the method illustrated in
Wiring-equipped wiring transfer plate 200, in which wiring 32 is formed on wiring transfer plate 100, is also used in the present embodiment as well. Stated differently, in the present embodiment as well, wiring 32 is formed by a transfer method using wiring-equipped wiring transfer plate 200 that is prepared in advance.
First, as illustrated in (a) through (c) in
Next, as illustrated in (d) in
Next, as illustrated in (e) in
In this way, wiring body 30E including via electrode 31E and wiring 32 is formed and mounting substrate 1E including wiring body 30E can be fabricated. Stated differently, it is possible to fabricate wiring body 30E on substrate 10 including conductor 11 and also to fabricate mounting substrate 1E including wiring body 30E disposed above substrate 10.
In this way, in wiring body 30E according to the present embodiment, as in wiring body 30 according to the above embodiment, the lower layer in via electrode 31E and the lower layer in wiring 32 include different conductive materials. More specifically, in the present embodiment, the lower layer in via electrode 31E is part of via electrode 31E, which includes conductive paste, and includes a different conductive material than adhesion layer 32a, which is the lower layer in wiring 32.
Thus, since there is no seed layer in via electrode 31E, there is no need to etch the seed layer when forming via electrode 31E. Therefore, the lower layer of wiring 32 is not undercut in a seed layer etching process, and the line width of the lower layer of wiring 32 is not reduced.
Therefore, in wiring body 30E and mounting substrate 1E according to the present embodiment as well, wiring 32 can be made finer and disposed at a narrower pitch.
Next, the configurations of wiring body 30F and mounting substrate 1F according to Embodiment 4 will be described with reference to
In Embodiment 1 described above, wiring 32 includes adhesion layer 32a including a fine-textured structure, wiring body layer 32b, which is an electroless plating film of Cu, and conductive layer 32c (a protective layer), which is an electroless plating film of Cu.
More specifically, as illustrated in
In the present embodiment, adhesion layer 32aF is not a fine-textured structure formed by copper oxide treatment, etc., but an organic thin film formed by organic adhesion treatment. For example, by introducing an organic component having high adhesion strength with the resin included in insulating layer 20 onto the surface of the copper included in wiring body layer 32bF, an organic thin film including an organic component chemically bonded to the resin included in insulating layer 20 and an organic component chemically bonded to the copper included in wiring body layer 32bF can be formed as adhesion layer 32aF. When adhesion layer 32a is formed by copper oxide treatment, there is a possibility that wiring 32 will peel off during etching because copper oxide is weak against acid. However, by forming adhesion layer 32aF by organic adhesion treatment as in the present embodiment, such defects can be inhibited.
In the present embodiment, wiring body layer 32bF is an electroplating film, not an electroless plating film. More specifically, wiring body layer 32bF is an electroplating film including copper.
Another layer including an electroless plating film may be inserted between adhesion layer 32aF and wiring body layer 32bF. In such cases, conductive layer 32c functioning as a protective layer becomes unnecessary because of the etching selectivity between the electroplating film and the electroless plating film.
Note that except for the configuration of wiring 32F, wiring body 30F and mounting substrate 1F according to the present embodiment are the same as wiring body 30 and mounting substrate 1 according to Embodiment 1 described above. The present embodiment can be applied not only to Embodiment 1 described above, but also to Embodiments 2 and 3 described above.
Hereinbefore, the wiring body and mounting substrate according to the present disclosure have been described based on embodiments, but the present disclosure is not limited to Embodiments 1 through 3 described above.
For example, in Embodiment 1 described above, when forming seed layer 31a of via electrode 31, seed layer 31a is formed by etching seed film 35 covering wiring 32 with an etchant, but this example is non-limiting. More specifically, seed layer 31a of via electrode 31 may be formed by a lift-off method. Next, this method will be described with reference to
First, as illustrated in (a) through (c) in
Next, as illustrated in (d) in
Next, as illustrated in (e) in
Next, as illustrated in (f) in
Next, as illustrated in (g) in
Next, as illustrated in (h) in
In this way, wiring body 30 including via electrode 31 and wiring 32 is formed and mounting substrate 1 including wiring body can be fabricated. Stated differently, it is possible to fabricate wiring body 30 on substrate 10 including conductor 11 and also to fabricate mounting substrate 1 including wiring body 30 disposed above substrate 10. Note that the present variation can also be applied to Embodiment 2 described above.
In Embodiments 1 through 4 described above, insulating layer 120 that serves as the transfer plate insulating layer in wiring transfer plate 100 is a resist, but this is non-limiting. For example, insulating layer 120 may be an insulating resin material including an inorganic material such as SiO2. In such cases, wiring transfer plate 100B including insulating layer 120B can be fabricated by the method illustrated in
First, as illustrated in (a) in
In Embodiments 1 through 4 described above, the electroless plating film may be an electroplating film, and the electroplating film may be an electrolytic plating film. Stated differently, the electroless plating film and the electroplating film may simply be plating films without distinction.
Embodiments arrived at by a person of skill in the art making various modifications to the above embodiments as well as embodiments realized by arbitrarily combining elements and functions in the embodiments which do not depart from the essence of the present disclosure are included in the present disclosure.
The wiring body according to the present disclosure is applicable as a wiring layer or the like in mounting substrates such as semiconductor package substrates.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-047323 | Mar 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/011943 | 3/16/2022 | WO |
