The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, as integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate). An MBC transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed from nanowires, nanosheets, other nanostructures, and/or other suitable structures. The shapes of the channel region have also given an MBC transistor alternative names such as a nanosheet transistor or a nanowire transistor.
Silicide layers are implemented at interfaces between source/drain contacts and epitaxial source/drain features to reduce contact resistance. Gate pitches shrink as dimensions of semiconductor devices continue to decrease. The smaller gate pitches create challenges in silicide formation.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within +/−10% of the number described, unless otherwise specified. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
Transistors on modern-day IC devices include planar transistors or multi-gate transistors. A planar device refers to a device having a gate structure that engages a planar surface of a semiconductor active region. Multi-gate devices refer to those whose gate structures are formed on at least two-sides of a channel region. Examples of multi-gate devices include fin-like field effect transistors (FinFETs) having fin-like structures and MBC transistors having a plurality of a channel members. As described above, MBC transistors may also be referred to as SGTs, GAA transistors, nanosheet transistors, or nanowire transistors. These multi-gate devices may be either n-type or p-type. An MBC transistor includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). MBC devices may have channel regions disposed in nanowire channel members, bar-shaped channel members, nanosheet channel members, nanostructure channel members, bridge-shaped channel members, and/or other suitable channel configurations. Both planar devices and multi-gate devices may include epitaxially grown source/drain features that may extend vertically and laterally beyond top surfaces and sidewalls of the active region. A silicide layer is formed at an interface between a source/drain feature and a metal contact feature to reduce contact resistance. In some existing processes, one or more dielectric layer is deposited over a source/drain feature and an opening is formed in the one or more dielectric layer to expose a portion of the source/drain feature. A pre-clean process and silicide formation are then performed with respect to the exposed portion in the opening. As gate pitches continue to shrink, these existing processes may run into challenges in forming a silicide layer satisfactorily.
The present disclosure provides a process and a structure to form wrap-around silicide layer that wraps over a top surface and sidewalls of source/drain features. In an example embodiment, after a source/drain feature is epitaxially deposited, a first contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer are deposited over the source/drain feature. The first ILD layer is selectively etched away with a wet etching process and the first CESL is anisotropically etched to expose the top surface and sidewalls of the source/drain feature. A silicide layer is then deposited to wrap over the source/drain feature. Thereafter, a second CESL and a second ILD layer are deposited over the silicide layer. Because the silicide layer is formed between the first CESL and the second CESL, the process may also be referred to as a silicide-middle process or salicide-middle process. Due to the fact that the wrap-around silicide layer is formed on a larger exposed surface, the process has an improved process window. The additional contact surface between the wrap-around silicide layer and the source/drain feature also reduces contact resistance.
The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,
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The substrate 202 may include an elementary (single element) semiconductor, such as silicon (Si), germanium (Ge), and/or other suitable materials; a compound semiconductor (i.e., alloy semiconductor), such as silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium phosphide (GaInAsP), and/or other suitable materials. The substrate 202 may be a single-layer material having a uniform composition. Alternatively, the substrate may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a buried silicon oxide (BOX) layer. In some embodiments, the substrate includes various doped regions, such as n-type wells or p-type wells. The doped regions may be doped with n-type dopants, such as phosphorus (P) or arsenic (As), and/or p-type dopants, such as boron (B) or BF2, depending on design requirements. Doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques. In the depicted embodiments, the substrate 202 includes silicon (Si).
The isolation feature 203 may also be referred to as a shallow trench isolation (STI) feature 203. The isolation feature 203 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. The gate spacer 214 may be a single layer or a multi-layer. In some instances, the gate spacer 214 may include silicon oxide, silicon oxycarbide, silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, a suitable low-k dielectric material, or a suitable dielectric material. The metal oxides here may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxide. Depending on the type of the devices, the source epitaxial feature 212 may be n-type or p-type. When the source/drain feature 212 is n-type, it includes silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenide (As). When the source/drain feature 212 is p-type, it includes silicon germanium (SiGe) doped with a p-type dopant, such as boron (B).
The gate structure 210 includes an interfacial layer 206, a gate dielectric layer 207 over the interfacial layer 206, and a gate electrode 208 over the gate dielectric layer 207. In some embodiments, the interfacial layer 206 includes silicon oxide and may be formed on semiconductor surfaces (such as silicon surfaces of the fin structure 204) in a pre-clean process. An example pre-clean process may include use of RCA SC-1 (ammonia, hydrogen peroxide and water) and/or RCA SC-2 (hydrochloric acid, hydrogen peroxide and water). The gate dielectric layer 207 may include a high-k dielectric material that has a dielectric material with a dielectric constant greater than that of silicon dioxide, which is about 3.9. In some instances, the gate dielectric layer 207 may include hafnium oxide (HfO), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable material. In one embodiment, the gate dielectric layer 207 includes hafnium oxide. The gate electrode 208 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the gate electrode may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof.
In some embodiments, the first CESL 218 is first conformally deposited on the workpiece 200, including over the source/drain feature 212, using ALD or CVD. The first ILD layer 220 is deposited over the first CESL 218 by spin-on coating, FCVD. CVD, or other suitable deposition technique. The first ILD layer 220 may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, after formation of the first ILD layer 220, the workpiece 200 may be annealed to improve integrity of the first ILD layer 220.
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After formation of the patterned hard mask 240, the first ILD layer 220 is selectively etched away using an isotropic wet etching process. In some embodiments, the isotropic wet etch may be a buffered oxide etch (BOE) that uses hydrofluoric acid (HF) and ammonium fluoride (NH4F). In some other embodiments, the isotropic wet etch may include use of dilute hydrofluoric acid (DHF). In embodiments where the first CESL 218 is formed of silicon nitride or silicon oxynitride, the selective wet etch is capable of substantially etching away the first ILD layer 220 without substantially etching the first CESL 218. After the first ILD layer 220 is etched away, an anisotropic etch process is performed to breach the first CESL 218 so as to expose the source/drain feature 212 in the source/drain access trench 222. For example, the anisotropic etch process may be a reactive-ion etching (RIE) process that includes use of a bromine-containing gas (e.g., HBr and/or CHBr3), a fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3, and/or C2F6), a carbon-containing gas (e.g., CH4 or C2H6), other suitable gases, or combinations thereof. As shown in
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In one exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes an active region extending along a first direction and including a first channel region, a second channel region, and a source/drain region sandwiched between the first channel region and the second channel region along the first direction, a first gate structure disposed over the first channel region and extending lengthwise along a second direction perpendicular to the first direction, a second gate structure disposed over the second channel region and extending lengthwise along the second direction, a source/drain feature disposed over the source/drain region, a first gate spacer disposed along a sidewall of the first gate structure, a second gate spacer disposed along a sidewall of the second gate structure, a first contact etch stop layer (CESL) disposed over a top surface of the source/drain feature and extending along sidewalls of the first gate spacer and the second gate spacer, a second CESL disposed over the top surface of the source/drain feature and extending along sidewalls of the first CESL, and a contact plug extending through the second CESL such that the second CESL is sandwiched between first CESL and the contact plug.
In some embodiments, the semiconductor structure further includes a silicide layer wrapping over the top surface and sidewalls if the source/drain feature. The contact plug is electrically coupled to the source/drain feature by way of the silicide layer. In some implementations, the silicide layer undercuts the second CESL. In some instances, the silicide layer further undercuts the first CESL. In some embodiments, the silicide layer extends between a sidewall of the source/drain feature and the second CESL. In some embodiments, top surfaces of the first gate structure, the second gate structure, the first gate spacer, the second gate spacer, the first CESL, and the second CESL are coplanar. In some instances, the semiconductor structure further includes an etch stop layer (ESL) disposed on and in contact with the top surfaces of the first gate structure, the second gate structure, the first gate spacer, the second gate spacer, the first CESL, and the second CESL. In some embodiments, a bottom surface of the second CESL extends further into the source/drain feature than a bottom surface of the first CESL.
In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure a channel region of a semiconductor body rising above an isolation feature, a gate structure wrapping over the channel region, a source/drain feature in contact with a sidewall of the channel region, a backside silicide layer disposed on a bottom surface of the source/drain feature, and a backside contact feature extending through the isolation feature to contact a bottom surface of the backside silicide layer. A sidewall of the backside contact feature is spaced apart from the isolation feature by a first backside contact etch stop layer (CESL) and a second backside CESL.
In some embodiments, the semiconductor structure further includes a gate spacer disposed along a sidewall of the gate structure, a first frontside CESL disposed over a top surface of the source/drain feature and extending along a sidewall of the gate spacer, a second frontside CESL disposed over the top surface of the source/drain feature and extending along a sidewalls of the first frontside CESL, and a contact plug extending along the second CESL to electrically coupled to the source/drain feature by way of a frontside silicide layer. In some implementations, the frontside silicide layer wraps over a top surface and sidewalls of the source/drain feature. In some embodiments, the first frontside CESL, the second frontside CESL, the first backside CESL, and the second backside CESL include silicon nitride. In some embodiments, the frontside silicide layer undercuts the second frontside CESL. In some instances, the frontside silicide layer further undercuts the first frontside CESL.
In yet another exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece that includes an active region extending along a first direction and including a first channel region, a second channel region, and a source/drain region sandwiched between the first channel region and the second channel region along the first direction, a first gate structure disposed over the first channel region and extending lengthwise along a second direction perpendicular to the first direction, a second gate structure disposed over the second channel region and extending lengthwise along the second direction, a source/drain feature disposed over the source/drain region, a first gate spacer disposed along a sidewall of the first gate structure, a second gate spacer disposed along a sidewall of the second gate structure, a first contact etch stop layer (CESL) disposed over a top surface of the source/drain feature and extending along sidewalls of the first gate spacer and the second gate spacer, a first interlayer dielectric (ILD) layer disposed over the first CESL. The method further includes etching the first ILD layer and the first CESL to form a source/drain access trench to exposes a top surface and sidewalls of the source/drain feature, after the etching, depositing a silicide layer to wrap over the top surface and sidewalls of the source/drain feature, depositing a second CESL layer over the source/drain access trench, including over the silicide layer, depositing an second ILD layer over the second CESL layer, etching the second ILD layer and the second CESL to form a source/drain contact opening to exposes a top surface of the source/drain feature, and forming a contact plug over the source/drain contact opening.
In some embodiments, the silicide layer includes TiSi, ZrSi, SbSi, BiSi, NiSi, SnSi, MoSi, or a combination thereof. In some implementations, the contact plug includes W, Ru, Co, Cu, Mo, TaN, or TiN. In some instances, the etching of the first ILD layer and the first CESL includes isotropically etching the first ILD layer, and anisotropically etching the first CESL to expose the top surface of the source/drain feature. In some embodiments, after the etching of the first ILD layer and the first CESL, a portion of the first CESL remains disposed along the sidewalls of the first gate spacer and the second gate spacer. In some implementations, the silicide layer extends between the top surface of the source/drain feature and a bottom surface of the second CESL.
The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims benefit of U.S. Provisional Patent Application Ser. No. 63/486,813, filed Feb. 24, 2023, the entirety of which is incorporated by reference.
Number | Date | Country | |
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63486813 | Feb 2023 | US |