David L. Roper

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Modified core for circuit module system and method
- Patent number 7,760,513
- Issue date Jul 20, 2010
- Entorian Technologies LP
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stacked module systems
- Patent number 7,656,678
- Issue date Feb 2, 2010
- Entorian Technologies, LP
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low profile stacking system and method
- Patent number 7,626,273
- Issue date Dec 1, 2009
- Entorian Technologies, LP
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system
- Patent number 7,606,048
- Issue date Oct 20, 2009
- Enthorian Technologies, LP
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Flex-based circuit module
- Patent number 7,595,550
- Issue date Sep 29, 2009
- Entorian Technologies, LP
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system
- Patent number 7,586,758
- Issue date Sep 8, 2009
- Entorian Technologies, LP
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and integrated circuit stacking system and method
- Patent number 7,542,304
- Issue date Jun 2, 2009
- Entorian Technologies, LP
- Russell Rapport
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit stacking system and method
- Patent number 7,524,703
- Issue date Apr 28, 2009
- Entorian Technologies, LP
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Split core circuit module
- Patent number 7,522,421
- Issue date Apr 21, 2009
- Entorian Technologies, LP
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Managed memory component
- Patent number 7,508,069
- Issue date Mar 24, 2009
- Entorian Technologies, LP
- James Douglas Wehrly, Jr.
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stacking system and method
- Patent number 7,495,334
- Issue date Feb 24, 2009
- Entorian Technologies, LP
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Modularized die stacking system and method
- Patent number 7,485,951
- Issue date Feb 3, 2009
- Entorian Technologies, LP
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system and method
- Patent number 7,335,975
- Issue date Feb 26, 2008
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stacked module systems and method
- Patent number 7,323,364
- Issue date Jan 29, 2008
- Staktek Group L.P.
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Managed memory component
- Patent number 7,304,382
- Issue date Dec 4, 2007
- Staktek Group L.P.
- James Douglas Wehrly, Jr.
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Leaded package integrated circuit stacking
- Patent number 7,259,452
- Issue date Aug 21, 2007
- Staktek Group L.P.
- James Douglas Wehrly, Jr.
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and chip scale stacking system and method
- Patent number 7,256,484
- Issue date Aug 14, 2007
- Staktek Group L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Pitch change and chip scale stacking system and method
- Patent number 7,202,555
- Issue date Apr 10, 2007
- Staktek Group L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low profile stacking system and method
- Patent number 7,180,167
- Issue date Feb 20, 2007
- Staktek Group L.P.
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low profile chip scale stacking system and method
- Patent number 7,094,632
- Issue date Aug 22, 2006
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Flexible circuit connector for stacked chip module
- Patent number 7,066,741
- Issue date Jun 27, 2006
- Staktek Group L.P.
- Carmen D. Burns
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pitch change and chip scale stacking system
- Patent number 7,053,478
- Issue date May 30, 2006
- Staktek Group L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stacked module systems and method
- Patent number 7,033,861
- Issue date Apr 25, 2006
- Staktek Group L.P.
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low profile chip scale stacking system and method
- Patent number 7,026,708
- Issue date Apr 11, 2006
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and chip scale stacking system and method
- Patent number 6,955,945
- Issue date Oct 18, 2005
- Staktek Group L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system and method
- Patent number 6,956,284
- Issue date Oct 18, 2005
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system and method
- Patent number 6,940,729
- Issue date Sep 6, 2005
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and chip scale stacking system and method
- Patent number 6,914,324
- Issue date Jul 5, 2005
- Staktek Group L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Wide data path stacking system and method
- Patent number 6,618,257
- Issue date Sep 9, 2003
- Staktek Group, L.P.
- James Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip scale stacking system and method
- Patent number 6,576,992
- Issue date Jun 10, 2003
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Server Rack System Latch Lockout
- Publication number 20240251513
- Publication date Jul 25, 2024
- Dell Products L.P.
- Richard W. Guzman
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed Memory Component
- Publication number 20090160042
- Publication date Jun 25, 2009
- Entorian Technologies, LP
- James Douglas Wehrly, JR.
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Low Profile Stacking System and Method
- Publication number 20090124045
- Publication date May 14, 2009
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
THIN CIRCUIT MODULE AND METHOD
- Publication number 20090073661
- Publication date Mar 19, 2009
- Staktek Group L.P.
- Mark Wolfe
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low profile chip scale stacking system and method
- Publication number 20080211077
- Publication date Sep 4, 2008
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Modularized Die Stacking System and Method
- Publication number 20080067662
- Publication date Mar 20, 2008
- Staktek Group. L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Leaded Package Integrated Circuit Stacking
- Publication number 20070257349
- Publication date Nov 8, 2007
- Staktek Group L.P.
- James Douglas Wehrly
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Split Core Circuit Module
- Publication number 20070258217
- Publication date Nov 8, 2007
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed memory component
- Publication number 20070164416
- Publication date Jul 19, 2007
- James Douglas Wehrly
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Managed memory component
- Publication number 20070159545
- Publication date Jul 12, 2007
- James Douglas Wehrly
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed memory component
- Publication number 20070158821
- Publication date Jul 12, 2007
- Leland Szewerenko
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Managed memory component
- Publication number 20070158800
- Publication date Jul 12, 2007
- James Douglas Wehrly
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low Profile Stacking System and Method
- Publication number 20070114649
- Publication date May 24, 2007
- Staktek Group L.P., a Texas Limited Partnership
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low Profile Stacking System and Method
- Publication number 20070117262
- Publication date May 24, 2007
- Staktek Group L.P., a Texas Limited Partnership
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Leaded package integrated circuit stacking
- Publication number 20070080470
- Publication date Apr 12, 2007
- Staktek Group. L.P.
- James Douglas Wehrly
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacked module systems and method
- Publication number 20060263938
- Publication date Nov 23, 2006
- Julian Partridge
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Modified core for circuit module system and method
- Publication number 20060198238
- Publication date Sep 7, 2006
- Staktek Group. L.P.
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacking system and method
- Publication number 20060131716
- Publication date Jun 22, 2006
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Circuit module component mounting system and method
- Publication number 20060118936
- Publication date Jun 8, 2006
- Staktek Group. L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacking system and method
- Publication number 20060091521
- Publication date May 4, 2006
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacked module systems and methods
- Publication number 20060092614
- Publication date May 4, 2006
- Staktek Group, L.P.
- Julian Partridge
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Integrated circuit stacking system and method
- Publication number 20060008945
- Publication date Jan 12, 2006
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacking system and method
- Publication number 20050280135
- Publication date Dec 22, 2005
- Staktek Group. L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Flex-based circuit module
- Publication number 20050263872
- Publication date Dec 1, 2005
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Pitch change and chip scale stacking system and method
- Publication number 20050146011
- Publication date Jul 7, 2005
- Staktek Group, L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low profile stacking system and method
- Publication number 20050146031
- Publication date Jul 7, 2005
- Staktek Group, L.P.
- Julian Partridge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and chip scale stacking system and method
- Publication number 20050067683
- Publication date Mar 31, 2005
- Staktek Group. L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and chip scale stacking system and method
- Publication number 20050062144
- Publication date Mar 24, 2005
- Staktek Group, L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and integrated circuit stacking system and method
- Publication number 20050057911
- Publication date Mar 17, 2005
- Staktek Group, L.P.
- Russell Rapport
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked module systems and methods
- Publication number 20050056921
- Publication date Mar 17, 2005
- Staktek Group. L.P.
- James Douglas Wehrly
- H01 - BASIC ELECTRIC ELEMENTS

David L. Roper

Person

Patents Grantslast 30 patents

Modified core for circuit module system and method

Stacked module systems

Low profile stacking system and method

Integrated circuit stacking system

Flex-based circuit module

Integrated circuit stacking system

Memory expansion and integrated circuit stacking system and method

Integrated circuit stacking system and method

Split core circuit module

Managed memory component

Stacking system and method

Modularized die stacking system and method

Integrated circuit stacking system and method

Stacked module systems and method

Managed memory component

Leaded package integrated circuit stacking

Memory expansion and chip scale stacking system and method

Pitch change and chip scale stacking system and method

Low profile stacking system and method

Low profile chip scale stacking system and method

Flexible circuit connector for stacked chip module

Pitch change and chip scale stacking system

Stacked module systems and method

Low profile chip scale stacking system and method

Memory expansion and chip scale stacking system and method

Integrated circuit stacking system and method

Integrated circuit stacking system and method

Memory expansion and chip scale stacking system and method

Wide data path stacking system and method

Chip scale stacking system and method

Patents Applicationslast 30 patents

Server Rack System Latch Lockout

Managed Memory Component

Low Profile Stacking System and Method

THIN CIRCUIT MODULE AND METHOD

Low profile chip scale stacking system and method

Modularized Die Stacking System and Method

Leaded Package Integrated Circuit Stacking

Split Core Circuit Module

Managed memory component

Managed memory component

Managed memory component

Managed memory component

Low Profile Stacking System and Method

Low Profile Stacking System and Method

Leaded package integrated circuit stacking

Stacked module systems and method

Modified core for circuit module system and method

Stacking system and method

Circuit module component mounting system and method

Stacking system and method

Stacked module systems and methods

Integrated circuit stacking system and method

Stacking system and method

Flex-based circuit module

Pitch change and chip scale stacking system and method

Low profile stacking system and method

Memory expansion and chip scale stacking system and method

Memory expansion and chip scale stacking system and method

Memory expansion and integrated circuit stacking system and method

Stacked module systems and methods