Jeffrey Alan Buchle

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit stacking system
- Patent number 7,606,048
- Issue date Oct 20, 2009
- Enthorian Technologies, LP
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system
- Patent number 7,586,758
- Issue date Sep 8, 2009
- Entorian Technologies, LP
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and integrated circuit stacking system and method
- Patent number 7,542,304
- Issue date Jun 2, 2009
- Entorian Technologies, LP
- Russell Rapport
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking system and method
- Patent number 7,495,334
- Issue date Feb 24, 2009
- Entorian Technologies, LP
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Modularized die stacking system and method
- Patent number 7,485,951
- Issue date Feb 3, 2009
- Entorian Technologies, LP
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system and method
- Patent number 7,335,975
- Issue date Feb 26, 2008
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and chip scale stacking system and method
- Patent number 7,256,484
- Issue date Aug 14, 2007
- Staktek Group L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Pitch change and chip scale stacking system and method
- Patent number 7,202,555
- Issue date Apr 10, 2007
- Staktek Group L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low profile chip scale stacking system and method
- Patent number 7,094,632
- Issue date Aug 22, 2006
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Pitch change and chip scale stacking system
- Patent number 7,053,478
- Issue date May 30, 2006
- Staktek Group L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low profile chip scale stacking system and method
- Patent number 7,026,708
- Issue date Apr 11, 2006
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and chip scale stacking system and method
- Patent number 6,955,945
- Issue date Oct 18, 2005
- Staktek Group L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit stacking system and method
- Patent number 6,940,729
- Issue date Sep 6, 2005
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory expansion and chip scale stacking system and method
- Patent number 6,914,324
- Issue date Jul 5, 2005
- Staktek Group L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Wide data path stacking system and method
- Patent number 6,618,257
- Issue date Sep 9, 2003
- Staktek Group, L.P.
- James Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip scale stacking system and method
- Patent number 6,576,992
- Issue date Jun 10, 2003
- Staktek Group L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Clock driver with instantaneously selectable phase and method for u...
- Patent number 6,282,210
- Issue date Aug 28, 2001
- Staktek Group L.P.
- Russell Rapport
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Low profile chip scale stacking system and method
- Publication number 20080211077
- Publication date Sep 4, 2008
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Modularized Die Stacking System and Method
- Publication number 20080067662
- Publication date Mar 20, 2008
- Staktek Group. L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacking system and method
- Publication number 20060131716
- Publication date Jun 22, 2006
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacking system and method
- Publication number 20060091521
- Publication date May 4, 2006
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacking system and method
- Publication number 20050280135
- Publication date Dec 22, 2005
- Staktek Group. L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Pitch change and chip scale stacking system and method
- Publication number 20050146011
- Publication date Jul 7, 2005
- Staktek Group, L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and chip scale stacking system and method
- Publication number 20050067683
- Publication date Mar 31, 2005
- Staktek Group. L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and chip scale stacking system and method
- Publication number 20050062144
- Publication date Mar 24, 2005
- Staktek Group, L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and integrated circuit stacking system and method
- Publication number 20050057911
- Publication date Mar 17, 2005
- Staktek Group, L.P.
- Russell Rapport
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit stacking system and method
- Publication number 20050041402
- Publication date Feb 24, 2005
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated circuit stacking system and method
- Publication number 20050041403
- Publication date Feb 24, 2005
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated circuit stacking system and method
- Publication number 20050041404
- Publication date Feb 24, 2005
- Staktek Group. L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Pitch change and chip scale stacking system
- Publication number 20050018412
- Publication date Jan 27, 2005
- Staktek Group, L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Point to point memory expansion system and method
- Publication number 20040245615
- Publication date Dec 9, 2004
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low profile chip scale stacking system and method
- Publication number 20040229402
- Publication date Nov 18, 2004
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MEMORY EXPANSION AND CHIP SCALE STACKING SYSTEM AND METHOD
- Publication number 20040197956
- Publication date Oct 7, 2004
- Staktek Group L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and chip scale stacking system and method
- Publication number 20040178496
- Publication date Sep 16, 2004
- Staktek Grop, L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low profile chip scale stacking system and method
- Publication number 20040052060
- Publication date Mar 18, 2004
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Modularized die stacking system and method
- Publication number 20040000707
- Publication date Jan 1, 2004
- Staktek Group, L.P.
- David L. Roper
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory expansion and chip scale stacking system and method
- Publication number 20040000708
- Publication date Jan 1, 2004
- Staktek Group, L.P.
- Russell Rapport
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacking system and method
- Publication number 20030137048
- Publication date Jul 24, 2003
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated circuit stacking system and method
- Publication number 20030081392
- Publication date May 1, 2003
- Staktek Group, L.P.
- James W. Cady
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Jeffrey Alan Buchle

Person

Patents Grantslast 30 patents

Integrated circuit stacking system

Integrated circuit stacking system

Memory expansion and integrated circuit stacking system and method

Stacking system and method

Modularized die stacking system and method

Integrated circuit stacking system and method

Memory expansion and chip scale stacking system and method

Pitch change and chip scale stacking system and method

Low profile chip scale stacking system and method

Pitch change and chip scale stacking system

Low profile chip scale stacking system and method

Memory expansion and chip scale stacking system and method

Integrated circuit stacking system and method

Memory expansion and chip scale stacking system and method

Wide data path stacking system and method

Chip scale stacking system and method

Clock driver with instantaneously selectable phase and method for u...

Patents Applicationslast 30 patents

Low profile chip scale stacking system and method

Modularized Die Stacking System and Method

Stacking system and method

Stacking system and method

Stacking system and method

Pitch change and chip scale stacking system and method

Memory expansion and chip scale stacking system and method

Memory expansion and chip scale stacking system and method

Memory expansion and integrated circuit stacking system and method

Integrated circuit stacking system and method

Integrated circuit stacking system and method

Integrated circuit stacking system and method

Pitch change and chip scale stacking system

Point to point memory expansion system and method

Low profile chip scale stacking system and method

MEMORY EXPANSION AND CHIP SCALE STACKING SYSTEM AND METHOD

Memory expansion and chip scale stacking system and method

Low profile chip scale stacking system and method

Modularized die stacking system and method

Memory expansion and chip scale stacking system and method

Stacking system and method

Integrated circuit stacking system and method