Scott E. Thompson

Person

Gainesville, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electronic devices and systems, and methods for making and using th...
- Patent number 11,887,895
- Issue date Jan 30, 2024
- United Semiconductor Japan Co., Ltd.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic devices and systems, and methods for making and using th...
- Patent number 11,062,950
- Issue date Jul 13, 2021
- United Semiconductor Japan Co., Ltd.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced transistors with punch through suppression
- Patent number 10,325,986
- Issue date Jun 18, 2019
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 10,250,257
- Issue date Apr 2, 2019
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electronic devices and systems, and methods for making and using th...
- Patent number 10,224,244
- Issue date Mar 5, 2019
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic devices and systems, and methods for making and using th...
- Patent number 10,217,668
- Issue date Feb 26, 2019
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic devices and systems, and methods for making and using same
- Patent number 10,074,568
- Issue date Sep 11, 2018
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried channel deeply depleted channel transistor
- Patent number 9,991,300
- Issue date Jun 5, 2018
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,985,631
- Issue date May 29, 2018
- MIE FUJITSU SEMICONDUCTOR LIMITED
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,966,130
- Issue date May 8, 2018
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Transistor with threshold voltage set notch and method of fabricati...
- Patent number 9,922,977
- Issue date Mar 20, 2018
- Mie Fujitsu Semiconductor Limited
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power semiconductor transistor structure and method of fabricat...
- Patent number 9,865,596
- Issue date Jan 9, 2018
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,838,012
- Issue date Dec 5, 2017
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Buried channel deeply depleted channel transistor
- Patent number 9,786,703
- Issue date Oct 10, 2017
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,741,428
- Issue date Aug 22, 2017
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,680,470
- Issue date Jun 13, 2017
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Advanced transistors with punch through suppression
- Patent number 9,508,800
- Issue date Nov 29, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS gate stack structures and processes
- Patent number 9,508,728
- Issue date Nov 29, 2016
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power semiconductor transistor structure and method of fabricat...
- Patent number 9,496,261
- Issue date Nov 15, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried channel deeply depleted channel transistor
- Patent number 9,478,571
- Issue date Oct 25, 2016
- Mie Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with threshold voltage set notch and method of fabricati...
- Patent number 9,418,987
- Issue date Aug 16, 2016
- Mie Fujitsu Semiconductor Limited
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating multiple transistor devices on a substrate w...
- Patent number 9,406,567
- Issue date Aug 2, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structures and processes based on selective thinning
- Patent number 9,391,076
- Issue date Jul 12, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor with reduced junction leakage c...
- Patent number 9,368,624
- Issue date Jun 14, 2016
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit devices and methods
- Patent number 9,362,291
- Issue date Jun 7, 2016
- Mie Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS gate stack structures and processes
- Patent number 9,281,248
- Issue date Mar 8, 2016
- Mie Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced transistors with punch through suppression
- Patent number 9,263,523
- Issue date Feb 16, 2016
- Mie Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Analog circuits having improved transistors, and methods therefor
- Patent number 9,231,541
- Issue date Jan 5, 2016
- Mie Fujitsu Semiconductor Limited
- Lawerence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High uniformity screen and epitaxial layers for CMOS devices
- Patent number 9,196,727
- Issue date Nov 24, 2015
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital circuits having improved transistors, and methods therefor
- Patent number 9,184,750
- Issue date Nov 10, 2015
- Mie Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING TH...
- Publication number 20210313231
- Publication date Oct 7, 2021
- United Semiconductor Japan Co., Ltd.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING TH...
- Publication number 20190080967
- Publication date Mar 14, 2019
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20180248548
- Publication date Aug 30, 2018
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20180048311
- Publication date Feb 15, 2018
- Scott E. Thompson
- G11 - INFORMATION STORAGE
Information Patent Application
Buried Channel Deeply Depleted Channel Transistor
- Publication number 20170323916
- Publication date Nov 9, 2017
- MIE Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Devices and Methods
- Publication number 20170301395
- Publication date Oct 19, 2017
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20170214404
- Publication date Jul 27, 2017
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- G11 - INFORMATION STORAGE
Information Patent Application
Electronic Devices and Systems, and Methods for Making and Using th...
- Publication number 20170117366
- Publication date Apr 27, 2017
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Advanced Transistors with Punch Through Suppression
- Publication number 20170040419
- Publication date Feb 9, 2017
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Channel Deeply Depleted Channel Transistor
- Publication number 20170025457
- Publication date Jan 26, 2017
- MIE Fujitsu Semiconductor Limited
- Teymur Bakhishev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Power Semiconductor Transistor Structure and Method of Fabricat...
- Publication number 20170012044
- Publication date Jan 12, 2017
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electronic Devices and Systems, and Methods for Making and Using th...
- Publication number 20160358918
- Publication date Dec 8, 2016
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistor with Threshold Voltage Set Notch and Method of Fabricati...
- Publication number 20160336318
- Publication date Nov 17, 2016
- MIE Fujitsu Semiconductor Limited
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Structures and Processes Based on Selective Thinning
- Publication number 20160307907
- Publication date Oct 20, 2016
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Devices and Methods
- Publication number 20160232964
- Publication date Aug 11, 2016
- MIE Fujitsu Semiconductor Limited
- Lawrence T. Clark
- G11 - INFORMATION STORAGE
Information Patent Application
Epitaxial Channel Transistors and Die With Diffusion Doped Channels
- Publication number 20160211346
- Publication date Jul 21, 2016
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Advanced Transistors with Punch Through Suppression
- Publication number 20160181370
- Publication date Jun 23, 2016
- MIE Fujitsu Semiconductor Limited
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Gate Stack Structures and Processes
- Publication number 20160141292
- Publication date May 19, 2016
- MIE Fujitsu Semiconductor Limited
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Digital Circuits Having Improved Transistors, and Methods Therefor
- Publication number 20160020768
- Publication date Jan 21, 2016
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- G11 - INFORMATION STORAGE
Information Patent Application
High Uniformity Screen and Epitaxial Layers for CMOS Devices
- Publication number 20150333144
- Publication date Nov 19, 2015
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING SAME
- Publication number 20150255350
- Publication date Sep 10, 2015
- MIE Fujitsu Semiconductor Limited
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES
- Publication number 20150061012
- Publication date Mar 5, 2015
- SUVOLTA, INC.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR
- Publication number 20150015334
- Publication date Jan 15, 2015
- SUVOLTA, INC.
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATI...
- Publication number 20140284722
- Publication date Sep 25, 2014
- Reza Arghavani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANALOG TRANSISTOR
- Publication number 20140248753
- Publication date Sep 4, 2014
- SUVOLTA, INC.
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION
- Publication number 20140167156
- Publication date Jun 19, 2014
- SuVolta, lnc.
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...
- Publication number 20140084385
- Publication date Mar 27, 2014
- SUVOLTA, INC.
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING TH...
- Publication number 20140077312
- Publication date Mar 20, 2014
- SUVOLTA, INC.
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICAT...
- Publication number 20130328129
- Publication date Dec 12, 2013
- SUVOLTA, INC.
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION
- Publication number 20130181298
- Publication date Jul 18, 2013
- Lucian Shifren
- H01 - BASIC ELECTRIC ELEMENTS

Scott E. Thompson

Person

Patents Grantslast 30 patents

Electronic devices and systems, and methods for making and using th...

Electronic devices and systems, and methods for making and using th...

Advanced transistors with punch through suppression

Digital circuits having improved transistors, and methods therefor

Electronic devices and systems, and methods for making and using th...

Electronic devices and systems, and methods for making and using th...

Electronic devices and systems, and methods for making and using same

Buried channel deeply depleted channel transistor

Digital circuits having improved transistors, and methods therefor

Integrated circuit devices and methods

Transistor with threshold voltage set notch and method of fabricati...

Low power semiconductor transistor structure and method of fabricat...

Digital circuits having improved transistors, and methods therefor

Buried channel deeply depleted channel transistor

Integrated circuit devices and methods

Digital circuits having improved transistors, and methods therefor

Advanced transistors with punch through suppression

CMOS gate stack structures and processes

Low power semiconductor transistor structure and method of fabricat...

Buried channel deeply depleted channel transistor

Transistor with threshold voltage set notch and method of fabricati...

Method for fabricating multiple transistor devices on a substrate w...

CMOS structures and processes based on selective thinning

Method for fabricating a transistor with reduced junction leakage c...

Integrated circuit devices and methods

CMOS gate stack structures and processes

Advanced transistors with punch through suppression

Analog circuits having improved transistors, and methods therefor

High uniformity screen and epitaxial layers for CMOS devices

Digital circuits having improved transistors, and methods therefor

Patents Applicationslast 30 patents

ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING TH...

ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING TH...

Digital Circuits Having Improved Transistors, and Methods Therefor

Digital Circuits Having Improved Transistors, and Methods Therefor

Buried Channel Deeply Depleted Channel Transistor

Integrated Circuit Devices and Methods

Digital Circuits Having Improved Transistors, and Methods Therefor

Electronic Devices and Systems, and Methods for Making and Using th...

Advanced Transistors with Punch Through Suppression

Buried Channel Deeply Depleted Channel Transistor

Low Power Semiconductor Transistor Structure and Method of Fabricat...

Electronic Devices and Systems, and Methods for Making and Using th...

Transistor with Threshold Voltage Set Notch and Method of Fabricati...

CMOS Structures and Processes Based on Selective Thinning

Integrated Circuit Devices and Methods

Epitaxial Channel Transistors and Die With Diffusion Doped Channels

Advanced Transistors with Punch Through Suppression

CMOS Gate Stack Structures and Processes

Digital Circuits Having Improved Transistors, and Methods Therefor

High Uniformity Screen and Epitaxial Layers for CMOS Devices

ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING SAME

HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES

ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATI...

ANALOG TRANSISTOR

ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION

DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHOD...

ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING TH...

LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICAT...

ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION