Sugibayashi et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure”, IEEE Journal of Solid-State Circuits, vol. 28 (No. 11), (Nov. 1993). |
Taguchi et al., “A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture”, IEEE Journal of Solid-State Circuits, vol. 26 (No. 11), (Nov. 1991). |
Kitsukawa et al., “256-Mb DRAM Circuit Technologies for File Applications”, IEEE Journal of Solid-State Circuits, vol. 28 (No. 11), (Nov. 1993). |
Jedec Solid State Products Engineering Council, “Committee Letter Ballot”, JC-42.3-95-73, Item #633.13, Arlington, VA (Apr. 1995). |
Yoo et al., “SP 23.6: A 32-Bank 1 Gb DRAM with 1 GB/s Bandwidth”, ISSCC96/Session 23/DRAM/Paper SP 23.6. |
Nitta et al., “SP 23.5: A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture”, ISSCC96/Session 23/DRAM Paper SP 23.5 |
U.S. patent application Ser. No. 08/521,563, entitled Improved Voltage Regulator Circuit, filed Aug. 30, 1995. |
U.S. patent application Ser. No. 08/668,347, entitled Differential Voltage Regulator, filed Jun. 26, 1996. |
U.S. patent application Ser. No. 08/460,234, entitled Single Deposition Layer Metal Dynamic Random Access Memory, filed Aug. 17, 1995. |
U.S. patent application Ser. No. 08/420,943, entitled Dynamic Random-Access Memory, filed Jun. 4, 1995. |
U.S. patent application Ser. No. 08/194,184, entitled Integrated Circuit Power Supply Having Piecewise Linearity, filed Feb. 8, 1994. |
U.S. patent application Ser. No. 08/137,679, entitled A Voltage Reference Circuit with Common Gate Loading for a Current Mirror Output Stage, filed Oct. 14, 1993. |
U.S. patent application Ser. No. 08/325,766, entitled An Efficient Method for Obtaining Usable Parts From a Partially Good Memory Integrated Circuit, filed Oct. 19, 1994. |