Sugibay Ashi et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure,” IEEE Journal of Solid-State Circuits, vol. 28 (No. 11), (Nov., 1993). |
Taguchi et al., “A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture,” IEEE Journal of Solid-State Circuits, vol. 26 (No. 11), (Nov., 1991). |
Kitsukawa et al., “256-Mb DRAM Circuit Technologies for File Applications,” IEEE Journal of Solid-State Circuits, vol. 28 (No. 11), (Nov., 1993). |
Jedec Solid State Products Engineering Council, “Committee Letter Ballot,” JC-42.3-95-73, Item #633.13, Arlington, VA (Apr., 1995). |
Yoo et al., “SP 23.6: A 32-Bank 1 Gb DRAM with 1BG/s Bandwidth,” ISSCC96/Session 23/DRAM/PAPER SP 23.6. |
Nitta et al., “SP 23.5: A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture,” ISSCC96/Session 23/DRAM/PAPER SP 23.5. |
U.S. patent application Ser. No. 08/420,943, entitled Dynamic Random-Access Memory, Filed Jun. 4, 1995. |
U.S. patent application Ser. No. 08/194,184, entitled Integrated Circuit Power Supply Having Piecewise Linearity, Filed Feb. 8, 1994. |
U.S. patent application Ser. No. 08/137,679, entitled A Voltage Reference Circuit With Common Gate Loading for a Current Mirror Output Stage, Filed Oct. 14, 1993. |
U.S. patent application Ser. No. 08/511,344, entitled A Two Stage Voltage Level Translator, Filed Aug. 4, 1995. |
U.S. patent application Ser. No. 08/456,534, entitled Method and Apparatus for Initiating and Controlling Test Modes Within an Integrated Circuit, Filed Jun. 1, 1995. |
U.S. patent application Ser. No. 08/325,766, entitled An Efficient Method for Obtaining Usable Parts froma Partically Good Memory Intergrated Circuit Integrated Circuit, Filed Oct. 19, 1994. |