Patent Application
20080156518
The present invention relates to the cutting of individual chip carriers from a tape or substrate that is configured to hold a plurality of microelectronic devices.
In conventional methods for cutting out individual chip carriers from a tape or substrate having multiple chip carriers that have been manufactured commonly in a previous step, a substrate for holding multiple chips can be put into a punch index frame. The punch index frame is typically a rectangular frame with a rectangular opening in the middle configured to hold the substrate in the frame at a fixed position. The punch index frame can be positioned in X- and Y-directions parallel to the plane of the substrate by linear motion relative to a cutting tool. For positioning of the substrate in relation to the punch index frame, to guarantee that the substrate is cut at the right position, alignment holes are arranged on the punch index frame and on the substrate itself that match each other.
When cutting the substrate into individual chip carriers, it is desirable that the edges of the individual chip carriers are precisely defined relative to the connection terminals, for example package pins that are arranged on surfaces of the individual chip carriers.
However, the above alignment of the substrate relative to the frame has the disadvantage that the position of holes on the substrate can be imprecise or misaligned relative to the position of the package pins. Among other reasons, this misalignment is due to the formation of the holes by a separate process than the formation of the pins. This can lead to inaccuracy in the offset between the package pins and the outer periphery of the chip carriers.
Thus, there are substantial needs for improved methods with increased precision for cutting substrates or tapes into a plurality of chip carriers.
One aspect of the present invention includes a method of cutting a substrate. The substrate has an upper and lower surface and the method cuts the substrate into individual microelectronic device carriers. Preferably, the method includes the steps of: inserting the substrate including a plurality of device carriers into a carrier frame by mechanically engaging at least one metallic alignment element with the carrier frame, and aligning a cutting device for cutting the substrate into individual device carriers with the carrier frame. The method also includes a step of cutting the substrate into the individual device carriers using the cutting device.
A second aspect of the present invention includes an in-process element for holding microelectronic devices. Preferably, the in-process element includes a substrate having an upper and lower surface and having a first area adapted to receive a plurality of microelectronic devices and a second area adapted for engagement with a carrier frame. The substrate includes metallic electrically conductive features in the first area of the substrate area configured for connection to microelectronic devices; and metallic alignment elements in the second area of the substrate, the metallic alignment elements being configured to mechanically engage into a carrier frame. Preferably, the metallic alignment elements are made from the same metal layer as the metallic conductive features, and are in predetermined positional relationship with the metallic conductive features.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings were:
It should be noted that the dimensions of the assemblies shown in the Figures may be distorted for clarity of the illustration, different proportions of the different dimensions are also possible, and like numbers represent similar elements.
Frame 110 has an opening 125 with length D5 (
Frame 110 has recessed interior edges 110 forming support recesses 117a, 117b (
In addition, frame 110 has first locating features in the form of holes 120 open to the engagement surfaces 130a and 130b. The axes of holes 120 are in the Z direction. In the variant shown, holes 120 are located substantially in the middle of engagement surfaces 130a, 130b. Six engagement holes 120 are depicted, but any number of engagement holes can be used. However, it is desirable that there are at least two holes arranged in opposite engagement surfaces 130a, and 130b, or 131a, and 131b of the carrier 110. Preferably, the holes 120 are located close to the corners of the outline 180 of the substrate 160. Frame 110 also has second location features 127, which in this embodiment are holes. The second location features 127 have a predetermined positional relationship with the first location features 120. Frame 110 further includes sprocket holes 115 that can be used for the movement and alignment of the carrier frame 110 towards a cutting device 210a, 210b (
Substrate 160 includes a wiring panel made of at least one dielectric layer and conductive traces and terminals. As best seen in
Substrate 160 includes a first area that will be used as chip carriers 170a, 170b, and a second area including outer boundary areas 165. The outer boundary areas 165 will partially or entirely overlie the frame surfaces 130a, 130b when the substrate 160 is engaged in the frame 110. The bottom surface 162 of the substrate 160 includes outer abutting surfaces 161 in outer boundary areas 165. Cutting lines 195 are depicted at the boundaries of the individual chip carriers 170a and 170b. The chip carriers 170a, 170b will form carriers for individual microelectronic devices 150a, 150b once cut out of the common substrate 160. The cutting lines 195 indicate the desired outer boundaries of the chip carriers 170a, 170b, and thus indicate the desired cutting location in a later step. The plurality of cutting lines 195 are shown in
Substrate 160 further includes metallic alignment elements in the form of alignment posts 140. Posts 140 are desirably formed from the same metal layer or composite metal layer as metallic electrically conductive features such as terminal pins 190a, 190b of the chip carriers 170a, 170b. Therefore, the alignment features will be in a predetermined and precise positional relationship with respect to the metallic electrically conductive features. For example, in such a manufacturing step, an unitary metal structure including one or more metal layers is etched, and the metal other than the remaining metallic features such as engagement posts 140, terminal pins 190a, 190b, and traces 158a (
In one stage of a method according to an embodiment of the invention, substrate 160 is assembled with frame 110 as shown in
The outer surface edge 164 of the substrate 160 is arranged close to the vertical wall 119 of the recesses 117a, 117b with a gap therebetween. The gap between the walls 119 and 164 should be bigger than the gap between the walls 122, 142 of the metallic alignment elements 140, 120. Stated another way, despite any tolerance of the placement of the wall 119 relative to pins 190a, 190b, wall 119 does not engage edge 164 of the substrate. In this variant, the Z-axis location of the upper surface 135 of the frame 110 is higher than the upper surface of the substrate 167. For facilitating the insertion of the substrate 160 into the openings 125 and recessed openings 117a, 117b, the inner edges 137 of the frame 110 are tapered. After engagement of the posts 140 into the holes 120, the substrate 160 optionally may be temporarily attached to the frame 110 by means of an adhesive tape 220. This temporary attachment can be done so as to avoid displacement of the substrate 160 out of the frame 110 during subsequent operations.
Before or after assembling substrate 160 with frame 110, microelectronic device 150 is mounted on the chip carriers 170 of substrate 160 and connected to bond pads 156a. The microelectronic devices 150a, 150b are preferably attached by means of soldering material 152a, 152b to bond pads 156a (
In another stage of the method, frame 110 is inserted into a holder 242 of a cutting machine, and fastened by an upper clamp 240 to the holder. The holder 242 is in predetermined spatial relationship to the operative elements of the cutting machine. Alignment features such as pins(not shown) of holder 242 will engage with second location features 127 (
After engaging the frame 110 with holder 242, the cutting process for singulation of the chip carriers 170a, 170b is initiated. The particular cutting machine depicted in
As noted above, the substrate's alignment with respect to the carrier 110 is made with the metallic alignment features or posts 140 that were formed in close precision to pins 190a, and 190b. In addition, the carrier 110 is precisely positioned with respect to holder 242 that engages with second location features 127. Accordingly, the operative elements of the cutting machine, in this case cutting blades 210a, 210b, will be in precise relationship with the location of the pins 190a, 190b. The cutting machine will cut the substrate along cutting planes 195 which lie in precise positional relationship to the electrically conductive features or terminal pins 190a. After the cutting operation, each individual chip carrier will have edges lying in precise positional relationship with the conductive features or terminal pins 190a on that chip carrier. In use, the individual chip carriers 170 typically are mounted to a larger circuit panel as, for example, by solder-bonding the terminal pins 190a to corresponding pads on the circuit board. Because the edges of the chip carrier are in precise positional relationship to the terminal pins, the edges of the chip carrier will be precisely positioned relative to the pads of the circuit board. This precision avoids possible interference between edges of adjacent chip carriers which are placed close to one another on the circuit board. Stated another way, this precision allows the circuit board designer to place the pads for receiving one chip carrier closer to the pads for receiving an adjacent chip carrier, and allows closer packing of chip carriers on a circuit board. There is no need for additional optical alignment of the substrate 160 relative to the cutting machine.
The punch and die cutting apparatus depicted in
As discussed above, the microelectronic devices 150 may be mounted on the substrate before or after substrate 160 is mounted on frame 110. If the substrate is mounted on frame 110 before the microelectronic devices are mounted, the frame can used to hold the substrate in precise registration with the equipment used to mount the substrate, in the same way as the frame registers the substrate with the cutting equipment. In some cases, additional operations can be performed after the devices are mounted on the substrate but before cutting. For example, an encapsulant or underfill may be deposited around each device, and each device may be marked with identifying indicia. Here again, if the substrate is mounted on the frame before these operations, the frame can be used to register the devices and substrate relative to the tools used in these operations. The configuration of the second engagement features which register the frame 110 with the holder 242 can be varied. For example, sprocket holes 150 (
A frame 310 used in a further embodiment of the invention is a substantially flat sheet of metal with an opening 325 to accommodate the conductive features of the substrate. In this embodiment, the engagement surface 330a of the frame is simply a portion of the top surface 335 of the frame. Stated another way, the frame omits the recess 117a, 117b, 118a, 118b (
It is not necessary that the chip carriers 370 have pins that project from the lower surface of the substrate. For example, the metallic electrically conductive features can also be flat or block shaped terminals, as long as the alignment features of the substrate, such as engagement posts 340, and metallic electrically conductive features of the chip carriers have a precisely defined positional relationship to each other.
In another variant, one of the posts 340 can be formed longer than all other posts of the substrate. The longer post preferably can be formed close to a corner of the substrate 360. The longer post may have a larger diameter than the remaining posts. The longer post may be inserted into the corresponding hole of the frame in a first step. In a subsequent step, the substrate 360 can be rotated in clockwise or counterclockwise around the Z-axis of the long post, to insert all the remaining posts 340 into their corresponding holes.
In
An additional feature of the alignment means of
Alternatively, the plates 342 can be metal strips that substantially cover the surface 330a in the X-direction. The metallic plate 346 defines the Z-axis location of the substrate when put into the frame 310 with an increased precision, since dielectric layers of the substrate usually have less precision tolerances of surfaces compared to metallic features of the substrate. In another alternative, the metallic plate 346 extends beyond the cutting lines 395 into the area of the chip carrier 370a. The metallic plate may be connected with a ground or power supply terminal of each chip carrier. Such mechanical connection with metal elements could be desirable to further increase alignment precision of the substrate 360. In the cutting step, the plate would be severed to form an individual ground or power supply plane on each chip carrier 370a.
In the variant of
In the variant of
The alignment features of the present invention are not limited to posts that engage into corresponding holes.
The ridges 592 (
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
A substrate such as a flexible circuit panel which includes a plurality of chip carriers is aligned with a carrier frame by engaging metallic alignment elements carried on the substrate, such as metal posts, with features of the carrier frame. The carrier frame is aligned with a cutting device, for example by engaging features of the carrier frame with the cutting device. The metallic alignment elements and terminals on the chip carriers may be formed in the same process step, so that the terminals are in a precise positional relationship to the alignment features. The cutting device cuts the substrate to yield individual chip carriers having edges in precise positional relationship to the terminals.
As these and other variations and combinations of the features discussed herein can be utilized without departing from the present invention, the foregoing description of the preferred embodiments should be taken by way of illustration rather than by way of limitation of the invention as defined by the claims.
