Patent Application
20150371938
The following description relates to integrated circuits (“ICs”). More particularly, the following description relates to a Back-End-Of-Line stack for a stacked device.
Microelectronic assemblies generally include one or more ICs, such as for example one or more packaged dies (“chips”) or one or more dies. One or more of such ICs may be mounted on a circuit platform, such as a wafer such as in wafer-level-packaging (“WLP”), printed board (“PB”), a printed wiring board (“PWB”), a printed circuit board (“PCB”), a printed wiring assembly (“PWA”), a printed circuit assembly (“PCA”), a package substrate, an interposer, or a chip carrier. Additionally, one IC may be mounted on another IC. An interposer may be an IC, and an interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device. Furthermore, an interposer may be formed like a PWB, namely without any circuit elements such as capacitors, resistors, or active devices. Additionally, an interposer includes at least one through-substrate-via.
An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs. An IC may be coupled to a circuit platform by bonding, such as bonding traces or terminals, for example, of such circuit platform to bond pads or exposed ends of pins or posts or the like of an IC. Additionally, a redistribution layer (“RDL”) may be part of an IC to facilitate a flip-chip configuration, die stacking, or more convenient or accessible position of bond pads for example.
Interconnecting of an IC to another IC or to a circuit platform using an interposer has issues with respect to cost. Accordingly, it would be desirable and useful to provide a low cost alternative to use of an interposer.
An apparatus relates generally to a back-end-of-line (“BEOL”) stack. In such an apparatus, the BEOL stack is configured to electrically couple at least one first electrical component to at least one second electrical component. First contacts are provided on a first side of the BEOL stack with a first pitch for providing a bondable surface for connection to the at least one first electrical component. Second contacts are provided on a second side of the BEOL stack with a second pitch larger than the first pitch, the second contacts providing another bondable surface for connection to the at least one second electrical component.
An apparatus relates generally to another BEOL stack. In such an apparatus, the BEOL stack is configured to electrically couple at least one first electrical component to at least one second electrical component. First contacts are provided on a first side of the BEOL stack with a first pitch for providing a bondable surface for connection to the at least one first electrical component. Second contacts are provided on a second side of the BEOL stack with a second pitch for providing another bondable surface for connection to the at least one second electrical component. Both the first pitch and the second pitch are fine pitches for interconnection with the at least one first electrical component and the at least one second electrical component, respectively.
A method relates generally to formation of a BEOL stack. In such a method, the BEOL stack is formed using a temporary support structure. The forming includes depositing dielectric layers and conductive layers with back-end-of-line dielectric and metal depositions. The conductive layers of the BEOL stack extend horizontally and vertically through the dielectric layers of the BEOL stack formed to provide electrically conductive paths. The BEOL stack includes first contacts of the conductive layers provided on a first side of the BEOL stack with a first pitch. The BEOL stack further includes second contacts of the conductive layers provided on a second side of the BEOL stack with a second pitch. The temporary support structure is removed after formation of the BEOL stack.
Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of exemplary apparatus(es) or method(s). However, the accompanying drawings should not be taken to limit the scope of the claims, but are for explanation and understanding only.
In the following description, numerous specific details are set forth to provide a more thorough description of the specific examples described herein. It should be apparent, however, to one skilled in the art, that one or more other examples or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative examples the items may be different.
Substrate 12 includes an upper surface 14 and a lower surface 16 that extend in lateral directions and are generally parallel to each other at a thickness of substrate 12. Use of terms such as “upper” and “lower” or other directional terms is made with respect to the reference frame of the figures and is not meant to be limiting with respect to potential alternative orientations, such as in further assemblies or as used in various systems.
Upper surface 14 may generally be associated with what is referred to as a “front side” 4 of an in-process wafer, and lower surface 16 may generally be associated with what is referred to as a “backside” 6 of an in-process wafer. Along those lines, a front-side 4 of an in-process wafer may be used for forming what is referred to as front-end-of-line (“FEOL”) structures 3 and back-end-of-line (“BEOL”) structures 5. Generally, FEOL structures 3 may include shallow trench isolations (“STI”) 7, transistor gates 8, transistor source/drain regions (not shown), transistor gate dielectrics (not shown), contact etch stop layer (“CESL”; not shown), a pre-metallization dielectric or pre-metal dielectric (“PMD”) 11, and contact plugs 9, among other FEOL structures. A PMD 11 may be composed of one or more layers. Generally, BEOL structures 5 may include one or more inter-level dielectrics (“ILDs”) and one or more levels of metallization (“M”). In this example, there are four ILDs, namely ILD1, ILD2, ILD3, and ILD4; however, in other configurations there may be fewer or more ILDs. Furthermore, each ILD may be composed of one or more dielectric layers. In this example, there are five levels of metallization, namely M1, M2, M3, M4, and M5; however, in other configurations there may be fewer or more levels of metallization. Additionally, metal from a metallization level may extend through one or more ILDs, as is known. Furthermore, each level of metallization may be composed of one or more metal layers. A passivation level 13 may be formed on a last metallization layer. Such passivation level 13 may include one or more dielectric layers, and further may include an anti-reflective coating (“ARC”). Furthermore, a redistribution layer (“RDL”) may be formed on such passivation level. Conventionally, an RDL may include: a dielectric layer, such as a polyimide layer for example; another metal layer on such dielectric layer and connected to a bond pad of a metal layer of a last metallization level; and another dielectric layer, such as another polyimide layer for example, over such RDL metal layer while leaving a portion thereof exposed to provide another bond pad. A terminal opening may expose such other bond pad of such RDL metal layer. Thereafter, a solder bump or wire bond may be conventionally coupled to such bond pad.
As part of a FEOL or BEOL structure formation, a plurality of via structures 18 may extend within openings formed in substrate 12 which extend into substrate 12. Via structures 18 may be generally in the form of any solid of any shape formed by filling an opening formed in substrate 12. Examples of such solid shapes generally include cylindrical, conical, frustoconical, rectangular prismatic, cubic, or the like.
Conventionally, via structures 18 may extend from upper surface 14 down toward lower surface 16, and after a backside reveal, via structures 18 may extend between surfaces 14 and 16, as effectively thickness of substrate 12 may be thinned so as to reveal lower end surfaces of via structures 18, as described below in additional detail. Via structures 18 extending through substrate 12 between surfaces 14 and 16, though they may extend above or below such surfaces, respectively, may be referred to as through-substrate-vias. As substrates are often formed of silicon, such through-substrate-vias are commonly referred to as TSVs, which stands for through-silicon-vias.
Such openings formed in substrate 12 may be conformally coated, oxidized, or otherwise lined with a liner or insulator 15. Conventionally, liner 15 is silicon dioxide; however, a silicon oxide, a silicon nitride, or another dielectric material may be used to electrically isolate via structures 18 from substrate 12. Generally, liner 15 is an insulating or dielectric material positioned between any and all conductive portions of a via structure 18 and substrate 12 such that an electronic signal, a ground, a supply voltage, or the like carried by such via structure 18 is not substantially leaked into substrate 12, which may cause signal loss or attenuation, shorting, or other circuit failure.
Overlying a liner 15 may be a barrier layer 24. Generally, barrier layer 24 is to provide a diffusion barrier with respect to a metallic material used to generally fill a remainder of an opening in which a via structure 18 is formed. Barrier layer 24 may be composed of one or more layers. Furthermore, a barrier layer 24 may provide a seed layer for subsequent electroplating or other deposition, and thus barrier layer 24 may be referred to as a barrier/seed layer. Moreover, barrier layer 24 may provide an adhesion layer for adherence of a subsequently deposited metal. Thus, barrier layer 24 may be a barrier/adhesion layer, a barrier/seed layer, or a barrier/adhesion/seed layer. Examples of materials that may be used for barrier layer 24 include tantalum (Ta), tantalum nitride (TaN), palladium (Pd), titanium nitride (TiN), TaSiN, compounds of Ta, compounds of Ti, compounds of nickel (Ni), compounds of copper (Cu,), compounds of cobalt (Co), or compounds of tungsten (W), among others.
Via structures 18 may generally consist of a metallic or other conductive material generally filling a remaining void in an opening formed in substrate 12 to provide a via conductor 21. In various examples, a via conductor 21 of a via structure 18 may generally consist of copper or a copper alloy. However, a via conductor 21 may additionally or alternatively include one or more other conductive materials such as tantalum, nickel, titanium, molybdenum, tungsten, aluminum, gold, or silver, including various alloys or compounds of one or more of the these materials, and the like. A via conductor 21 may include non-metallic additives to control various environmental or operational parameters of a via structure 18.
Via structures 18 may each include an upper end contact surface 20 which may be level with upper surface 14 of substrate 12 and a lower end contact surface 22 which may be level with lower surface 16 of substrate 12 after a backside reveal. End surfaces 20 and 22 may be used to interconnect via structures 18 with other internal or external components, as below described in additional detail.
In this example, upper end contact surface 20 of via conductors 21 are interconnected to M1 through a respective contact pad 23. Contact pads 23 may be formed in respective openings formed in PMD 11 in which M1 extends. However, in other configurations, one or more via conductors 21 may extend to one or more other higher levels of metallization through one or more ILDs. Furthermore, via structure 18 is what may be referred to as a front side TSV, as an opening used to form via structure is initially formed by etching from a front side of substrate 12.
However, a via structure may be a backside TSV, as generally indicated in
IC 10 of
For purposes of clarity by way of example and not limitation, it shall be assumed that front side TSVs are used, as the following description is generally equally applicable to backside TSVs.
More recently, TSVs have been used to provide what is referred to as three-dimensional (“3D”) ICs or “3D ICs.” Generally, attaching one die to another using, in part, TSVs may be performed at a bond pad level or an on-chip electrical wiring level. ICs 10 may be diced from a wafer into single dies. Such single dies may be bonded to one another or bonded to a circuit platform, as previously described. For purposes of clarity by way of example and not limitation, it shall be assumed that an interposer is used for such circuit platform.
Interconnection components, such as interposers, may be in electronic assemblies for a variety of purposes, including facilitating interconnection between components with different connection configurations or to provide spacing between components in a microelectronic assembly, among others. Interposers may include a semiconductor layer, such as of silicon or the like, in the form of a sheet or layer of material or other substrate having conductive elements such as conductive vias extending within openings which extend through such layer of semiconductor material. Such conductive vias may be used for signal transmission through such interposer. In some interposers, ends of such vias may be used as contact pads for connection of such interposer to other microelectronics components. In other examples, one or more RDLs may be formed as part of such interposer on one or more sides thereof and connected with one or both ends of such vias. An RDL may include numerous conductive traces extending on or within one or more dielectric sheets or layers. Such traces may be provided in one level or in multiple levels throughout a single dielectric layer, separated by portions of dielectric material within such RDL. Vias may be included in an RDL to interconnect traces in different levels of such RDL.
A bottom IC 10-3 of such ICs in a 3D stack optionally may be coupled to an interposer or interposer die 40. Interposer 40 may be an active die or a passive die. For purposes of clarity and not limitation, it shall be assumed that interposer 40 is a passive die. IC 10-3 may be coupled to interposer 40 by microbumps 52. Interposer 40 may be coupled to a package substrate 41. Package substrate 41 may be formed of thin layers called laminates or laminate substrates. Laminates may be organic or inorganic. Examples of materials for “rigid” package substrates include an epoxy-based laminate such as FR4, a resin-based laminate such as bismaleimide-triazine (“BT”), a ceramic substrate, a glass substrate, or other form of package substrate. An under fill 54 for a flip chip attachment may encapsulate C4 bumps or other solder balls 53 used to couple interposer 40 and package substrate 41. A spreader/heat sink (“heat sink”) 43 may be attached to package substrate 41, and such heat sink 43 and substrate package 41 in combination may encase ICs 10 and interposer 40 of such 3D stack. A thermal paste 42 may couple an upper surface of IC 10-1 on top of such 3D stack to an upper internal surface of such heat sink 43. Ball grid array (“BGA”) balls or other array interconnects 44 may be used to couple package substrate 41 to a circuit platform, such as a PCB for example.
3D wafer-level packaging (“3D-WLP”) may be used for interconnecting two or more ICs, one or more ICs to an interposer, or any combination thereof, where interconnects thereof may use via structures 18. Optionally, ICs may be interconnected die-to-die (“D2D”) or chip-to-chip (“C2C”), where interconnects thereof may use via structures 18. Further, optionally, ICs may be interconnected die-to-wafer (“D2W”) or chip-to-wafer (“C2W”), where interconnects thereof may use via structures 18. Accordingly, any of a variety of die stacking or chip stacking approaches may be used to provide a 3D stacked IC (“3D-SIC” or “3D-IC”).
A dielectric layer 302 is grown or deposited or a combination thereof on an upper surface 331 of support structure 301. For example, a full-thickness silicon wafer may be used to grow a thermal oxide to provide a dielectric layer 302. A masking layer 303, such as a resist, is deposited and patterned on dielectric layer 302. Masking layer 303 is patterned to define openings 332 in masking layer 303 exposing corresponding portions of an upper surface of dielectric layer 302. A dielectric etch 310 operation, which may be a wet or dry etch, is performed to etch recesses 333 into dielectric layer 302 through openings 332. Dielectric etch 310 may be an anisotropic etch.
Masking layer 303 may be removed, and one or more metal or other conductive layers (“metal layer 304”) may be deposited on an upper surface of dielectric layer 302, including into recesses formed therein, with a metal deposition 311 operation. Recesses 333 formed in dielectric layer 302 may be on a pitch 352, as described below in additional detail.
An upper portion of metal layer 304 may be removed by a metal etch or a CMP 312 operation. A lower portion of metal layer 304 may remain in recesses 333 after such a CMP 312 operation to provide conductive pads, traces, contracts, and/or other conductive structures (“contacts”) 338, whether generally horizontal or vertical conductive structures.
Operations as described with reference to
After such BEOL processing, a BEOL stack 315 may be provided having a plurality of dielectric layers 302 and a plurality of metal layers 304. A lower surface, generally surface 334, of a lowermost set of conductive structures of a BEOL stack 315 may resemble a bondable backside surface, such as for example a surface with under bump metallization pads or bond pads as contacts 338. An uppermost or top surface 335 of such a BEOL stack 315 may resemble a bondable front side surface of an interposer die, such as for example a surface having contacts 339 used to mount to a die using microbumps or other fine pitch contacts.
Contacts 339 may be provided on an upper side 335 of BEOL stack 315 with a pitch 351. In an implementation, pitch 351 may be less than approximately 100 microns. Generally, by “fine pitch” it is meant a pitch of less than approximately 100 microns. More particularly, in some implementations, a “fine pitch” may be less than approximately 60 microns. Contacts 338 provided on a lower side of BEOL stack 315 may have a pitch 352, where pitch 351 of contacts 339 is less than pitch 352 of contacts 338. In an implementation, pitch 352 of contacts 338 may be greater than approximately 50 microns and less than approximately 500 microns. Along those lines, there may be multiples of tens of thousands of contacts 339, while there may be multiples of thousands of contacts 338.
Conductive metal layers 304 of BEOL stack 315 may extend horizontally and/or vertically through insulating layers 302 of BEOL stack 315 for providing various interconnections to and between contacts 338 and 339. Along those lines, a portion of conductive metal layers 304 may be interconnected to one another to provide electrically conductive paths, such as conductive path 337 for example, from a portion of contacts 339 on upper side 335 of BEOL stack 315 to contacts 338 on a lower side 334 of BEOL stack 315. Electrically conductive paths 337 may be used to interconnect at least two electrical components, such as for example integrated circuit dies 10-1 and 10-2, via a portion of contacts 339 to upper side 335 of BEOL stack 315 via microbumps 52 or flip-chip solder bumps. Again, micro bumps 52 may be for a pitch 351. An under fill 54 may be injected under microbumped integrated circuit dies 10-1 and 10-2 followed by depositing or molding an encapsulant 316. Electrically conductive paths 337 may be used to interconnect a circuit platform via contacts 338 to a lower side 334 of BEOL stack 315 after removal of support structure 301, as described below in additional detail.
With particular reference to
After removal of support structure 301, a lowermost portion of an initial dielectric layer 302 may be removed by a CMP operation as previously described, or other material removal operation for exposing lower surface 334 to expose lower surfaces of contacts 338. With respect to the latter, the mask used to pattern masking layer 303 may be used to expose lower surfaces 334 of contacts 338. Along those lines, another masking layer 303 may be deposited and patterned on a lower surface 341 of BEOL stack 315 to define another set of openings 332. Another dielectric etch 310 may be used to form opening down to lower surfaces 334 of contacts 338.
Contacts 338 may be coupled to a package substrate 319, or other circuit platform. In the example of
A support structure 301 is obtained. For this implementation, such support structure 301 may be a transparent carrier, such as a glass, quartz, sapphire, or other transparent material.
A sacrificial layer 401, such as less than approximately 100 nm thick, is deposited on upper surface 331 of support structure 301. Such sacrificial layer 401 may be GaN, InN, or other readily removable layer in accordance with the following description. Such sacrificial layer 401 may be deposited with CVD, sputtering, e-beam evaporation, or other type of deposition.
A dielectric layer 302 is deposited on sacrificial layer 401. This first or initial dielectric layer 302 may be one from which sacrificial layer 401 is more easily removed for a laser lift-off, such as a SiN layer for example. Optionally, a GaN sacrificial layer 401 may additionally provide an initial dielectric layer 302, which is patterned as described below in additional detail. Thus, a laser lift-off may be used to remove a thin layer of GaN while leaving a portion of GaN in place as a dielectric layer 302. Optionally, a GaN initial dielectric layer 302 may be entirely removed during lift-off to leave metal contacts 338 exposed.
A masking layer 303, such as a resist, is deposited and patterned on dielectric layer 302. Masking layer 303 is patterned to define openings 332 in masking layer 303 exposing corresponding portions of an upper surface of dielectric layer 302. A dielectric etch 310 operation, which may be a wet or dry etch, is performed to etch recesses 333 into dielectric layer 302 through openings 332. Dielectric etch 310 may be an anisotropic etch. The above description up to removal of support structure 301 is the same for both sets of
With particular reference to
A masking layer 502 is deposited and patterned on a multi-BEOL stack 515 to define one or more recesses 503 associated with stress relief scribe lanes or street lines. A dielectric etch 502 is used to etch an opening through dielectric layers 302 between BEOL stacks 315 of multi-BEOL stack 515 to form an opening or trench 504. Dielectric etch 502 in this example is a stop on material of support substrate 301 etch, such as a stop on silicon dielectric etch for the example of a silicon wafer as a support structure 301. Opening 504 may be used to delineate BEOL stacks 315 of a multi-BEOL stack 515.
Respective sets of integrated circuit dies, or other suitable dies, may be interconnected to each of BEOL stacks 315 of a multi-BEOL stack 515 while such BEOL stacks 315 are attached to a same support structure 301. Continuing the above example, pairs of integrated circuit dies 10-1 and 10-2 are respectively interconnected to BEOL stacks 315 through corresponding sets of microbumps followed by injection of an under fill, such as previously described. An encapsulation, such as by depositing or molding an encapsulant 316, may be used to encapsulate each of such pairs of integrated circuit dies 10-1 and 10-2 in a same operation, namely wafer-level encapsulation.
Additionally, even though it has been assumed that two or more integrated circuit or other dies are interconnected to a BEOL stack 315, in other configurations a single integrated circuit die may be attached to a BEOL stack 315. For example, a BEOL stack 315 may be formed independently from a large integrated circuit die to reduce the number of BEOL operations used in forming such a large integrated circuit die. This may improve yield of such large integrated circuit die by avoiding many BEOL operations, which operations may effectively be transferred to formation of a BEOL stack 315. Such BEOL stack 315 may be substantially less expensive to manufacture than a large integrated circuit die, and accordingly such BEOL stack 315 may be tested prior to interconnection to any integrated circuit die. Thus, complications associated with BEOL operations of an integrated circuit die may be removed from fabrication of such integrated circuit die. Moreover, if formation of BEOL layers increases a die's size, then removing BEOL operations of an integrated circuit die to a BEOL stack may increase the number of integrated circuit dies per wafer.
In
In this example, integrated circuit dies 10-1 and 10-2 are interconnected to a lower surface 334 of BEOL stack 315-1 with corresponding microbumps 52, under fill 54, and encapsulant 316, and integrated circuit dies 10-3 and 10-4 are interconnected to an upper surface 335 of BEOL stack 315-1 with corresponding microbumps 52, under fill 54, and encapsulant 316. Even though pairs of integrated circuit dies are illustratively depicted on opposing sides of BEOL stack 315-1, either or both of such opposing sides may have one or more integrated circuit dies interconnected respectively thereto.
BEOL stack 315-1 may include horizontal conductive paths 342 for interconnection of dies 10-1 and 10-2, as well as horizontal conductive paths 342 for interconnection of dies 10-3 and 10-4. Likewise, BEOL stack 315-1 may include vertical conductive paths 337 for interconnection of dies 10-1 and 10-3, as well as vertical conductive paths 337 for interconnection of dies 10-2 and 10-4. These are just some examples of die-to-die interconnections on a same side and on opposing sides of BEOL stack 315-1, and other such interconnections may be used.
For this 3D stacked IC device 300 for dual-sided die attachment, temporary support structure 301 is left in place for coupling of integrated circuit dies 10-3 and 10-4, such as previously described with reference to
While the foregoing describes exemplary embodiment(s) in accordance with one or more aspects of the invention, other and further embodiment(s) in accordance with the one or more aspects of the invention may be devised without departing from the scope thereof, which is determined by the claim(s) that follow and equivalents thereof. Claim(s) listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.
