The present disclosure relates to a chip package and a manufacturing method of the chip package.
Image sensors are devices that convert optical signals into electrical signals. Currently, the types of image sensors commonly used include charge coupled device (CCD) and complementary metal-oxide semiconductor (CMOS). Complementary metal-oxide semiconductor image sensors (CIS) have the characteristics of low cost, low power consumption, small size and high integration, and are widely used in many fields such as mobile phones, automobiles, security control, medical treatment, etc.
When manufacturing the chip package of an image sensor, the diced image sensor chip is usually bonded to a carrier board, and then the cut glass sheet is placed on the image sensor chip, and a wire bonding process and a molding process are performed in sequence. However, the aforementioned steps are performed in chip-scale packaging, and it will take a lot of time to bond a large number of chips and glass sheets one by one, and the chips are easily contaminated, such that product yield is difficult to improve. In addition, because the coefficient of thermal expansion (CTE) of a molding material does not match a glass sheet, the molding material generally covering the entire sidewall of the glass sheet is easy to cause the glass sheet to break.
One aspect of the present disclosure provides a chip package.
According to some embodiments of the present disclosure, a chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.
In some embodiments, a top of an edge of the molding material is lower than a position of half a thickness of the light transmissive sheet.
In some embodiments, a thickness of the light transmissive sheet is in a range from 50 μm to 1000 μm, and a thickness of the supporting element is in a range from 40 μm to 250 μm.
In some embodiments, a sidewall of a top portion of the light transmissive sheet has a protruding portion extending in a horizontal direction, and the molding material extends to a bottom surface of the protruding portion.
In some embodiments, a corner of a top portion of the chip has a concave portion, and the molding material extends to the concave portion.
In some embodiments, an outer sidewall of the supporting element is recessed in a sidewall of the light transmissive sheet.
In some embodiments, an outer sidewall of the supporting element is aligned with a sidewall of the light transmissive sheet in a vertical direction.
In some embodiments, a top portion of an outer sidewall of the supporting element is aligned with a sidewall of the light transmissive sheet in a vertical direction, and a bottom portion of the outer sidewall of the supporting element protrudes from the sidewall of the light transmissive sheet.
In some embodiments, an entire outer sidewall of the supporting element protrudes from a sidewall of the light transmissive sheet.
In some embodiments, the carrier board has a conductive pad, the chip has a contact electrically connected to the conductive pad of the carrier board by a conductive wire, and the conductive wire is located in the molding material.
Another aspect of the present disclosure provides a manufacturing method of a chip package.
According to some embodiments of the present disclosure, a manufacturing method of a chip package includes forming a supporting element having a grip shape on a light transmissive sheet; forming a temporary bonding layer covering the light transmissive sheet; cutting the light transmissive sheet and the supporting element along the supporting element to form a plurality of trenches; bonding the supporting element to a wafer such that the supporting element is located between the light transmissive sheet and the wafer and surrounds a plurality of sensing areas of the wafer; removing the temporary bonding layer; cutting the wafer along the trenches to form a plurality of chips; bonding one of the chips on a carrier board; and forming a molding material on the carrier board, wherein the molding material surrounds said chip on the carrier board and the light transmissive sheet, and a top surface of the molding material is lower than a top surface of the light transmissive sheet.
In some embodiments, forming the molding material on the carrier board is performed such that a top of an edge of the molding material is lower than a position of half a thickness of the light transmissive sheet.
In some embodiments, the manufacturing method of the chip package further includes flipping a combination of the light transmissive sheet, the supporting element, and the temporary bonding layer after the trenches is formed and before the supporting element is bonded to the wafer, such that the temporary bonding layer is above the light transmissive sheet, and the supporting element is below the light transmissive sheet.
In some embodiments, cutting the light transmissive sheet and the supporting element along the supporting element includes cutting, by a first cutting tool, a portion of the light transmissive sheet; and cutting, by a second cutting tool, another portion of the light transmissive sheet and the supporting element, wherein a width of the second cutting tool is greater than a width of the first cutting tool, such that a sidewall of the light transmissive sheet has a protruding portion extending in a horizontal direction.
In some embodiments, forming the molding material on the carrier board is performed such that the molding material extends to a bottom surface of the protruding portion.
In some embodiments, cutting the wafer along the trenches to form the chips includes cutting, by a first cutting tool, a top portion of the wafer; and cutting, by a second cutting tool, a bottom portion of the wafer, wherein a width of the second cutting tool is less than a width of the first cutting tool, such that a corner of a top portion of each of the chips has a concave portion.
In some embodiments, cutting the light transmissive sheet and the supporting element along the supporting element includes cutting, by a first cutting tool, the light transmissive sheet; and cutting, by a second cutting tool, the supporting element, wherein a width of the second cutting tool is greater than a width of the first cutting tool, such that an outer sidewall of the supporting element is recessed in a sidewall of the light transmissive sheet.
In some embodiments, cutting the light transmissive sheet and the supporting element along the supporting element includes cutting, by a first cutting tool, the light transmissive sheet and a portion of the supporting element; and cutting, by a second cutting tool, another portion of the supporting element, wherein a width of the second cutting tool is less than a width of the first cutting tool, such that a top portion of an outer sidewall of the supporting element is aligned with a sidewall of the light transmissive sheet in a vertical direction, and a bottom portion of the outer sidewall of the supporting element protrudes from the sidewall of the light transmissive sheet.
In some embodiments, cutting the light transmissive sheet and the supporting element along the supporting element includes cutting, by a first cutting tool, the light transmissive sheet; and cutting, by a second cutting tool, the supporting element, wherein a width of the second cutting tool is less than a width of the first cutting tool, such that an entire outer sidewall of the supporting element protrudes from a sidewall of the light transmissive sheet.
In some embodiments, the manufacturing method of the chip package further includes after bonding one of the chips on the carrier board, electrically connecting a conductive wire to a contact of the chip on the carrier board and a conductive pad of the carrier board by wire bonding, wherein after the molding material is formed on the carrier board, the conductive wire is located in the molding material.
In the aforementioned embodiments of the present disclosure, during the manufacturing method of the chip package, the light transmissive sheet is covered by the temporary bonding layer, and then the light transmissive sheet and the supporting element are cut along the supporting element, and then the supporting element is bonded to the wafer. Therefore, the wafer can be cut along the trenches to form the chips, thereby realizing wafer-level packaging for bonding the light transmissive sheet to the chips. As a result, process time can be saved, and the sensing area of the chip is prevented from being polluted to improve product yield. In a subsequent process, the chip can be bonded to the carrier board, and the amount of the molding material can be controlled to form on the carrier board such that the top surface of the molding material is lower than the top surface of the light transmissive sheet. Such a configuration can reduce the influence of the mismatch of the coefficient of thermal expansion (CTE) between the light transmissive sheet and the molding material, thereby preventing the light transmissive sheet from cracking due to temperature during manufacturing processes.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In this embodiment, the chip 120 may be an image sensor, such as a complementary metal-oxide semiconductor (CMOS), and the sensing area 122 may be an image sensing area. The material of the light transmissive sheet 130 may be glass, and the material of the supporting element 140 may be epoxy, but the present disclosure is not limited in this regard. The carrier board 110 may have conductive pads 112 and 116, a circuit 114, and a conductive structure 118. The circuit 114 may be electrically connected to the conductive pads 112 and 116. The conductive pad 112 is configured to electrically connect to the chip 120. The conductive structure 118 is electrically connected to the conductive pad 116, and is configured to electrically connect to another electronic component (e.g., a system PCB).
Specifically, since the amount of the molding material 150 has been specially designed, the top surface 152 of the molding material 150 can be lower than the top surface 132 of the light transmissive sheet 130 after the molding material 150 is formed on the carrier board 110. Compared with a tradition configuration, the height of the top surface 152 of the molding material 150 is reduced by 20% to 50%. Such a configuration can electively reduce the influence of the mismatch of the coefficient of thermal expansion (CTE) between the light transmissive sheet 130 and the molding material 150, thereby preventing the light transmissive sheet 130 from cracking due to temperature during manufacturing processes.
In some embodiments, the top of an edge 151 of the molding material 150 is lower than the position of half a thickness H of the light transmissive sheet 130 (i.e., lower than the position of a dotted line L). The thickness H of the light transmissive sheet 130 may be in a range from 50 μm to 1000 μm. A thickness h of the supporting element 140 is in a range from 40 μm to 250 μm. The outer sidewall 141 of the supporting element 140 is aligned with the sidewall 131 of the light transmissive sheet 130 in a vertical direction. Moreover, the chip 120 may be bonded to the carrier board 110 by an adhesive layer A, and the chip 120 has a contact 124. The contact 124 can be electrically connected to the conductive pad 112 of the carrier board 110 by a conductive wire W, such as performing a wire bonding process. In addition, the conductive wire W is located in the molding material 150.
It is to be noted that the connection relationships, the materials, and the advantages of the elements described above will not be repeated in the following description. In the following description, the manufacturing method of the chip package 100 will be explained.
After the light transmissive sheet 130a is covered by the temporary bonding layer TB, the structure of
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In the following description, other types of chip packages and manufacturing thereof will be explained.
In summary, during the manufacturing method of the chip package, the light transmissive sheet 130 which is not yet cut is covered by the temporary bonding layer TB (see
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims priority to U.S. Provisional Application Ser. No. 63/342,088, filed May 14, 2022, which is herein incorporated by reference.
Number | Date | Country | |
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63342088 | May 2022 | US |