Patent Application
20250038068
This application claims priority to China Application Serial Number 202310914504.3, filed Jul. 24, 2023, which is herein incorporated by reference.
The present invention relates to a circuit board and a manufacturing method thereof, and particularly relates to a circuit board with a refrigeration structure and its manufacturing method.
With the development of semiconductor technology, an image quality of an image sensor is getting better and better, but the required power consumption increases accordingly, so that the energy required for heat dissipation also increases. If the heat dissipation problem of the image sensor cannot be effectively solved, it may cause hot pixels, thereby destroying the image quality.
If merely using a metal layer under the image sensor for heat dissipation, the power consumption of the image sensor cannot be effectively dissipated when the image sensor works for a long time or provides a higher image quality. In view of the above, there is a need to develop a circuit board that can effectively dissipate heat to overcome the above disadvantages.
At least one embodiment of the present invention provides a circuit board with a refrigeration structure and a manufacturing method thereof, in which the refrigeration structure can provide cold ends to remove heat energy from an image sensor. Therefore, the heat energy of the circuit board can be effectively dissipated.
The circuit board provided by at least one embodiment of the present invention includes a main board, a first bonding layer, a second bonding layer, a thermistor layer, a plurality of N-type semiconductor units, and a plurality of P-type semiconductor units. The main board includes a first external structure, a second external structure, and an internal structure. The internal structure is disposed between the first external structure and the second external structure, in which the internal structure, the first external structure, and the second external structure are stacked along a first direction. The internal structure includes a first internal circuit layer, a second internal circuit layer, and an insulating layer. The insulating layer is disposed between the first internal circuit layer and the second internal circuit layer, in which the insulating layer, the first internal circuit layer, and the second internal circuit layer are stacked along the first direction. The first bonding layer is disposed between the internal structure and the first external structure, in which the first bonding layer connects to the internal structure and the first external structure. The second bonding layer is disposed between the internal structure and the second external structure, in which the second bonding layer connects to the internal structure and the second external structure. The thermistor layer is embedded in the first bonding layer and disposed on the insulating layer and the first internal circuit layer. The N-type semiconductor units and the P-type semiconductor units are embedded in the second bonding layer and electrically connect to the second internal circuit layer and the second external structure, in which the N-type semiconductor units and the P-type semiconductor units alternately arrange along a second direction perpendicular to the first direction, and an orthogonal projection of the N-type semiconductor units and the P-type semiconductor units on the insulating layer overlaps an orthogonal projection of the thermistor layer on the insulating layer.
In at least one embodiment of the present invention, the second internal circuit layer includes a plurality of cold ends, and the second external structure includes a plurality of hot ends, in which an ith N-type semiconductor unit is adjacent to an ith P-type semiconductor unit, the ith N-type semiconductor unit and the ith P-type semiconductor unit connect to a same cold end, and an ith P-type semiconductor unit and a (i+1)th N-type semiconductor unit connects to a same hot end, where i is a positive integer.
In at least one embodiment of the present invention, N-type semiconductor units and P-type semiconductor units connect to the second external structure.
In at least one embodiment of the present invention, the circuit board further includes a thermal conductive layer and a dissipation reinforcing layer. The thermal conductive layer is disposed on the second external structure, in which the thermal conductive layer connects to the second external structure and the second bonding layer. The dissipation reinforcing layer is disposed on the thermal conductive layer.
In at least one embodiment of the present invention, the circuit board further includes a thermal conductive layer and an image sensor. The thermal conductive layer is disposed on the thermistor layer. The image sensor is disposed on the thermal conductive layer.
In at least one embodiment of the present invention, a protruding portion of the internal structure protrudes from a sidewall of the first external structure and a sidewall of the second external structure, in which the main board further includes a first cover layer and a second cover layer. The first cover layer covers the protruding portion of the internal structure. The second cover layer covers the protruding portion of the internal structure. The circuit board further includes an extending board, in which the extending board electrically connects to the protruding portion of the internal structure.
In at least one embodiment of the present invention, the extending board comprises a data processor and a driving circuit.
In at least one embodiment of the present invention, the circuit board further includes a solder mask layer disposed on the first external structure and on the second external structure.
In at least one embodiment of the present invention, the circuit board further includes a protecting layer on the first external structure, in which the protecting layer includes a nickel-gold layer.
At least one embodiment of the present invention provides a manufacturing method of a circuit board comprising the following operations. An internal structure is provided, in which the internal structure includes a first internal circuit layer, a second internal circuit layer, and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer, in which the insulating layer, the first internal circuit layer, and the second internal circuit layer stack along a first direction; a thermistor layer is formed on the first internal circuit layer, in which the thermistor layer connects to the insulating layer and the first internal circuit layer; a first peelable glue layer is formed on the thermistor layer; a first bonding layer is formed on the first internal circuit layer, in which the first bonding layer encapsulates the first peelable glue layer and the thermistor layer; a second bonding layer is formed on the second internal circuit layer, in which the second bonding layer includes a plurality of recesses, the recesses expose the second internal circuit layer, and an orthogonal projection of the recesses on the insulating layer overlaps an orthogonal projection of the thermistor layer on the insulating layer; a N-type semiconductor material and a P-type semiconductor material are filled in the recesses to form N-type semiconductor units and P-type semiconductor units, in which the N-type semiconductor units and the P-type semiconductor units alternately arrange along a second direction perpendicular to the first direction; a first external structure is formed on the first bonding layer; a second external structure is formed on the second bonding layer, such that the second external structure electrically connects to the N-type semiconductor units and the P-type semiconductor units; and the first peelable glue layer and a portion of the first bonding layer located above the first peelable glue layer are removed, and the thermistor layer is exposed.
In at least one embodiment of the present invention, the manufacturing method of the circuit board further includes: a thermal conductive layer is formed on the thermistor layer.
In at least one embodiment of the present invention, the manufacturing method of the circuit board further includes: an image sensor is disposed on the thermistor layer; a thermal conductive layer is formed on the second external structure, in which the thermal conductive layer connects to the second external structure and the second bonding layer; a dissipation reinforcing layer is formed on the thermal conductive layer.
In at least one embodiment of the present invention, the manufacturing method of the circuit board further includes: after the image sensor is disposed, bonding wires are formed above the image sensor, such that the image sensor is electrically connected to the first external structure.
In at least one embodiment of the present invention, the manufacturing method of the circuit board further includes: a first cover layer is formed on first internal circuit layer, in which the first cover layer separates from the thermistor layer; a second cover layer is formed on the second internal circuit layer, in which the second cover layer separates from the recesses, and an orthogonal projection of the first cover layer on the insulating layer overlaps an orthogonal projection of the second cover layer on the insulating layer; a second peelable glue layer is formed on the first cover layer, in which in the operation of forming the first bonding layer, the first bonding layer further encapsulates the second peelable glue layer and the first cover layer; a third peelable glue layer is formed on the second cover layer, in which in the operation of forming the second bonding layer, the second bonding layer further encapsulates the third peelable glue layer and the second cover layer; a second peelable glue layer is removed to expose the first cover layer; and a third peelable glue layer is removed to expose the second cover layer.
In at least one embodiment of the present invention, the manufacturing method of the circuit board further includes: after the first bonding layer and the second bonding layer are formed, a plated-through hole is formed.
In at least one embodiment of the present invention, the manufacturing method of the circuit board further includes: after the through-hole is formed, a solder mask layer is formed in the plated-through hole and on the first external structure and the second external structure.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
In the following text, in order to clearly present the technical features of the present disclosure, the dimensions (such as lengths, widths, thicknesses and depths) of the components (such as insulating layers, circuit layers, and through-holes, etc.) in the drawings may be enlarged in a non-proportional manner, and the number of some components may be reduced. Therefore, the description and explanation of the following embodiments are not limited to the number of components in the drawings and the size and shape of the components, but should cover the deviations in sizes, shapes and both caused by actual manufacturing processes and/or tolerances. For example, a planar surface shown in the drawings may have rough and/or non-linear features, while acute angles shown in the drawings may be rounded. Therefore, the components shown in the drawings of the present disclosure are mainly for illustration, and are not intended to accurately depict the actual shapes of the components, nor are used to limit the scope of the patent application of the present disclosure.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. That is, when the device is oriented differently from the drawings (rotated 90 degrees or at other orientations), the spatially relative terms used in the present disclosure may also be interpreted accordingly.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
As used herein, “about”, “approximately”, “essentially”, or “substantially” can be used according to optical properties, etching properties, mechanical properties, measurement properties, coating properties or other properties. Accepted deviation ranges or standard deviations are selected, instead of one standard deviation for all properties. It should be noted that a first direction D1 and a second direction D2 are labeled in the drawings to present the configuration relationship of the components in the drawings, and the first direction D1 and the second direction D2 are substantially perpendicular to each other.
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In some embodiments, a material of the insulating layer 130 may be an insulating material such as, polyimide (PI), glass fiber epoxy resin (FR4), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethylene (PE), but is not limited thereto.
In the present embodiment, the first internal circuit layer 110 and the second internal circuit layer 120 are formed by first forming a dry film, and then exposed and developed. Therefore, the first internal circuit layer 110 and the second internal circuit layer 120 are formed by a subtractive process. However, in other embodiments, the first internal circuit layer 110 and the second internal circuit layer 120 may be formed by a semi-additive process or an additive process. In some embodiments, a material of the first internal circuit layer 110 and/or second internal circuit layer 120 may be a conductive material such as copper, gold, or silver, but is not limited thereto.
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N-type semiconductor units 510a, 510b, and 510c and P-type semiconductor units 520a, 520b, and 530c alternately arrange along the second direction D2. Taking
In the present embodiment, the N-type semiconductor material is filled into portions of the recesses 422 by using a printing process, and then the N-type semiconductor material is baked to form N-type semiconductor units 510a, 510b, and 510c. After that, the P-type semiconductor material is filled into the remaining portions of the recesses 422 by using a printing process, and then the P-type semiconductor material is baked to form the P-type semiconductor units 520a, 520b, and 530c. N-type semiconductor is the semiconductor in which the electron density in the conduction band is greater than the hole density in the valence band, such that the N-type semiconductor material is formed by adding acceptor impurities (for example, doping arsenic or phosphorus) to the crystal structure of silicon. P-type semiconductor is the semiconductor in which the hole density in the conduction band greater than the electron density in the valence band, such that the P-type semiconductor material is formed by adding acceptor impurities (for example, boron doping) to the crystal structure of silicon. In some embodiments, the N-type semiconductor material and the P-type semiconductor material may be bismuth antimony telluride alloys, bismuth telluride, lead telluride, silicon germanium, or skutterudite. In the present example, the N-type semiconductor material may be Bi2Sb2.7Te0.3, and the P-type semiconductor material may be BiSbTe.
It is understood that one N-type semiconductor unit and the adjacent P-type semiconductor unit form a pair of thermocouples.
Referring to
It is noted that second external structure 620 includes hot ends 621 and 622. It is understood that both of the hot ends 621 and 622 are metal pads of the second external structure 620 at this stage. Specifically, the P-type semiconductor unit 520a and the N-type semiconductor unit 510b connect to the same hot end 621, the P-type semiconductor unit 520b and the N-type semiconductor unit 510c connect to the same hot end 622, and the hot end 621 and the hot end 622 are spaced apart from each other. In other words, the N-type semiconductor units 510a, 510b, and 510c and the P-type semiconductor units 520a, 520b, and 530c form a series structure between the cold ends 121, 122, and 123 and the hot ends 621 and 622.
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In the present embodiment, the first peelable glue layer 310, the second peelable glue layer 320, and the third peelable glue layer 330 are removed by using a routing process. It is understood that the material of the peelable glue layer has certain viscosity, such that it hardly has residual glue on the underlying film layer when the peelable glue layer is removed.
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In the present embodiment, a material of the thermal conductive layer 73 may be silicone. In the present embodiment, the thermal conductive layer 730 is formed by a laminating process.
In the embodiment of
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The N-type semiconductor units 510a, 510b, and 510c, the P-type semiconductor units 520a, 520b, and 530c electrically connect to the cold ends 121 and 122 of the second internal circuit layer 120 and the hot ends 621 and 622 of the second external structure 620, such that the refrigeration structure are a series structure. Taking
The disclosed extending board EB may be used as a central controller, which may determine the current magnitude flowing through the refrigeration structure according to the temperature information (for example, the temperature of the image sensor 820 measured by the thermistor layer 210).
The disclosed thermistor layer 210 is embedded in the first bonding layer 410, and the refrigeration structure is embedded in the second bonding layer 420, in which the thermistor layer 210 connects to the cold ends 121 and 122. The thermistor layer 210 is used to monitor the temperature of the upper image sensor 820 and transmits the monitored temperature to the extending board EB, and then the extending board EB uses a data processor to determine the current magnitude flowing through the refrigeration structure.
Referring to arrows of the refrigeration structure shown in
Based on the above, the provided circuit board of the present invention has the refrigeration structure. The refrigeration structure can adjust the cooling effect according to the demand, and the cold ends of the refrigeration structure can remove the heat energy of the image sensor. Therefore, the heat energy of the circuit board can be effectively dissipated.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310914504.3 | Jul 2023 | CN | national |
