The present invention relates to resistive random access memory (ReRAM) devices. More particularly, the present invention relates to circuitry and methods for programming ReRAM devices.
ReRAM cells program by diffusion of metal ions through an electrolyte layer that is otherwise a barrier to electron flow. During programming an electric field (e-field) is presented across the device by placing appropriate potentials on the bit lines and word lines to which the cell is connected. The e-field increases until it causes breakdown of the electrolyte as the metal filament diffuses through the electrolyte from the ion source side of the device and reaches the opposite electrode. This often results in damage to the electrolyte, which makes the device difficult to erase and may even lead to device failure. A reverse e-field is applied to erase the device. The ion source of each of the ReRAM cells, throughout this document, is illustrated by the wider end.
Attempts to control this programming process have been made in some designs by placing a current limiting device on the bit line to limit the avalanche current through the ReRAM device during the programming process.
A capacitor 24 depicted in dashed lines represents the capacitance of output node 22 which is shared by many ReRAM cells. Capacitor 24 is shown only in
P-channel transistor 16 is common to all ReRAM cells on the output node 22 and acts as a current drive/limit transistor in programming and erasing modes of
As shown in
As shown in
After programming ReRAM device 12, during an operating mode of the 1T1R ReRAM memory cell 10, the ReRAM cell 10 is biased as shown in
This prior-art arrangement is inadequate when programming the ReRAM device as it ignores the current dump resulting from the capacitance (in dashed lines) of the output node 22. If the ReRAM device 12 is in a high resistance state, i.e. is in an erased state, its resistance is about 1 Mohm. When an applied programming voltage causes it to change to its low resistance state (e.g., 10K ohms) there will be a large current spike associated with the discharge of the capacitor 24. This large current spike can damage the structure of the ReRAM device 12.
According to one aspect of the present invention, a ReRAM device is positioned in the drain circuit of a current limiting device, such that when the voltage across the ReRAM device drops rapidly during the programming process, the current will not increase significantly. For example, the n-channel access transistor/programming transistor may have its source connected to a lower power rail so that the bias on the gate will cause it to be a current limiting device, thereby limiting the capacitive dump spike current. In particular, the access transistor is connected and biased so as to act as a current limiter. In the prior art only the p-channel transistor is biased as a current limiter.
According to another aspect of the present invention, the application of programming voltage is spit into at least two pulses. Each additional pulse is accompanied by an increase in gate bias to increase the current drive such that the metal filament forming in the ReRAM device increases in size in a controlled manner. In particular, a first pulse is designed so as not allow enough current to cause any damage to the device, but be sufficient to allow an initial filament to form. This pulse is formed by control of the gate voltage to the access transistor. One or more additional pulses are generated using gate voltages that allow for the passage of larger values of current, sufficient to drive the device to the low-resistance state.
According to another aspect of the present invention, a variable ramp bias is applied to the bit line such that the e-field applied across the ReRAM device is minimized initially as the filament is forming and is increased after the ReRAM device begins to conduct current. Thus, the bias voltage is increased in concert with each successive current pulse.
According to another aspect of the present invention, all three aforementioned aspects of the present invention, or any combination of them may be employed to limit damage to the solid electrolyte layer of the ReRAM device.
The invention will be explained in more detail in the following with reference to embodiments and to the drawing in which are shown:
Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.
Referring now to
In the embodiment depicted in
The effect of employing the circuit arrangement shown in
The ReRAM cells 10 and 30 of
Referring now to
ReRAM cell 40 includes an upper ReRAM device 42 and a lower ReRAM device 44. Upper ReRAM device 42 is connected between a top node 46 (a first bit line) and an output node 48 through p-channel access transistor 50 and lower ReRAM device 44 is connected between a bottom node 52 (a second bit line) and the output node 48 through n-channel access transistor 54. ReRAM cell 40 may be used as a configuration cell for a user-programmable integrated circuit such as an FPGA integrated circuit. When ReRAM cell 40 is so used, the output node 48 is shown connected to the gate of one or more switch transistors 56. Switch transistors 56 may be used to make connections and define logic module functions in a user-programmable integrated circuit such as a field-programmable-gate-array (FPGA) integrated circuit. During normal circuit operation (when the ReRAM cell 40 is controlling switch transistor 56 by selectively turning it on or off) as depicted in
During normal circuit operation, one of ReRAM devices 42 and 44 will be in its on state and the other one of ReRAM devices 42 and 44 will be in its off state. Depending on which ReRAM device is on and which ReRAM device is off, node 48 will either be pulled up to the voltage at node 46 (VDD) to turn on switch transistor 56 or down to the voltage at node 52 (0V) to turn off switch transistor 56.
Because the ReRAM device that is in its on state will have almost no voltage across it, essentially the entire VDD voltage will be dropped across the series combination of the one of ReRAM devices 42 and 44 that is in its off state and its access transistor 50 or 54, respectively. The voltages applied respectively to the gates of p-channel access transistor 50 and n-channel access transistor 54 are selected such that VDD potential will be divided such that only about 0.2-0.5V will be maintained across the off-state ReRAM cell, the remainder of the voltage being dropped across its access transistor 50 or 54 to prevent overstressing the off-state ReRAM device. Assuming a VDD voltage of 1.5V, the gate voltage for a p-channel access transistor 50 having a Vt of −0.3V would be 0.75V, resulting in about 1.3V across the p-channel access transistor 50 and about 0.2V across off-state ReRAM device 42.
Similar conditions apply to an off-state ReRAM device 44 in series with the re-channel access transistor 54 as shown in
The ReRAM device 42, 44 that is in its on state has very little voltage across it and ReRAM device stress is not an issue. As an example, if ReRAM device 44 is in its low-resistance on state, and n-channel access transistor 44 has a Vt of 0.3V, and with a gate voltage of 0.75V, then n-channel transistor 54 is turned on and passes the 0V bias of node 52 to node 48. There is insignificant voltage drop as the current through the off-state ReRAM 42 is several orders of magnitude lower than can be sourced by the on-state ReRAM 44.
Before programming the ReRAM cell 40, preferably both ReRAM devices 42 and 44 are erased (turned off) to their high resistance states. Then, only one of the ReRAM devices 42 and 44 is programmed to its low resistance (on) state.
The terminal of p-channel transistor 50 connected to the bitline 46 through the upper ReRAM device 42, and upper ReRAM device 42 becomes the source of p-channel transistor 50 because it is at a higher potential than the other terminal (connected to 0V at the output node 48) and is thus turned on because its gate-to-source voltage is −1.8V. This causes current to flow through the upper ReRAM device 42 in a direction that causes the metal ions forming the conductive bridge to migrate through the solid electrolyte back towards the ion source to eliminate the conductive bridge. The gate of n-channel transistor 54 is biased at, for example, 0V. The terminal of n-channel transistor 54 connected to output node 48 becomes the source of n-channel transistor 54 because it is at a lower potential than the other terminal (connected to 1.8V at bitline 52 through the lower ReRAM device 44) and n-channel transistor 54 is thus turned off because its gate-to-source voltage is 0V. The current flow through ReRAM device 42 thus flows through programming transistor 58.
Because the bottom node 52 is also biased at 0V, the potential across lower ReRAM device 44 is such as to prevent migration of metal ions from the metal electrode into its solid electrolyte layer and it remains in an erased state. Lower ReRAM device 44 will not be programmed regardless of the bias applied to n-channel access transistor 54 during programming, which, as a non-limiting example, could be either 0V or 1.8V, or any voltage in between those values to lower the stress on the device not being programmed.
Referring now to
Persons of ordinary skill in the art will observe that, under these conditions, the terminal of n-channel access transistor 54 connected to output node 48 becomes its source and the terminal of n-channel access transistor 54 connected to lower ReRAM device 44 becomes its drain since it is at a higher voltage potential. The polarity of the voltage across lower ReRAM device 44 causes ions from the metal electrode to migrate into the solid electrolyte layer of the ReRAM device 44, forming a bridging connection to place it in its low resistance state to turn it on. As noted above, n-channel access transistor 54 is acting as a common-source current limiting device, responsive to the selected gate voltage, to limit the programming current and power dissipation in lower ReRAM device 44 during programming in accordance with the present invention. The actual voltage applied to the gate of the n-channel access transistor 54 in any particular circuit design will be determined by the Vt of n-channel access transistor 54 as well as the amount of current that is desired to flow through lower ReRAM device 44. The device geometry and characteristics of the ReRAM device being programmed will also affect the amount of programming current desired and thus the choice of the gate voltage. Persons of ordinary skill in the art will observe that because the top node 46 is also biased at 1.8V, the potential across upper ReRAM device 42 is the opposite of the polarity of the voltage across lower ReRAM device 44, such as to prevent migration of metal ions from the metal electrode into its solid electrolyte layer to form a bridging connection to place it in its low resistance state and it remains in an erased state. Upper ReRAM device will not be programmed regardless of the bias applied to the gate of p-channel access transistor 50 during programming, which, as a non-limiting example, could be either 0V or 1.8V.
According to another aspect of the present invention illustrated in
According to one exemplary non-limiting embodiment in which two pulses are employed, a typical first current pulse could be about 10 μA, followed by a second current pulse of about 100 μA. The larger current second pulse is preferably sufficient to drive the device to its low resistance state.
In other embodiments, a larger number of pulses could be employed. According to another exemplary non-limiting embodiment, three or more pulses could be employed, e.g., and as shown in
According to another aspect of the present invention illustrated in
According to another aspect of the present invention illustrated in
By way of illustration, the first ramp period 80 may have a duration of between about 100 nS and about 10 μS to a current value of about 10 μA. The second ramp period 96 may have a duration of between about 1 μS and about 1000 to a current value of about 80 μA. The third ramp period 104 may have a duration of between about 1 μS and about 1000 to a current value of about 100 μA. Persons of ordinary skill in the art will recognize that these durations and current values are nominal only and that the pulse widths, ramp durations and amplitudes to be selected for any given ReRAM device will depend on the number of pulses to be employed, the device geometry and characteristics of the ReRAM device being programmed, including the thickness and composition of the solid electrolyte as well as the composition of the metal layer ion source that will be used to form the conductive filament through the solid electrolyte. Such skilled persons will appreciate that these selections will be routine, as they are a normal component of performing the device characterizations of the ReRAM devices.
According to the aspects of the present invention in
In yet another aspect of this invention as also illustrated in
In the case of programming ReRAM device 44 in
According to another aspect of the present invention, the characteristics of the population of ReRAM devices on the wafer can be determined at wafer sort and constants can then be loaded into the individual die defining the number and amplitude of the pulses, as well as ramp rates, to be used to program the devices.
Referring now to
At reference numeral 116, and as shown in
At reference numeral 120 the resistance of the ReRAM device is measured during intervals between successive ones of the gate voltage pulses and the ramped voltage pulses. At reference numeral 122, the gate voltage pulses and the ramped voltage pulses are terminated when the resistance of the ReRAM device decreases below a threshold value. The method ends at reference numeral 124.
The present invention improves the endurance of a typical ReRAM memory cell on an integrated circuit.
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
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Child | 16693317 | US |