Patent Application
20250218977
The present invention relates generally to semiconductor devices, and more particularly to a semiconductor devices including through insulator vias (TIV).
Integrated circuits (“ICs”) are incorporated into many electronic devices. Integrated circuit (IC) packaging allows for multiple integrated circuits (ICs) to be vertically stacked in “three-dimensional (3D)” packages in order to save horizontal area on printed circuit boards (PCBs). An alternative packaging technique, referred to as 2.5D packaging, can use an interposer, which may be formed from a semiconductor material such as silicon, for coupling one or more semiconductor die to a printed circuit board (PCB). A plurality of integrated circuits (ICs) or other semiconductor dies, which may be heterogeneous technologies, may be mounted on the interposer.
As the demand for artificial intelligence (AI), high-speed computation (HPC), and powerful computing continues to grow, there is an increasing need to enhance the number of transistors in a single package. However, traditional materials like silicon, commonly used for interposers, are encountering limitations. Insulating substrates, such as glass substrates and dielectric substrates, can offer numerous advantages, including exceptional flatness, high thermal stability, and rigidity. These attributes enable further miniaturization and integration of transistors when compared to silicon substrates.
However, processing using insulating interposer type substrates can present challenges, especially in the context of achieving 2.5D or 3D packaging through the Through-Glass-Via (TGV) technique.
Further, many devices on one or more of the semiconductor die may cause electrical noise and/or create electromagnetic (“EM”) interference by emitting EM emissions. Additionally, through insulator via (TIV) noise coupling in an insulating or glass interposer can cause degradation of the signal quality. Systems based on through insulator vias (TIV) have been determined to be vulnerable to noise coupling because the low loss of the insulator or glass composition interposer, which cannot attenuate the coupling noise.
In an embodiment, the present invention provides a through insulator via (TIV) that includes continuous and complete shielding of the electrically conductive features of the through insulator via (TIV) that provides for signal transmission. For example, a coaxial arrangement is provided in which ground shielding is positioned around the signal via. The ground shielding is continuous from a first end of the through insulator via (TIV) to the second end of the through insulator via (TIV). The ground shielding can connect to electrically conductive features on both ends of the through insulator via (TIV). The continuous ground shielding can provide a continuous ground return path for uniform impedance. The coaxial geometry of the ground shielding around the signal, as well as the continuous nature of the ground shielding along the entire height of the signal via, provides a through insulator via (TIV) that can overcome the disadvantages of noise through insulator vias (TIVs) that do not include the continuous shielding of the designs described herein.
In an embodiment, a device is provided that includes two adjacent chiplets separated by an insulating region. A through insulator via (TIV) is present in the insulating regions separating the two adjacent chiplets. The through insulator via (TIV) includes a coaxial arrangement of a signal via having ground shielding about a perimeter of the signal via. The ground shielding is continuous from a first face of the insulating region to a second face of the insulating region.
In an embodiment, the signal via is separated from the ground shielding by a via insulating material. In some embodiments, the insulating region has a first dielectric composition that is different from a composition of a second dielectric composition for the via insulating material.
In some embodiments, the through insulator via (TIV) is connected to a bridge chip that is present on the at least two chiplets.
In some embodiments, the through insulator via (TIV) is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region. The redistribution layer being may be in electrical communication with one of the at least two chiplets.
In some embodiments, the semiconductor device includes two stacked levels of chiplets and the through insulator via (TIV) is a skip via.
In some embodiments, the through insulator via (TIV) with the ground shielding may be integrated with a power via that does not include ground shielding.
In another embodiment, semiconductor device is provided that includes at least two chiplets separated by an insulating region and a through insulator via (TIV) extending through the insulating region. The through insulator via (TIV) may include a coaxial arrangement of a signal via of a first metal composition having ground shielding of a second metal composition about a perimeter of the signal via. In some embodiments, the first metal composition is different than the second metal composition. In some embodiments, the ground shielding is continuous from a first face of the insulating region to a second face of the insulating region.
In some embodiments, the signal via is separated from the ground shielding by a via insulating material. In some embodiments, the insulating region has a composition that is different from the composition of the via insulating material.
In some embodiments, the through insulator via (TIV) is connected to a bridge chip that is present on the at least two chiplets. In some embodiments, the through insulator via is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region. In some embodiments, the redistribution layer is in electrical communication with one of the at least two chiplets.
In some embodiments, the semiconductor device includes a plurality of chiplets that are present on different levels. In some embodiments, the different levels can include two stacked levels of chiplets, and the through insulator via (TIV) is a skip via.
In some embodiments, the through insulator via (TIV) having the ground shielding may be integrated with a power via that does not include ground shielding.
In another embodiment, a semiconductor device is provided that includes at least two chiplets separated by an insulating region. The semiconductor device also includes a through insulator via (TIV) extending through the insulating region. The through insulator via (TIV) includes a coaxial arrangement of a signal via having ground shielding about a perimeter of the signal via. In some embodiments, the signal via and the ground shield each have a same metal composition. The ground shielding is continuous from a first face of the insulating region to a second face of the insulating region.
In an embodiment, the signal via is separated from the ground shielding by a via insulating material. In an embodiment, the insulating region has a composition that is different from the composition of the via insulating material.
In an embodiment, the through insulator via is connected to a bridge chip that is present on the at least two chiplets.
In some embodiments, the through insulator via is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region. The redistribution layer is in in electrical communication with one of the at least two chiplets.
In some embodiments, the at least two chiplets including a plurality of chiplets that are present on different levels. In an embodiment, the different levels can include two stacked levels of chiplets and the through insulator via is a skip via.
In an embodiment, the at least two chiplets includes two stacked levels of chiplets and the through insulator via is a skip via.
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures. The term “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In an embodiment, the present invention provides a through insulator via (TIV) that includes continuous and complete shielding of the electrically conductive signal transmission features of the through insulator via (TIV).
In accordance with some embodiments, the ground shielding is continuous from one end of the through insulator via to the second end of the through insulator via (TIV). The ground shielding can connect to electrically conductive features on both ends of the through insulator via (TIV). This can provide a continuous ground return path for uniform impedance. The coaxial geometry of the ground shielding around the signal via, as well as the continuous nature of the ground shielding along the entire height of the signal via, provides a through insulator via (TIV) that can overcome the disadvantages of noise coupling in prior through insulator vias having insufficient shielding.
A “through insulator via (TIV)” is a vertical metal containing via passing completely through an insulating material. In the embodiment depicted in
The insulating material that the through silicon via (TIV) is positioned through may be a glass type dielectric. However, the insulating material that the through insulator via (TIV) extends through is not intended to be limited to only glass type compositions, as any insulating material through which a via can extend is suitable for providing the insulating material that the through silicon via (TIV) is present in. For example, the insulator that the through silicon via (TIV) extends through, e.g., the insulator composition for the material that is present in the insulating region 5, may be aluminosilicate glass, borosilicate glass, fused silica or a combination thereof. Other insulators may include oxides, nitrides or oxynitride containing materials.
The through insulator via 10 includes a signal via 9 and ground shielding 8 in a coaxial arrangement. The coaxial arrangement includes at least two concentric conductors separated by an insulator. The signal via 9 may be the centrally positioned conductor, and the ground shielding 8 may surround, e.g., encircle, the signal via 9. The signal via 9 and the ground shielding 8 may have the composition of an electrically conductive material. For example, the signal via 9 and the ground shielding 8 may each have the composition of any elemental metal, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W) and combinations thereof. In some embodiments, the signal via 9 and the ground shielding 8 may have the same composition metal. In other embodiments, the signal via 9 and the ground shielding 8 have different composition metals.
A via insulating material 7 may be present between and separating the signal via 9 and the ground shielding 8. The via insulating material 7 may have a dielectric composition. For example, the via insulating material 7 may have a composition that includes an oxide, e.g., silicon oxide, a nitride, e.g., silicon nitride, or an oxynitride material. In some examples, the via insulating material 7 can have a different composition than the insulating material composition for the material of the insulating region 5.
In some embodiments, the ground shielding 8 is continuous from a first face F1 of the insulating region 5 to a second face F2 of the insulating region 5. In some examples, the term “continuous” when describing the ground shielding means that that the shielding material layer is completely free of breaks or openings along an entirety of the height of ground shielding 8 that extends from the first face F1 to the second face F2 of the insulating region 5.
The first face F1 and the second face F2 of the insulating region 5 can included an interface to electrically conductive features of a bridge chip 40, e.g., stacked bridge chip. A bridge chip 40 includes circuitry, as well as active devices, that can provide for electrical communication between the first chiplet 20 and the second chiplet 30.
In some embodiments, the through insulator via (TIV) 10 having the coaxial arrangement of the signal via 9 and the ground shielding 8 may be integrated with a power via 11 that does not include ground shielding.
In some embodiments, the interconnects of metal between the first chiplet 20 the bridge chip 40 and the second chiplet 30, as well as the through insulator via 10, provides for electrical communication between the elements. In some embodiments, the interconnects at the interfaces of the bridge chip 40, the first chiplet 20 and the second chiplet 30 are provided by redistribution layers 35. Redistribution layers (RDLs) are the metal interconnects that electrically connect one part of the semiconductor package to another. In one example, the through insulator via (TIV) 10 is in electrical communication with a redistribution layer 35 on the face F1 of the insulating region 5. In one example, the redistribution layer 35 is in electrical communication with the first chiplet 20 and the second chiplet 30.
The structures depicted in
The chiplet carrier 21 provides support for the chiplet 20 through processing that can include layer transfer. The chiplet carrier 21 may be a silicon substrate. However, other substrate types may also be applicable for the chiplet carrier 21. The chiplet carrier 21 may be engaged to the chiplet backside power distribution network level 23 through the chiplet bonding layer 22, which can be an oxide containing layer. Backside power delivery refers to the technique of routing power supply lines on the backside of a semiconductor chip or integrated circuit (IC) instead of the traditional frontside. The chiplet backside power distribution network level 23 may include a plurality of metal lines and vias formed through interlevel dielectric layers.
The chiplet active device level 24 is present on the chiplet backside power distribution network 23. The chiplet active device level 24 may be formed using front end of the line (FEOL) processing. The chiplet active device level 24 may include the active devices for the chiplet 20. The term “active device” refers to a devices that include, but are not limited to transistors, resistors and capacitors. In some embodiments, the active devices are formed on a semiconductor substrate 27 that is integrated into the first chiplet 20. Middle of the line (MOL) processing may be employed to form frontside contacts to the active devices in the chiplet active device level 24. The chiplet back end of the line level 25 is present on the chiplet active device level 24.
The chiplet back end of the line (BEOL) level 25 includes metal lines and vias that may be in electrical communication with the frontside contacts to the active devices.
The process sequence that is used for forming the metal lines and vias is a back end of the line (BEOL) process. In some embodiments, an interlevel dielectric layer is first deposited and then etched to form via openings to the underlying contacts. Thereafter, the via openings are then filled with an electrically conductive material, such as a metal, e.g., copper, to provide vias. Thereafter, a deposition, pattern and fill sequence is repeated to forms lines. This may be referred to as a single damascene method for forming lines and vias. However, dual damascene sequences are also applicable. The sequence of deposition, pattern and etch are repeated as many times as needed to form each level of metal lines and vias. Still referring to
The bridge chip 40 includes one side for interfacing with the first chiplet 20, and a second side for interfacing with the second chiplet 30. An active device region may be present on each side of the bridge chip active device level 44 to communicate with the first chiplet 20 and the second chiplet 30 that corresponds to the side that the active device region is present on.
Still referring to
In a following step, the electrically conductive features of the bridge chip redistribution layer 65 may be bonded to the contacts of the bridge chip connection layer 51. Bonding may be provided by thermal bonding processes. In a following step, a dielectric material fill may be deposited, such as an oxide, nitride or oxynitride. The deposition process can include chemical vapor deposition, but this is only one example of a deposition process that is suitable for this stage of the process flow. A planarization process may be applied to dielectric material fill 52, such as chemical mechanical planarization. The planarization process may remove the bridge chip carrier 41 and the bridge chip bonding layer 42.
In a following process sequence, the structure depicted in
In a following process sequence, the structure depicted in
It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
Having described preferred embodiments of coaxial through insulator via between chiplets (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
