Claims
- 1. A multichip package comprising:
- a substrate including a plurality of conductive traces and flexible leads connected to outer ends of at least some of said conductive traces adjacent the periphery of said flexible substrate, said substrate including conductive terminals accessible at a surface thereof connected to at least some of said traces;
- a first microelectronic element having a front face including contacts and a back face, the front face of said first microelectronic element confronting said flexible substrate;
- a second microelectronic element larger than said first microelectronic element, said second microelectronic element having a front face including contacts, said second microelectronic element overlying said first microelectronic element with said front face of said second microelectronic element facing toward said substrate,
- a compliant element disposed alongside said first microelectronic element between said second microelectronic element and said substrate,
- wherein said flexible leads are connected to said second microelectronic element and at least some of said traces are connected to said first microelectronic element for electrically interconnecting said first and second microelectronic elements with one another and with said terminals.
- 2. A package as claimed in claim 1 wherein said compliant element includes a compliant layer extending between said back face of said first microelectronic element and said front face of said first microelectronic element.
- 3. A package as claimed in claim 2 wherein said substrate is flexible.
- 4. A package as claimed in claim 3, wherein said flexible substrate includes an interior bond window and said conductive traces have inner ends extending at least partially across said interior bond window.
- 5. A package as claimed in claim 4, wherein the inner ends of said conductive traces include flexible leads.
- 6. A package as claimed in claim 4, wherein the contacts of said first microelectronic element are aligned with said interior bond window.
- 7. A package as claimed in claim 3, wherein said flexible substrate includes a central region bounded and defined by said interior bond window, and wherein said first microelectronic element overlies said central region of said flexible substrate.
- 8. A package as claimed in claim 7, wherein the front face of said first microelectronic element includes a central portion and a peripheral portion surrounding said central portion, said contacts of said first microelectronic element being disposed in said peripheral portion of said front face.
- 9. A package as claimed in claim 8, wherein the central portion of said first microelectronic element is in contact with the central region of said flexible substrate.
- 10. A package as claimed in claim 3, wherein said first microelectronic element is a memory chip.
- 11. A package as claimed in claim 10, wherein said second microelectronic element is selected from the group consisting of microprocessors, microcontrollers, and application specific integrated circuits.
- 12. A package as claimed in claim 3 wherein said compliant element includes compliant encapsulant surrounding said flexible leads.
- 13. A package as claimed in claim 12, wherein said compliant element extends beyond the periphery of said package to provide a compliant bumper surrounding said package.
- 14. A package as claimed in claim 3, wherein said compliant element includes a substantially continuous compliant pad which completely covers said first microelectronic element.
- 15. A package as claimed in claim 3, wherein the front face of said second microelectronic element includes a central portion and a peripheral portion surrounding said central portion, said contacts of said second microelectronic element being disposed in said peripheral portion of said front face.
- 16. A package as claimed in claim 15, wherein the central portion of said second microelectronic element is in contact with said compliant element.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims benefit of U.S. Provisional Patent Application Serial No. 60/033,352 filed Dec. 13, 1996, the disclosure of which is incorporated by reference herein. This application is also a divisional of U.S. patent application Ser. No. 08/989,710 filed Dec. 12, 1997, now U.S. Pat. No. 6,054,337, the benefit of which is claimed pursuant to 35 U.S.C. Section 120.
US Referenced Citations (14)
Divisions (1)
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Number |
Date |
Country |
Parent |
989710 |
Dec 1997 |
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