Patent Application
20050170609
The invention generally relates to forming electrical interconnections in a stacked die device.
There are a number of scenarios where a stacked die approach is of value. For example, a MEMS die may be conductively connected to a circuit die. Such die may require both electrical and mechanical interconnections. Parasitic capacitance and resistance problems also should be addressed in such situations.
Thus, a stacked die device may include two or more wafers that are bonded to one another. Each wafer may include micromachined components and/or integrated circuit components. Generally speaking, the various components on the wafers are fragile, and many of the components can be damaged by high temperatures. In essence, then, there is a “thermal budget” for the stacked die device that is determined by the most temperature-sensitive feature.
Embodiments of the present invention provide for electrically interconnecting wafers in stacked wafer devices within the thermal budgets of the stacked wafer devices. Specifically, an electrode is formed through a first wafer from a component on a front side of the first wafer to a back side of the first wafer. A first electrically conductive interface is formed in contact with an exposed portion of the electrode on the back side of the first wafer. The first electrically conductive interface is conductively bonded with a second electrically conductive interface on a second wafer under pressure at a temperature below the thermal budget of the stacked wafer device. Such a temperature is generally well below the melting point of at least one of the electrically conductive interfaces. Depending on the substances in the first and second electrically conductive interfaces, such conductive bonding can occur by way of interdiffusion, thermocompression, or other mechanism. In some embodiments, the conductive bonding may be facilitated or enabled by performing the conductive bonding in an ambient (e.g., air or other gas) or in a vacuum. The conductive bonding produces an electrically conductive interconnection between the wafers, and, more particularly, from the component on the front side of the first wafer to the second electrically conductive interface on the second wafer, without damaging features on either wafer. This electrical connection allows the wafers to operate as one integrated device.
In accordance with one aspect of the invention there is provided a method for electrically interconnecting wafer devices. The method involves forming an electrode through a first wafer from a component on a front side of the first wafer to a back side of the first wafer; forming a first electrically conductive interface in contact with an exposed portion of the electrode on the back side of the first wafer; and conductively bonding the first electrically conductive interface with a second electrically conductive interface on a second wafer under pressure at a temperature below the melting point of at least one of the electrically conductive interfaces.
The first and second interfaces may include gold (Au). The first and second interfaces may include aluminum-copper (AlCu). The first and second interfaces may include platinum (Pt) with or without an adhesive underlayer. One of the interfaces may include silicon (Si) and the other may include platinum (Pt) (with or without an adhesive underlayer). One of the interfaces may include doped polysilicon and the other may include a solderable metal.
In certain embodiments of the invention, the conductive bonding is performed in a vacuum. The conductive bond may be formed through interdiffusion, thermocompression, or other mechanism. The electrode may be formed by filling a lined through-wafer via in the first wafer with an electrically conductive material. The first wafer may be a MEMS wafer, and the second wafer may be an integrated circuit wafer.
In accordance with another aspect of the invention there is provided an apparatus comprising a first wafer having (1) an electrode passing through the first wafer from a component on a top side to a bottom side, and (2) a first electrically conductive interface on the bottom side of the first wafer in contact with an exposed portion of the electrode; and a second wafer having a second electrically conductive interface conductively bonded with the first electrically conductive interface under pressure at a temperature below the melting point of at least one of the electrically conductive interfaces.
The first and second interfaces may include gold (Au). The first and second interfaces may include aluminum-copper (AlCu). The first and second interfaces may include platinum (Pt) with or without an adhesive underlayer. One of the interfaces may include silicon (Si) and the other may include platinum (Pt) (with or without an adhesive underlayer). One of the interfaces may include doped polysilicon and the other may include a solderable metal.
The conductive bond may be formed through interdiffusion, thermocompression, or other mechanism. The first wafer may be a MEMS wafer, and the second wafer may be an integrated circuit wafer.
The foregoing and advantages of the invention will be appreciated more fully from the following further description thereof with reference to the accompanying drawings wherein:
Embodiments of the present invention provide for electrically interconnecting wafers in stacked wafer devices within the thermal budgets of the stacked wafer devices. Specifically, an electrode is formed through a first wafer from a component on a front side of the first wafer to a back side of the first wafer. A first electrically conductive interface is formed in contact with an exposed portion of the electrode on the back side of the first wafer. The first electrically conductive interface is typically a raised structure that protrudes from the back side of the first wafer. The first electrically conductive interface is conductively bonded with a second electrically conductive interface on a second wafer under pressure at a temperature below the thermal budget of the stacked wafer device. The process temperature is generally well below the melting point of at least one of the electrically conductive interfaces. Depending on the substances in the first and second electrically conductive interfaces, such conductive bonding can occur by way of interdiffusion, thermocompression, or other mechanism. In some embodiments, the conductive bonding may be facilitated or enabled by performing the conductive bonding in an ambient (e.g., air or other gas) or in a vacuum. The conductive bonding produces an electrically conductive interconnection between the wafers, and, more particularly, from the component on the front side of the first wafer to the second electrically conductive interface on the second wafer, without damaging features on either wafer. This electrical connection allows the wafers to operate as one integrated device.
In a typical embodiment of the present invention, the first wafer includes an opening (referred to hereinafter as a “through-wafer via”). The through-wafer via is typically lined with one or more insulating materials. The electrode passes through the through-wafer via. The electrode may be formed by filling the through-wafer via with an electrically conductive material, such as silicon, polysilicon, or metal. The insulating lining, if present, electrically isolates the electrode from the wafer.
The temperature and other parameters selected for a particular embodiment of the invention may depend on a number of factors, including, but not limited to, the materials in the electrically conductive interfaces, the amount of pressure applied, the size of the features in contact, and whether the conductive bonding is performed in an ambient (e.g., air or another gas) or in a vacuum. Typically, conductive bonding is performed within the temperature range of about 280 C to 500 C. Generally speaking, increasing bond pressure and/or decreasing the size of the features in contact and/or using a vacuum during bonding could improve conductive bonding.
In embodiments of invention in which a metal, such as platinum, gold, or aluminum-copper (AlCu), is deposited as an electrically conductive interface onto a silicon or polysilicon electrode, it may be advantageous to process the exposed portion of the electrode prior to deposition of the metal, for example, by sputter etching, in order to facilitate adhesion and electrical connectivity. Alternatively, or additionally, an adhesion material, such as titanium-tungsten or titanium, may be deposited as an underlayer.
In a first exemplary embodiment, Wafer 1 has a lined through-wafer via filled with doped polysilicon. Platinum is deposited and patterned onto the exposed polysilicon in the via on the backside of the wafer. Wafer 2 has a conductive polysilicon interconnect. The platinum of Wafer 1 is brought into contact with the polysilicon interconnect on Wafer 2 and heated above about 280 C but below about 450 C. The two wafers are conductively bonded through the formation of platinum-silicide at the platinum-polysilicon interface on both wafers.
In a second exemplary embodiment, Wafer 1 has a lined through-wafer via filled with doped polysilicon. A solderable metal, such as platinum or gold, is deposited and patterned onto the exposed polysilicon in the via on the backside of the wafer. Wafer 2 has solder bumps on the interconnect bond pads. Wafer 1 and Wafer 2 are conductively bonded by aligning the solderable metal on Wafer 1 to the solder bumps on wafer 2 and applying pressure and temperature less than about 450 C.
In a third exemplary embodiment, Wafer 1 has a lined through-wafer via filled with metal. Metal is deposited and patterned onto the exposed metal in the via on the backside of the wafer, forming conductive pads on the metal filled vias. The metal pads on Wafer 1 are aligned to metal bond pads on Wafer 2 and a metal-metal conductive bond is made by applying pressure and temperature less than about 450 C.
In a fourth exemplary embodiment, Wafer 1 has an electrode passing through a through-wafer via and an electrically conductive interface, formed from a metal such as gold or platinum, in contact with an exposed portion of the electrode on the back side of the wafer. Wafer 2 includes an electrically conductive interface, also formed from gold or platinum. The electrically conductive interfaces are conductively bonded at a temperature of approximately 500 C.
In a fifth exemplary embodiment, Wafer 1 has an electrode passing through a through-wafer via and an electrically conductive interface, formed from aluminum-copper (possibly with an adhesive underlayer of titanium-tungsten, titanium, or other material), in contact with an exposed portion of the electrode on the back side of the wafer. Wafer 2 includes an electrically conductive interface, also formed from aluminum-copper (possibly with an adhesive underlayer of titanium-tungsten, titanium, or other material). The electrically conductive interfaces are conductively bonded at a temperature of approximately 450 C-500 C.
In a sixth exemplary embodiment, Wafer 1 has an electrode passing through a through-wafer via and an electrically conductive interface, formed from platinum with an underlayer of titanium-tungsten (TiW), in contact with an exposed portion of the electrode on the back side of the wafer. Wafer 2 includes an electrically conductive interface, also formed from platinum with an underlayer of titanium-tungsten. The electrically conductive interfaces are conductively bonded at a temperature of approximately 450 C.
In a seventh exemplary embodiment, Wafer 1 has an electrode passing through a through-wafer via and an electrically conductive interface, formed from platinum (possibly with an adhesive underlayer of titanium-tungsten, titanium, or other material), in contact with an exposed portion of the electrode on the back side of the wafer. Wafer 2 includes an electrically conductive interface formed from silicon or polysilicon. The electrically conductive interfaces are conductively bonded at a temperature of approximately 450 C.
The exemplary embodiments discussed above demonstrate some possible combinations of materials, process temperatures, and process pressures for conductively bonding wafer devices. It should be apparent to a skilled artisan that other materials and process temperatures may also be used. For example, it may be possible to conductively bond materials at lower temperatures, particularly if the conductive bonding is performed at higher pressures and/or in a vacuum. Conversely, it may be possible to conductively bond materials at higher temperatures.
While the exemplary embodiments discussed above demonstrate some electrically conductive interfaces composed of one or two material layers, it may be possible to have electrically conductive interfaces with more than two material layers. Extra layers may be necessary or desirable, for example, to aid in bonding.
It is well known that aluminum-copper (AlCu) generally has a native oxide. Conventional wisdom has held that this native oxide will prevent thermocompression bonding of aluminum to aluminum or AlCu to AlCu. However, AlCu to AlCu bonds were successfully formed in bonding tests at a temperature 450 C to 500 C and a bond pressure of 2-6 Bar or higher, both in an ambient and in a vacuum. In fact, leaving the as-deposited AlCu surface untreated appeared to produce a better result than if the AlCu surface was chemically or physically treated prior to bonding, although this could be due in part to constraints of the particular test procedure (e.g., the time between treatment and bonding).
It is also well known that aluminum-copper can have different proportions of aluminum and copper. Aluminum-copper with approximately one percent copper has been used successfully in bonding tests, although other percentages may also provide sufficient bonding.
To improve device performance, the electrical resistance and parasitic capacitance of the interconnects formed by the conductively filled via should be minimized. To that end, embodiments identify materials and processing steps that produce a low resistance via fill, thus enabling a good electrical connection with a via dimensioned to minimize parasitic capacitance. For example, process steps may fill the lined through-wafer via with a conductive material, such as doped polysilicon, deposited metal, or chemical vapor deposition (CVD) metal (e.g., tungsten or platinum). Related U.S. patent application Ser. No. 10/827,680 entitled “MEMS DEVICE WITH CONDUCTIVE PATH THROUGH SUBSTRATE,” which was incorporated by reference above, describes a number of techniques for forming filled through-wafer vias, including filling an etched through-wafer via and backgrinding a filled cavity. The present invention is not limited to any particular technique for forming the through-wafer via.
It should be noted that the specific temperatures recited above are exemplary for specific embodiments of the invention. Those skilled in the art should understand that other temperatures can be used to accomplish similar goals for different devices. Those skilled in the art should also recognize that electrical interconnections, formed as described above, can also act as mechanical interconnections for the wafers.
Although the above discussion discloses various exemplary embodiments of the invention, it should be apparent that those skilled in the art can make various modifications that will achieve some of the advantages of the invention without departing from the true scope of the invention.
This patent application is a continuation-in-part of, and thus claims priority from, U.S. patent application Ser. No. 10/737,231 entitled “SEMICONDUCTOR ASSEMBLY WITH CONDUCTIVE RIM AND METHOD OF PRODUCING THE SAME,” which was filed Dec. 15, 2003 in the names of Susan A. Alie, Michael Judy, Bruce K. Wachtmann, and David Kneedler, and is also a continuation-in-part of, and thus claims priority from U.S. patent application Ser. No. 10/827,680 entitled “MEMS DEVICE WITH CONDUCTIVE PATH THROUGH SUBSTRATE,” which was filed Apr. 19, 2004 in the names of Kieran P. Harney, Lawrence E. Felton, Thomas Kieran Nunan, Susan A. Alie, and Bruce K. Wachtmann. This patent application also claims priority from U.S. Provisional Patent Application No. 60/542,261 entitled “CONDUCTIVE BOND FOR THROUGH-WAFER INTERCONNECT,” which was filed Feb. 5, 2004 in the names of Susan A. Alie, Bruce K. Wachtmann, Lawrence E. Felton, and Changhan Yun. The above patent applications are hereby incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 60542261 | Feb 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10737231 | Dec 2003 | US |
| Child | 11050469 | Feb 2005 | US |
| Parent | 10827680 | Apr 2004 | US |
| Child | 11050469 | Feb 2005 | US |
