Patent Application
20250006673
For integrated circuit design and fabrication, the need to improve performance and lower costs are constant challenges. As transistors continue to shrink in size and are used in high-power and high-density semiconductors systems, for example, package-on-package structures, it is becoming increasingly difficult and costly to provide effective thermal management for such high-power and high-density semiconductors systems.
Electrical resistance is the main reason for the generation of heat in semiconductor devices, and high-power and high-density semiconductors systems provide less surface area to dissipate the generated heat. When a semiconductor system overheats, the devices and components with thermal ratings less than the generated temperature may be damaged. To avoid thermally-induced damage, the heat generated by the semiconductor system needs to be dissipated to its surrounding environment by a thermal transfer system.
Heat sinks are commonly used, as part of a thermal transfer system for high-power and high-density semiconductor systems, to provide additional surface area for heat dissipation. The use of heat sinks in combination with other thermal management devices, such as cooling fans, can provide the necessary heat dissipation rates for most high-power and high-density semiconductor systems. In most conventional thermal transfer systems remove the generated heat by the semiconductor system from the top of the package structure, i.e., coupling the heat sink to the package lid. For package-on-package structures, it may be difficult to provide thermal pathways that remove the generated heat from embedded logic devices to heat sinks positioned above the package structures or to other parts of the printed circuit boards.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the present disclosure. The dimensions of the various features or elements may be arbitrarily expanded or reduced for clarity. In the following description, various aspects of the present disclosure are described with reference to the following drawings, in which:
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details, and aspects in which the present disclosure may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Various aspects are provided for devices, and various aspects are provided for methods. It will be understood that the basic properties of the devices also hold for the methods and vice versa. Other aspects may be utilized and structural, and logical changes may be made without departing from the scope of the present disclosure. The various aspects are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects.
As set forth in this disclosure, the present cooling elements and methodology are intended to remove heat from an embedded logic package in a semiconductor package-on-package (POP) structure to increase the performance of the POP structure. The present cooling elements draw the heat downward from the logic package to the underlying package substrate and printed circuit board. From the use of the present cooling methodology, the performance of the logic package, as well as the POP structure generally, will increase as optimal temperature conditions are better maintained.
In a further aspect, the present cooling elements may be made of a heat-conductive material, e.g., copper, aluminum, and other metals. The present cooling element may include one or more elements, such as a heat transfer layer or strand, that are formed in the logic package, a plurality of thermal vias that are formed in the package substrate and/or printed circuit board. If copper is used, for example, as the heat-conductive material, the thermal vias may be filled by an electroplating process or using a semi-solid paste through a paste printing process that employs pressure and heat. The semi-solid paste may be used to fill a thermal via opening and it will be sintered at a required temperature. Thereafter, upon cooling, the semi-solid paste will solidify to form an element of the heat conducting pathway.
Accordingly, the present disclosure provides a package-on-package structure having a package substrate with a logic package disposed on the package substrate, and heat conductive pathways being provided in the package-on-package structure for removing heat from the logic package. In an aspect, the heat conductive pathways enable a downward transfer of the heat generated by the logic package toward the package substrate and a printed circuit board (PCB). In another aspect, the heat conducting pathways may include a heat transfer layer formed proximally to a bottom surface of the logic package. In a further aspect, the heat conducting pathways may include one or more thermal vias in the package substrate and PCB.
The present disclosure is also directed to a method that includes providing a logic package, forming heat conductive pathways in a package substrate and a PCB, and disposing the logic package and the package substrate over the PCB. In an aspect, the logic package may be thermally coupled to the package substrate and PCB, by way of the heat conductive pathways, and a thermal differential directs the heat generated by the logic package downward along the heat conductive pathways toward the package substrate and PCB. In another aspect, the method includes disposing a second package over the logic package to form a package-on-package structure. In yet another aspect, the method includes forming a heat transfer layer proximal to a bottom surface of the logic package to facilitate the transfer of heat generated by the logic package and forming at least one metal via positioned in the package substrate, as elements of the heat conductive pathways.
The present disclosure is further directed to an embedded package cooling system having heat conductive pathways that are thermally coupled to a logic package, which is embedded in a package-on-package structure and disposed on a package substrate, for heat dissipation and enables a downward transfer of heat generated by the logic package toward the package substrate and PCB. In another aspect, the embedded package cooling system includes a heat transfer layer formed proximally to a bottom surface of the logic package and a plurality of metal vias formed in the package substrate as elements of the heat conductive pathways.
The technical advantages of the present disclosure include, but are not limited to:
To more readily understand and put into practical effect the present structural elements and method for cooling an embedded logic package, which may be used for improving the performance of package-on-package structures, particular aspects will now be described by way of examples provided in the drawings that are not intended as limitations. The advantages and features of the aspects herein disclosed will be apparent through reference to the following descriptions relating to the accompanying drawings. Furthermore, it is to be understood that the features of the various aspects described herein are not mutually exclusive and can exist in various combinations and permutations. For the sake of brevity, duplicate descriptions of features and properties may be omitted.
In
In an alternative aspect, which is not shown, a heat transfer layer may be positioned near the top of a logic package in a package-on-package structure. In this aspect, the heat transfer layer may be thermally coupled to a second package (non-logic package) by a non-metal thermal via (e.g., a silicon via) at the top of the logic package. The heat conductive pathways may be formed that lead from the second package in the package-on-package structure to direct the heat downward toward a package substrate having substrate thermal vias and further downward toward to a PCB having PCB thermal vias.
In another aspect, if there is a space between the logic package 201 and the package substrate 202, an underfilling 210 may be used to fill the space, which may also provide an additional heat conductive pathway 205 for heat dissipation. In a further aspect, a plurality of solder balls 209 may provide further heat conductive pathways 205 to the print circuit board 203 (not shown).
In
As shown in
The operation 601 may be directed to providing a package substrate and PCB.
The operation 602 may be directed to drilling openings for thermal vias in the package substrate/PCB. The size of the drill openings may be approximately 4 mm.
The operation 603 may be directed to filling the thermal vias with copper or other metal using electroplating and/or a semi-solid paste, e.g., Cu paste LTV 54M. It should be understood that other conventional methods/processes may be used to form the thermal vias. The filling process may be from the top or below.
The operation 604 may be directed to removing the excess copper/metal using mechanical or chemical methods.
The operation 605 may be directed to applying pressure and heat to the package substrate/PCB followed by a cleaning process. For example, the pressure may be 1.0 MT for 40 minutes at a curing temperature of 225° C.
The operation 606 may be directed to forming a package-on-package structure with heat conductive pathways on the PCB.
In another aspect, the present cooling methodology may be able to reduce z-direction warpage with the use of thermal vias in the printed circuit board (PCB). For simulations using a plurality of thermal vias (e.g., 52 vias) having a similar structure to that shown in
It will be understood that any property described herein for a particular package-on-package structure and cooling method for embedded logic packages may also hold for any other package-on-package structure using the cooling methodology described herein. It will also be understood that any property described herein for a specific method may hold for any of the methods described herein. Furthermore, it will be understood that for any of the heat conductive pathways and the methods described herein, not necessarily all the components or operations described will be shown in the accompanying drawings or method, but only some (not all) components or operations may be disclosed.
To more readily understand and put into practical effect the present semiconductor carrier platforms and thermal stability layers, they will now be described by way of examples. For the sake of brevity, duplicate descriptions of features and properties may be omitted.
Example 1 provides a package-on-package structure including a package substrate, a logic package disposed on the package substrate, and heat conductive pathways provided in the package-on-package structure and coupled to the logic package for removing heat from the logic package, for which the heat conductive pathways enable a downward transfer of heat generated by the logic package towards the package substrate and a printed circuit board, for which the heat conductive pathways enable a downward transfer of heat generated by the logic package towards the printed circuit board.
Example 2 may include the package-on-package structure of example 1 and/or any other example disclosed herein, for which the heat conducting pathways include a heat transfer layer formed proximally to a bottom surface of the logic package.
Example 3 may include the package-on-package structure of example 1 and/or any other example disclosed herein, for which the heat conducting pathways include at least one substrate thermal via in the package substrate and the logic package is thermally coupled to the at least one substrate thermal via.
Example 4 may include the package-on-package structure of example 3 and/or any other example disclosed herein, for which the heat conducting pathways comprise at least one PCB thermal via in the PCB and the logic package is thermally coupled to the at least one PCB thermal via.
Example 5 may include the package-on-package structure of example 3 and/or any other example disclosed herein, for which the at least one substrate thermal via is a through-hole.
Example 6 may include the package-on-package structure of example 4 and/or any other example disclosed herein, for which the at least one PCB thermal via is a through-hole via, blind via, or buried via.
Example 7 may include the package-on-package structure of example 6 and/or any other example disclosed herein, for which the least one PCB thermal via is a buried via wherein the buried via is coupled to a plurality of micro vias.
Example 8 may include the package-on-package structure of example 4 and/or any other example disclosed herein, for which the at least one PCB thermal via is formed of a copper material.
Example 9 may include the package-on-package structure of example 3 and/or any other example disclosed herein, for which the at least one PCB thermal via provides a ground connection.
Example 10 may include the package-on-package structure of example 1 and/or any other example disclosed herein, for which the logic package is embedded in the package-on-package structure.
Example 11 provides a method that includes providing a logic package, forming heat conductive pathways in a package substrate, forming heat conductive pathways in a PCB, disposing the logic package over the package substrate, disposing a second package over the logic package to form a package-on-package structure, disposing the logic package and package substrate over the PCB, for which the logic package is thermally coupled to the package substrate and the PCB, and providing a thermal differential that directs heat generated by the logic package downward along the heat conductive pathways toward the package substrate and the PCB.
Example 12 may include the method of example 11 and/or any other example disclosed herein, for which the forming heat conductive pathways further includes forming a heat transfer layer proximal to a bottom surface of the logic package, for which the heat transfer layer facilitates the transfer of heat generated by the logic package.
Example 13 may include the method of example 11 and/or any other example disclosed herein, for which the forming heat conductive pathways further includes forming at least one metal via in the package substrate.
Example 14 may include the method of example 13 and/or any other example disclosed herein, for which the forming at least one substrate thermal via in the package substrate further includes drilling a substrate via opening in the package substrate and filling the substrate via opening with copper.
Example 15 may include the method of example 13 and/or any other example disclosed herein, for which the forming at least one PCB thermal via in the PCB further comprises drilling a PCB via opening in the PCB and filling the PCB via opening with copper.
Example 16 may include the method of example 14 and/or any other example disclosed herein, for which the heat conductive pathway further includes forming a plurality of micro vias in the package substrate that are thermally coupled to the at least one PCB thermal via.
Example 17 provides a package cooling system including heat conductive pathways that are thermally coupled to a logic package for heat dissipation, for which the embedded logic package is embedded in a package-on-package structure and disposed on a package substrate and a printed circuit board coupled to the heat conductive pathways that enable a downward transfer of heat generated by the logic package toward the package substrate and the PCB.
Example 18 may include the package cooling system of example 17 and/or any other example disclosed herein, for which the heat conductive pathways further include a heat transfer layer formed proximally to a bottom surface of the logic package.
Example 19 may include the package cooling system of example 17 and/or any other example disclosed herein, for which the heat conductive pathways further include a substrate thermal via formed in the package substrate and a PCB thermal via formed in the PCB.
Example 20 may include the package cooling system of example 19 and/or any other example disclosed herein, for which the heat conductive pathways further include a plurality of micro vias in the package substrate that are thermally coupled to the PCB thermal via in the PCB.
The term “comprising” shall be understood to have a broad meaning similar to the term “including” and will be understood to imply the inclusion of a stated integer or operation or group of integers or operations but not the exclusion of any other integer or operation or group of integers or operations. This definition also applies to variations on the term “comprising” such as “comprise” and “comprises”.
The term “coupled” (or “connected”) herein may be understood as electrically coupled or as mechanically coupled, e.g., attached or fixed or attached, or just in contact without any fixation, and it will be understood that both direct coupling or indirect coupling (in other words: coupling without direct contact) may be provided.
The terms “and” and “or” herein may be understood to mean “and/or” as including either or both of two stated possibilities.
While the present disclosure has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims. The scope of the present disclosure is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
