Patent Application
20240331975
The present technology relates to semiconductor processing. More specifically, the present technology relates depositing and etching materials to form densified seam-free materials in gap fill processes.
Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods of formation and removal of exposed material. As device sizes continue to shrink, material formation may affect subsequent operations. For example, in gap filling operations a material may be formed or deposited to fill a trench or other feature formed on a semiconductor substrate. As features may be characterized by higher aspect ratios and reduced critical dimensions, these filling operations may be challenged. For example, as the deposition may occur at the top and along sidewalls of the feature, continued deposition may pinch off the feature including between sidewalls within the feature, and may produce voids within the feature. This can impact device performance and subsequent processing operations.
Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology.
Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature within the substrate. The processing region may be at least partially defined between a faceplate and a substrate support on which the substrate is seated. The methods may include forming plasma effluents of the silicon-containing precursor. The methods may include depositing a silicon-containing material on the substrate. A bias power may be applied to the substrate support. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming plasma effluents of the hydrogen-containing precursor. The methods may include etching the silicon-containing material from a sidewall of the feature within the substrate with the plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining silicon-containing material within the feature defined within the substrate.
In some embodiments, he feature within the substrate may be characterized by an aspect ratio of greater than or about 1:1. The feature may be characterized by a width across the feature of less than or about 100 nm. The bias power source may be operated in a pulsing mode at a pulsing frequency of less than or about 3 MHz during both the depositing and the etching. The bias power source may be operated at a duty cycle of less than or about 50% during both the depositing and the etching. A plasma power source may be operated in a continuous wave mode while the bias power source is operated in a pulsing mode during the depositing and the etching. The plasma effluents of the silicon-containing precursor may be formed at a first power level from a plasma power source. The plasma effluents of the hydrogen-containing precursor may be formed at a second power level from the plasma power source greater than the first power level. The densifying may include reducing a hydrogen content of the silicon-containing material to less than or about 30 at. %. The etching is performed halogen-free. The method may be repeated for a second cycle. A temperature of the substrate may be maintained at a temperature of less than or about 450° C. A pressure within the semiconductor processing chamber may be maintained at a pressure of greater than or about 1 Torr.
Some embodiments of the present technology encompass semiconductor processing methods. The methods may include i) forming plasma effluents of a silicon-containing precursor. The methods may include ii) depositing a silicon-containing material on a substrate. The substrate may define a feature within the substrate. The substrate may be seated on a substrate support. A bias power may be applied to the substrate support. The methods may include iii) forming plasma effluents of a hydrogen-containing precursor. The methods may include iv) etching the silicon-containing material from a sidewall of the feature within the substrate with the plasma effluents of the hydrogen-containing precursor. The methods may include repeating operations i) through iv) to iteratively fill the feature.
In some embodiments, the bias power source may be operated in a pulsing mode at a frequency of less than or about 3 MHz. The bias power source may be operated at a duty cycle of less than or about 25%. The etching may fully remove the silicon-containing material from sidewalls of the feature above a base fill of the feature. The bias power source may be operated at a plasma power of less than or about 750 W. The methods may include v) densifying remaining silicon-containing material within the feature defined within the substrate. A temperature of the substrate may be maintained at a temperature of less than or about 350° C.
Some embodiments of the present technology encompass semiconductor processing methods. The methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature within the substrate. The processing region may be at least partially defined between a faceplate and a substrate support on which the substrate is seated. The methods may include forming plasma effluents of the silicon-containing precursor. The plasma effluents of the silicon-containing precursor may be formed at a first power level from a plasma power source. The methods may include depositing a silicon-containing material on the substrate. A bias power may be applied to the substrate support. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming plasma effluents of the hydrogen-containing precursor. The plasma effluents of the hydrogen-containing precursor may be formed at a second power level from the plasma power source greater than the first power level. The methods may include etching the silicon-containing material from a sidewall of the feature within the substrate with the plasma effluents of the hydrogen-containing precursor. The etching may fully remove the silicon-containing material from sidewalls of the feature above a base fill of the feature. The methods may include densifying remaining silicon-containing material within the feature defined within the substrate.
In some embodiments, the silicon-containing material comprises amorphous silicon.
Such technology may provide numerous benefits over conventional systems and techniques. For example, by performing a sequential deposition and etch operation according to embodiments of the present technology, sidewall coverage can be limited or controlled, which may limit seam or void formation in small features. Additionally, by etch operations subsequent to deposition processes according to embodiments of the present technology, halogen residue may be reduced or eliminated, which may increase uniformity during further processing. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.
A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.
Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.
In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.
Amorphous silicon may be used in semiconductor device manufacturing for a number of structures and processes, including as a sacrificial material, for example as a dummy gate material, or as a trench fill material. In gap filling operations, some processing may utilize plasma-enhanced deposition under process conditions to increase the directionality of the deposition, which may allow the deposited material to better fill features on the substrate. In some deposition processes, the deposited material may be characterized by relatively high amounts of hydrogen. The increased amounts of hydrogen may form a material that is less dense than other formed films.
As feature sizes continue to shrink, plasma-enhanced depositions may be challenged for narrow features, which may be further characterized by higher aspect ratios. For example, pinching of the feature may more readily occur due to deposition on sidewalls of the feature, which in small feature sizes may further restrict flow and deposition further into the feature, and may produce seams or voids in the deposited material. Conventional technologies have attempted to address the formation of seams or voids by performing intermittent etch operations to remove materials from the sidewalls of the features being filled. However, conventional etch operations have required many cycles and/or the use of halogen etchants to remove materials from the sidewalls of the features being filled to limit seam or void formation. The incorporation of halogen etchants may leave halogen residue that may interfere with further processing operations.
The present technology may overcome these limitations by performing an intermittent etch of the formed film that is halogen-free. The etch may limit or prevent sidewall coverage during trench fill, allowing improved fill operations to be performed. Additionally, the etch may not leave any halogen residues that may interfere with further processing operations. Specifically, the halogen-free etch operations may prevent any non-uniformity in the structure.
After describing general aspects of a chamber according to some embodiments of the present technology in which plasma processing operations discussed below may be performed, specific methodology may be discussed. It is to be understood that the present technology is not intended to be limited to the specific films, chambers, or processing discussed, as the techniques described may be used to improve a number of film formation processes, and may be applicable to a variety of processing chambers and operations.
A plasma profile modulator 111 may be disposed in the processing chamber 100 to control plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108 that may be disposed adjacent to the chamber body 102, and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106, or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-like member, and may be a ring electrode. The first electrode 108 may be a continuous loop around a circumference of the processing chamber 100 surrounding the processing volume 120, or may be discontinuous at selected locations if desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or a mesh electrode, or may be a plate electrode, such as, for example, a secondary gas distributor.
One or more isolators 110a, 110b, which may be a dielectric material such as a ceramic or metal oxide, for example aluminum oxide and/or aluminum nitride, may contact the first electrode 108 and separate the first electrode 108 electrically and thermally from a gas distributor 112, also referred to as a faceplate, and from the chamber body 102. The gas distributor 112 may define apertures 118 for distributing process precursors into the processing volume 120. The gas distributor 112 may be coupled with a first source of electric power 142, such as an RF generator, RF power source, DC power source, pulsed DC power source, pulsed RF power source, or any other power source that may be coupled with the processing chamber. In some embodiments, the first source of electric power 142 may be an RF power source.
The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, a body of the gas distributor 112 may be conductive while a face plate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by the first source of electric power 142 as shown in
The first electrode 108 may be coupled with a first tuning circuit 128 that may control a ground pathway of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit elements. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 may be any circuit that enables variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some embodiments as illustrated, the first tuning circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled with the first electronic controller 134, which may afford a degree of closed-loop control of plasma conditions inside the processing volume 120.
A second electrode 122 may be coupled with the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled with a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode, and may be coupled with a second tuning circuit 136 by a conduit 146, for example a cable having a selected resistance, such as 50 ohms, for example, disposed in the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor, and may be coupled with the second electronic controller 140 to provide further control over plasma conditions in the processing volume 120.
A third electrode 124, which may be a bias electrode and/or an electrostatic chucking electrode, may be coupled with the substrate support 104. The third electrode may be coupled with a second source of electric power 150 through a filter 148, which may be an impedance matching circuit. The second source of electric power 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second source of electric power 150 may be an RF bias power.
The lid assembly 106 and substrate support 104 of
Upon energizing a plasma in the processing volume 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow properties of the ground paths represented by the two tuning circuits 128 and 136. A set point may be delivered to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of deposition rate and of plasma density uniformity from center to edge. In embodiments where the electronic controllers may both be variable capacitors, the electronic sensors may adjust the variable capacitors to maximize deposition rate and minimize thickness non-uniformity independently.
Each of the tuning circuits 128, 136 may have a variable impedance that may be adjusted using the respective electronic controllers 134, 140. Where the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors, and the inductances of the first inductor 132A and the second inductor 132B, may be chosen to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum in the capacitance range of each variable capacitor. Hence, when the capacitance of the first electronic controller 134 is at a minimum or maximum, impedance of the first tuning circuit 128 may be high, resulting in a plasma shape that has a minimum aerial or lateral coverage over the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, effectively covering the entire working area of the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and aerial coverage of the substrate support may decline. The second electronic controller 140 may have a similar effect, increasing and decreasing aerial coverage of the plasma over the substrate support as the capacitance of the second electronic controller 140 may be changed.
The electronic sensors 130, 138 may be used to tune the respective circuits 128, 136 in a closed loop. A set point for current or voltage, depending on the type of sensor used, may be installed in each sensor, and the sensor may be provided with control software that determines an adjustment to each respective electronic controller 134, 140 to minimize deviation from the set point. Consequently, a plasma shape may be selected and dynamically controlled during processing. It is to be understood that, while the foregoing discussion is based on electronic controllers 134, 140, which may be variable capacitors, any electronic component with adjustable characteristic may be used to provide tuning circuits 128 and 136 with adjustable impedance.
Processing chamber 100 may be utilized in some embodiments of the present technology for processing methods that may include formation or etching of materials for semiconductor structures. It is to be understood that the chamber described is not to be considered limiting, and any chamber that may be configured to perform operations as described may be similarly used.
Method 200 may include additional operations prior to initiation of the listed operations. For example, additional processing operations may include forming structures on a substrate, which may include both forming and removing material. For example, transistor structures, memory structures, or any other structures may be formed. Prior processing operations may be performed in the chamber in which method 200 may be performed, or processing may be performed in one or more other processing chambers prior to delivering the substrate into the semiconductor processing chamber or chambers in which method 200 may be performed. Regardless, method 200 may optionally include delivering a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal such as substrate support 104, and which may reside in a processing region of the chamber, such as processing volume 120 described above.
A substrate on which several operations have been performed may be substrate 305 of a structure 300, which may show a partial view of a substrate on which semiconductor processing may be performed. It is to be understood that structure 300 may show only a few top layers during processing to illustrate aspects of the present technology. The substrate 305 may include a material in which one or more features 310 may be formed. Substrate 305 may be any number of materials used in semiconductor processing. The substrate material may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metal materials, or any number of combinations of these materials, which may be the substrate 305, or materials formed in structure 300. Features 310 may be characterized by any shape or configuration according to the present technology. In some embodiments, the features may be or include a trench structure or aperture formed within the substrate 305.
Although the features 310 may be characterized by any shapes or sizes, in some embodiments the features 310 may be characterized by higher aspect ratios, or a ratio of a depth of the feature to a width across the feature. For example, in some embodiments features 310 may be characterized by aspect ratios greater than or about 1:1, and may be characterized by aspect ratios greater than or about 2:1, greater than or about 3:1, greater than or about 5:1, greater than or about 10:1, or greater. Additionally, the features may be characterized by narrow widths or diameters across the feature including between two sidewalls, such as a dimension less than or about 100 nm, and may be characterized by a width across the feature of less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 17 nm, less than or about 15 nm, less than or about 12 nm, less than or about 10 nm, less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, or less.
In some embodiments, method 200 may include optional treatment operations, such as a pretreatment, that may be performed to prepare a surface of substrate 305 for deposition. Once prepared, method 200 may include providing one or more precursors to a processing region of the semiconductor processing chamber housing the structure 300 at operation 205. The precursors may include one or more silicon-containing precursors, as well as one or more diluents or carrier gases such as an inert gas or other gas delivered with the silicon-containing precursor. Silicon-containing precursors that may be used during the silicon-containing material 315 may include, but are not limited to, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H10), pentasilane (Si5H12), or other organosilanes including cyclohexasilanes, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), as well as any other silicon-containing precursors that may be used in silicon-containing film formation. The silicon-containing material may be nitrogen-free, oxygen-free, and/or carbon-free in some embodiments.
Deposition plasma effluents may be formed of the deposition precursors including the silicon-containing precursor at operation 210. The deposition plasma effluents may be formed within the processing region, which may allow deposition materials to deposit on the substrate. For example, in some embodiments a capacitively-coupled plasma may be formed within the processing region by applying plasma power to the faceplate or substrate support as previously described.
The power applied during deposition may be a lower power plasma, which may limit dissociation, and which may maintain an amount of hydrogen incorporation in the deposited materials. Accordingly, in some embodiments a plasma power source may deliver a plasma power to the faceplate or substrate support of less than or about 300 W, and may deliver a power of less than or about 250 W, less than or about 200 W, less than or about 150 W, less than or about 100 W, less than or about 50 W, or less. At plasma powers to the faceplate or substrate support of greater than, for example, 350 W, the substrate 305, such as the sidewalls defining the features 310, may be damaged.
During the deposition operation, an additional power source, a bias power source, may be engaged and coupled with the substrate support as previously described to provide a bias to the plasma generated above the substrate 305. The bias may draw plasma effluents to the substrate 305, which may increase deposition at the bottom of the features 310. The bias power applied may be relatively low to limit damage to the structure. Accordingly, in some embodiments a plasma power source may deliver a plasma power to the faceplate or substrate support of less than or about 1,000 W, and may deliver a power of less than or about 750 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, or less. Additionally, by adjusting the source power and the bias power applied, densification of the deposited silicon-containing material 315 may occur during the deposition operation. In embodiments, both the source power and the bias power may be applied to the substrate support, such as via second source of electric power 150 as previously described.
A silicon-containing material may be deposited on the substrate at operation 215 from plasma effluents of the silicon-containing precursor. The silicon-containing material may be or include amorphous silicon. The deposited materials may at least partially fill the features on the substrate to provide a bottom-up type of gap fill. As illustrated in
Subsequent an amount of deposition, in some embodiments of the present technology a treatment or modification process may be formed that is configured to etch back the formed material. This process may be performed in the same chamber as the deposition, and may be performed in a cyclic process to fill the feature. In some embodiments the silicon-containing precursor flow may be halted and the processing region may be purged. Subsequent a purge, a hydrogen-containing precursor may be provided to the processing region of the semiconductor processing chamber at operation 220. Treatment plasma effluents may be formed at operation 225, which may also be a capacitively-coupled plasma formed within the processing region, although in some embodiments an inductively-coupled plasma may similarly be applied. The treatment plasma effluents may be formed by applying a plasma power to the faceplate or substrate support, and in some embodiments no other power source may be engaged.
Similar to the deposition operation, during the treatment operation, the bias power source may be engaged to provide a bias to the plasma generated above the substrate. This may draw plasma effluents to the substrate, which may bombard the film and cause densification of the deposited silicon-containing material 315. Although any hydrogen-containing material may be used, in some embodiments diatomic hydrogen or deuterium may be used as the hydrogen-containing precursor to produce the treatment plasma, along with one or more additional precursors. The hydrogen radicals and ions may readily penetrate the materials formed within the features 310, and may release incorporated hydrogen from the silicon-containing material 315 causing densification. The bias power applied may be relatively low to limit sputtering of the produced film as well as to limit any potential damage to the structure. Materials delivered to form the plasma may similarly have a reduced amount of heavier materials to limit sputtering of the deposited films. Additionally, by adjusting the source power and the bias power applied, an etching operation may be performed, which may reduce sidewall coverage of the deposited material.
The etch operation may be performed halogen-free. The presence of halogen-containing materials may result in halogen residues remaining in the features 310 subsequent filling of the features 310 with silicon-containing material 315. This halogen residue may contaminate the structure 300, and may cause non-uniformities to result during further processing. Accordingly, the etch operation may be performed without the presence of halogens or halogen-containing materials.
As previously discussed, hydrogen, or any other hydrogen-containing material may be utilized to generate a plasma within the processing region by delivering power to the faceplate from the plasma power source. The source plasma power in some embodiments may be greater than a plasma power used during the deposition. For example, the plasma power delivered may be greater than or about 100 W, and may be greater than or about 200 W, greater than or about 300 W, greater than or about 400 W, or more. By increasing the source plasma power during the treatment plasma formation, a greater amount of plasma effluents may be generated. However, the source plasma power may be maintained at less than or about 1000 W to not damage the underlying structure, and may be maintained at less than or about 900 W, less than or about 800 W, less than or about 700 W, less than or about 600 W, or less. Additionally, aspects of the bias power may also be adjusted, which may also limit damage to the underlying structure. For example, the bias power may be maintained below or about 1,000 W, and may be below or about 750 W, below or about 600 W, below or about 500 W, below or about 400 W, or less. While in some operations, a bias power may be higher than a plasma source power, the bias power may alternatively be maintained below the plasma power in other operations.
Applying greater bias may increase a directionality of delivery perpendicular to a plane across the substrate. Accordingly, by reducing the bias power supplied, the amount of directionality may reduce, which may increase interaction of the plasma effluents within the feature. The plasma effluents may then etch the silicon-containing material 315 at operation 230, and may remove the silicon-containing material 315 from the sidewalls of the features 310. The plasma effluents may fully remove silicon-containing material 315 from the sidewalls of the features 310 above a base fill of the silicon-containing material 315. The base fill of the silicon-containing material may refer to the silicon-containing material 315 deposited at the bottom of the features 310, or on the previously deposited silicon-containing material 315 toward the bottom of the features 310.
Simultaneously, or additionally, plasma effluents delivered more directionally may penetrate the remaining silicon-containing material 315 formed at the bottom of the features 310 and/or on the substrate 305. This penetration may reduce hydrogen incorporation to densify the film at optional operation 235. The densification at operation 235 may result from the plasma effluents of one or more precursors or, in embodiments, may be a separate operation using, for example, an inert precursor to densify the remaining silicon-containing material 315. As illustrated in
Additional adjustments may be made to further increase etching of deposited material along sidewalls of the features by adjusting one or more characteristics of the plasma power or bias power being supplied. For example, in some embodiments both the plasma power source and bias power source may be operated in a continuous wave mode. Additionally, one or both of the power sources may be operated in a pulsed mode. In some embodiments, the source power may be operated in a continuous wave mode or pulsed mode while the bias power is operated in a pulsed mode. A pulsing frequency for the source power may be greater than or about 1 MHZ, and may be greater than or about 3 MHz, greater than or about 5 MHz, greater than or about 13.5 MHz, greater than or about 15 MHz, greater than or about 17.5 MHz, greater than or about 20 MHz, greater than or about 22.5 MHz, or more. A pulsing frequency for the bias power may be less than or about 5 MHZ, and may be less than or about 4 MHZ, less than or about 3 MHz, less than or about 2 MHZ, or less. The duty cycle of the bias power may be less than or about 75%, and the bias power may be operated at a duty cycle of less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, less than or about 20%, less than or about 10%, less than or about 5%, or less. By operating the bias power for a reduced duty cycle, such as an on-time duty of less than or about 50%, a greater amount of time per cycle may be performing a more isotropic etch within the feature, which may better remove material from the sidewalls.
As shown in
Temperature and pressure may also impact operations of the present technology. For example, the process may be performed at a temperature below or about 450° C., and may be performed at a temperature less than or about less than or about 400° C., less than or about 350° C., less than or about 300° C., less than or about 250° C., less than or about 225° C., less than or about 200° C., less than or about 180° C., less than or about 160° C., less than or about 140° C., less than or about 120° C., less than or about 100° C., less than or about 80° C., less than or about 60° C., less than or about 40° C., or lower. The temperature may be maintained in any of these ranges throughout the method, including during the treatment and etching. At higher temperatures, crystallized silicon-containing material may be formed instead of an amorphous silicon-containing material. Pressure within the semiconductor processing chamber may be kept relatively low for any of the processes as well, such as at a chamber pressure of less than or about 20 Torr, and pressure may be maintained at less than or about 18 Torr, less than or about 16 Torr, less than or about 14 Torr, less than or about 12 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, less than or about 4 Torr, less than or about 2 Torr, or less. However, lower pressures may result in a slower fill rate of the features. Additionally, higher pressures may result in reduced pattern loading and/or line bending. Accordingly, pressure within the semiconductor processing chamber may be kept maintained at greater than or about 1 Torr, greater than or about 2 Torr, and pressure may be maintained at greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr, greater than or about 6 Torr, greater than or about 7 Torr, or more. By performing processes according to some embodiments of the present technology, improved fill of narrow features utilizing silicon-containing materials may be produced.
In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.
Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology. Additionally, methods or processes may be described as sequential or in steps, but it is to be understood that the operations may be performed concurrently, or in different orders than listed.
Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.
As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a silicon-containing precursor” includes a plurality of such precursors, and reference to “the silicon-containing material” includes reference to one or more materials and equivalents thereof known to those skilled in the art, and so forth.
Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.
