DEPOSITION OF THIN FILM DIELECTRICS AND LIGHT EMITTING NANO-LAYER STRUCTURES

Abstract

A method is disclosed for deposition of thin film dielectrics, and in particular for chemical vapour deposition of nano-layer structures comprising multiple layers of dielectrics, such as, silicon dioxide, silicon nitride, silicon oxynitride and/or other silicon compatible dielectrics. The method comprises post-deposition surface treatment of deposited layers with a metal or semiconductor source gas, e.g. a silicon source gas. Deposition of silicon containing dielectrics preferably comprises silane-based chemistry for deposition of doped or undoped dielectric layers, and surface treatment of deposited dielectric layers with silane. Surface treatment provides dielectric layers with improved layer-to-layer uniformity and lateral continuity, and substantially atomically flat dielectric layers suitable for multilayer structures for electroluminescent light emitting structures, e.g. active layers containing rare earth containing luminescent centres. Doped or undoped dielectric thin films or nano-layer dielectric structures may also be provided for other semiconductor devices.

Description

TECHNICAL FIELD

The present invention relates to the deposition of thin film dielectrics for semiconductor device structures, and more particularly relates to nano-layer dielectrics for light emitting device structures and methods of chemical vapour deposition thereof. This invention has particular application to engineered structures for light emitters comprising rare earth luminescent centers in a dielectric host matrix, e.g. for high brightness, solid-state lighting.

BACKGROUND OF THE INVENTION

Applicant's related copending United States patent publications nos. 2008/0093608 entitled “Engineered Structure for Solid State Light Emitters” published Apr. 24, 2008 in the name of Chik et al, 2007/0181898 entitled “Pixel Structure for a Solid State Light Emitting Device” published Aug. 9, 2007 in the name of Chik et al, and U.S. patent application Ser. No. 12/508,033 entitled “Engineered structure for high brightness solid-state light emitters” filed Jul. 23, 2009 in the name of Calder et al, which are incorporated herein by reference, disclose light emitting device structures and methods of fabrication of light emitting device structures from silicon or other group IV materials. In particular, high brightness, light emitting device structures are disclosed that comprise thin active layers, i.e. light emitting layers, comprising luminescent centres which may be electrically excited, such as rare earth ions in a rare earth oxide or other suitable host matrix. The host matrix may comprise a dielectric, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon aluminum oxynitride (SiAlON), aluminum oxide, or other materials, such as disclosed the above referenced copending applications. For improved excitation efficiency, a drift layer, i.e. an electron acceleration layer, comprising, for example, undoped silicon dioxide or silicon nitride, is provided adjacent each active layer. Preferably, for high brightness light emitters, engineered structures are provided comprising a plurality of active layer and drift layer pairs, in which each drift layer has a thickness, dependent on the applied electric field, related to a required excitation energy of an adjacent active layer. Multilayer light emitting structures may be provided, for example, comprising one or more active layers comprising rare earth doped silicon dioxide or silicon nitride, and corresponding drift layers comprising undoped silicon dioxide or silicon nitride. Active layers are preferably thin, and may be in the range from one monolayer (1 atomic layer) to 10 nm thick Drift layers are typically 2 to 10 nm thick, depending on the applied electric field, to provide a sufficient thickness for acceleration of electrons for appropriate energy matching. Light emitting structures of this type may be fabricated as large area emitters or as pixel structures. Structures may comprise one active layer/drift layer pair or many, e.g. twenty-four, layer pairs emitting one or more colours, to provide light emission of a desired Colour Rendering Index (CRI).

With reference to FIG. 1, a light emitting device structure 1, similar to that described in the above referenced co-pending United States patent applications, comprises a multi-layer emitter structure 2 including a plurality of active layer/drift layer pairs, i.e. thin active layers of rare earth doped silicon nitride 3 and silicon dioxide drift layers 4, formed on a silicon substrate 6 with a back contact electrode 7. Also provided is a top electrode 8 comprising a transparent conducting oxide, such as indium tin oxide. Light emission from the multi-layer emitter structure 1 may be electrically excited by application of a suitable AC or DC voltage to the emitter layer structure 2 between the back contact electrode 7 and the top electrode 8.

For light emitting structures 1, as disclosed in the above mentioned references, which operate at relatively high electric fields, i.e. 5 MV/cm or more, high quality dielectrics with low trap density are required for reliability and extended lifetime. For high brightness and luminous efficiency, careful control of layer thicknesses is desirable. Such structures have been fabricated by plasma enhanced chemical vapour deposition (PECVD), for example.

Literature reports indicate that suitable rare earth containing oxides, or rare earth doped oxides or other dielectrics, can be formed by any of a number of techniques, such as ion implantation, chemical vapour deposition (CVD), physical vapour deposition, i.e. sputtering, spin-on (sol gel) techniques, beam deposition, laser deposition, or any of a large number of similar chemical or physical deposition techniques that are generally well known in the thin film or semiconductor technology fields. Although epitaxial processes are well known for growing nano-structured single crystal semiconductor layers, e.g. for multiquantum well (MQW) semiconductor lasers with QW thicknesses on the order of 3 to 5 nm, to the inventors' knowledge, these processes are typically applied for deposition of crystalline materials and are not applicable for amorphous, i.e. non-crystalline, dielectric layers. Methods, such as chemical vapour deposition (CVD), are well established for achieving high quality, uniform single layers of thin dielectrics, or a few thin film dielectric layers, i.e. the number of layers N=2 or 3, for such structures as transistor gate stacks. However, achieving high quality multilayer stacks (N>3) of thin films of amorphous or non-crystalline materials poses some challenges to known commercial chemical vapour deposition processes for volume production at reasonable cost.

Although light emitting device structures, such as shown in FIG. 1, have been fabricated by PECVD, for larger scale fabrication of multilayer light emitting structures, a suitable production class tool is required which is capable of deposition of high quality oxides and nitrides. In these respects, a low pressure (LP) CVD process, i.e. thermal CVD, for deposition of higher quality dielectrics offers some advantages over a PECVD process.

For commercial production of high quality, thin dielectrics such as silicon dioxide used for gate oxides for electronic devices, industry standard processes use chemical vapour deposition (CVD). That is, silicon dioxide and silicon nitride are typically produced by low pressure LPCVD from a mixture of reactant gases comprising a silicon source gas, typically silane (SiH₄), dichlorosilane (SiH₂Cl₂), or TEOS (tetra-ethyl ortho silicate (Si(OC₂H₅)₄) with an oxidation source gas, e.g. oxygen (O₂) or nitrous oxide (N₂O), or a nitridation source gas, e.g. ammonia (NH₃) or nitrogen (N₂), as appropriate. The reaction is thermally driven, at a relatively high temperature, e.g. 400° C. to 900° C. Examples of known systems and processes, and examples of reactant gases and process conditions, for chemical vapour deposition of silicon dioxide, silicon nitride and silicon oxynitride are disclosed, for example, in U.S. Pat. Nos. 6,713,127, 6,884,464, and 7,465,669 to Iyer et al. (Applied Materials). To improve uniformity and flatness of each layer in a multi-layer structure, an optional post deposition treatment or passivation with the oxidation or nitridation source gas is also disclosed. That is, after deposition of a desired layer thickness, the flow of silicon source gas is turned off (or diverted) and the surface of the deposited layer is then exposed to a flow of nitridation or oxidation source gas only, i.e. ammonia or nitrous oxide. This post treatment of the deposited layer with oxidation or nitridation source gas is explained in U.S. Pat. Nos. 6,713,127 and 6,884,464 as terminating unreacted silicon sites, to maximize uniformity and minimize surface roughness of the deposited layers.

However, attempts to fabricate larger area, thin film dielectric layers for a multilayer light emitting structures, as described above, using available commercial thermal CVD processes and equipment, and preferred reactant gas mixtures and process conditions, such as those described in the aforementioned patents, does not provide sufficient control of the layer thicknesses, uniformity, and layer-to-layer reproducibility for such light emitting structures. In fabricating a light emitting device structure wherein active layers comprise rare earth doped silicon nitride, and drift layers comprise silicon dioxide, there is breakdown of the layer structure after deposition of the first few layers on a silicon substrate. For example, FIG. 2 shows a transmission electron micrograph (TEM) cross section through a multi-layer structure comprising five periods, i.e. five layer pairs, deposited using conventional disilane chemistry and process sequence, and including a step of post deposition treatment with the oxidation or nitridation source gas, as described above.

The photomicrograph in FIG. 2 illustrates an example of the multi-layer emitter structure 2, which comprises a plurality of thin layers of silicon nitride 3 and silicon dioxide 4, formed on a silicon substrate 6. In FIG. 2, the silicon nitride layers 3 appear with darker contrast than the silicon dioxide layers 4. The multi-layer emitter structure 2 was deposited by an industry standard, well known process of thermal chemical vapour deposition (CVD) at low pressure, using disilane as the silicon source gas, and an oxidation source gas comprising N₂O or a nitridation source gas comprising NH₃, to produce the silicon dioxide or silicon nitride layers, respectively. As is conventional, after suitable preparation of the silicon substrate 6, deposition of a layer of silicon dioxide 4 or silicon nitride 3 proceeds by introducing a suitable mixture of reactant gases, together with an inert carrier gas into the CVD reaction chamber at an appropriate temperature and pressure. The substrate 6 is exposed to the reactant gas mixture for a time sufficient to deposit a required thickness of dielectric, i.e. silicon nitride or silicon dioxide. When the desired thickness of dielectric is reached the disilane flow is switched off or diverted, and the flow of nitridation or oxidation source gas, e.g. N₂O or NH₃, is continued for post-treatment, i.e. to terminate reactive silicon, and passivate the surface of the deposited dielectric layer 3 or 4. After purging the chamber with inert carrier gas, then the reactant gas mixture for deposition of the next layer is introduced into the chamber and, so on. This allows a number of layers 3 and 4 of a predetermined thickness to be deposited sequentially.

However, as will be seen from FIG. 2, although reasonable uniformity of the layer thickness is obtained for the first layer 4, the layer structure begins to break down as more layers are deposited. Several layers into the structure significant surface structure and roughness of each layer is apparent, which propagates through subsequently deposited layers. Thus for example in a large area multi-layer structure, such as for a light emitting device structure 2 as shown schematically in FIG. 1, that requires, for example, forty-eight layer, i.e. twenty-four layer pairs of active layers 3 comprising a luminescent species, and respective drift layers 4, this structure is far from ideal. The light emitting structure 2 in FIG. 2 shows surface roughness exceeding 1 nm. In particular, in a light emitting structure, careful control of the drift layer thickness is desirable for controlling excitation energy in operation of the device, and because such devices operate at relatively high fields, high quality oxides or nitrides, free of defects are needed for reliability and extended lifetime. As apparent from FIG. 2, surface “roughness” or discontinuities in the layer structure are as large as the thickness of the layer. Consequently this process, even with post-treatment of the deposited layers with the oxidation or nitridation source gas, cannot meet the required specifications for a multi-layer light emitting device structure described above, requiring sub nanometer surface roughness.

Consequently, improved processes are required for deposition of multilayer light emitting structures comprising nano-layer dielectrics, particularly for layers less than 10 nm thick, where careful control of layer uniformity, thickness, surface roughness or flatness, and layer-to-layer reproducibility is required.

It is desirable to overcome the above-mentioned limitations and provide for improved uniformity and flatness of dielectric layers for light emitting structures and other semiconductor devices.

Thus, there is a need for alternative or improved materials, structures and/or methods of fabrication for solid-state light emitters, particularly for applications requiring higher brightness, luminous efficacy and reliability, such as solid-state lighting.

SUMMARY OF THE INVENTION

The present invention seeks to overcome or mitigate the above-mentioned problems relating to deposition of thin film dielectrics and deposition of nano-layer structures for solid-state light emitters, or at least provide an alternative.

One aspect of the invention provides a method of fabricating a thin film dielectric structure for a semiconductor device comprising:

a) depositing a first layer, comprising a first dielectric, on a substrate; and

b) surface treating the first layer with a surface activating reactant gas.

When the thin film dielectric comprises a plurality of layer pairs of first and second dielectric layers, steps of deposition of a first or second dielectric layer and post deposition surface treatment thereof are repeated sequentially to provided a desired number of layer pairs.

Another aspect of the invention provides a method of depositing, by chemical vapour deposition (CVD) in a CVD reaction chamber, a thin film dielectric stack comprising:

a) providing a substrate;

b) depositing a first dielectric layer of a first desired thickness by exposure of the substrate to a first reactant gas mixture comprising a silicon source gas and at least one of one of a nitridation source gas and an oxidation source gas;

c) surface treating the first dielectric layer by exposure to the silicon source gas;

d) depositing a second dielectric layer of a second desired thickness by exposure to a second reactant gas mixture comprising a mixture of a silicon source gas and at least one of one of a nitridation source gas and an oxidation source gas; and

e) surface treating the second dielectric layer by exposure to the silicon source gas. a method

In particular, dielectric layers such as oxides, nitrides or oxynitrides of silicon or other silicon compatible dielectrics, with or without dopants, such as rare earth luminescent centres, may be deposited with significantly improved uniformity, and reduced surface roughness, approaching atomically flat layers. For example, multilayer thin film dielectrics may be deposited by thermal CVD, characterized by a surface roughness of less than 0.21 nm, when the deposited dielectric layer is surface treated with a silicon source gas, and silane in particular, before depositing a subsequent layer thereon.

For improved layer-to-layer uniformity, multilayer dielectric structures suitable for light emitting structures may be deposited by surface treating each individual dielectric layer with silane prior to deposition of a subsequent layer.

Further aspects of the invention provide semiconductor devices structures and light emitting device structures comprising thin film dielectric layers deposited by these methods. For light emitting device structures, active (light emitting) layers may be doped with luminescent rare earth species or other luminescent centres.

Thus, in a preferred embodiment, a light emitting device structure may be provided comprising a plurality of active layer and drift layer pairs, each of the active and drift layers comprising a substantially atomically flat dielectric layer deposited by chemical vapour deposition. In preferred embodiments of this structure, each dielectric layer is selected from the group consisting of doped and undoped oxides and nitrides of silicon. Each active layer comprises luminescent centres, preferably a rare earth, such as cerium, and has a thickness from 1 monolayer to 10 nm. Each drift layer has a thickness from 2 nm to 10 nm. Preferably each layer has a surface roughness of less than 0.21 nm Light emitting structures may comprise a layer stack comprising one or more active layer/drift layer pairs, wherein the drift layers are configured with electrode structures as appropriate, for DC or for AC operation.

For example, for fabrication of a multilayer dielectric stack for in a light emitting structure, the first dielectric layer may comprise rare earth doped silicon nitride (active layer) deposited from a reactant mixture of silane and ammonia (NH3). The second dielectric layer may comprise silicon dioxide (drift layer). To deposit silicon nitride, the first reactant gas mixture comprising silane and ammonia, together with a suitable source of rare earth dopant if required, is introduced into the chamber to deposit a desired thickness of the first dielectric layer, i.e. the rare earth doped silicon nitride. Then the exposure of the substrate to the flow of all reactant gases is stopped, with the exception of the silicon source gas, which in this embodiment is silane. Silane is flowed into the chamber, with an inert carrier gas to maintain pressure and flow dynamics, for a sufficient time to surface treat the deposited layer. After purging the chamber a second mixture of reactant gases consisting of silane and nitrous oxide are introduced into the chamber to deposit a required thickness of silicon dioxide, and then the oxygen containing reactant gas flow is stopped, to expose the deposited surface to silane. Thus after deposition of each dielectric layer, the surface of the deposited dielectric layer is treated by briefly by exposure to the silicon source gas, plus additional non-reactive carrier gases to maintain chamber pressure and flow dynamics, and then the chamber is purged with the carrier gas or gases, before deposition of the next layer. Silane treatment of the deposited dielectric layer is preferably long enough to improve flatness, e.g. by providing active silicon or a monolayer of silicon on the surface, while avoiding formation of a layer of amorphous silicon or polycrystalline silicon.

While this method is particularly suitable for deposition of engineered light emitting structures as described in the above reference copending patent applications, thin well defined doped or undoped dielectric layers that are substantially atomically flat are also desirable for many other electronic devices such as gate oxides for transistor gate stacks, and gate oxide or tunnel oxides for memory or flash devices.

While methods according to preferred embodiments are particularly suitable for deposition by thermal CVD of commonly used silicon containing dielectrics such as nitrides, oxides and oxynitrides of silicon, it is believed that similar surface activating treatment may be applicable for deposition of other dielectrics, e.g. SiAlON or aluminum oxide, or other dielectrics of similar structure or surface chemistry. with improved layer-to-layer reproducibility and reduced surface roughness. More generally, during chemical vapour deposition of dielectrics comprising oxides, nitrides or oxynitrides of metal or semiconductor species M, deposited layers are surface treated with an appropriate M source gas, before deposition of a subsequent dielectric layer.

Methods and structures according to embodiments of the invention therefore provide for improved flatness, reduced surface roughness, and improved layer-to-layer uniformity in multilayer semiconductor device structures, and particularly for light emitting device structures.

Embodiments of the invention will now be described, by way of example, with reference to the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of a light emitting device comprising an emitter layer structure as disclosed in Applicants aforementioned co-pending patent applications;

FIG. 2 shows a TEM photomicrograph of a multilayer structure similar to the emitter layer structure shown in FIG. 1, fabricated by a conventional known method of chemical vapour deposition;

FIG. 3 is a schematic illustration of a multilayer dielectric structure according to an embodiment of the present invention;

FIG. 3A shows an enlarged schematic view of an interface between first and second dielectric layers deposited using a conventional CVD process;

FIG. 3B shows an enlarged schematic view of the interface between first and second dielectric layers deposited by a CVD method according to a preferred embodiment of the present invention;

FIG. 4 shows a TEM photomicrograph of a multilayer structure for an emitter layer structure similar to that shown in FIG. 3B, comprising a plurality of thin dielectric layers, fabricated by a method chemical vapour deposition according to an embodiment of the present invention;

FIG. 5 shows a TEM photomicrograph of another multilayer emitter structure comprising a plurality of thin dielectric layers, fabricated by a method of chemical vapour deposition according to a preferred embodiment of the present invention;

FIG. 6 illustrates a process flow chart for deposition of dielectric layers and surface treatment by a method according to an embodiment of the invention;

FIG. 7 illustrates a more detailed process flow chart for a method according to an embodiment of the invention for deposition a structure as shown in FIGS. 4 and 5; and

FIG. 8A shows schematically a light-emitting device structure comprising a multilayer light emitting structure, shown enlarged in FIG. 8B, according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

With reference to FIG. 3, a device structure 10, in accordance with an embodiment of the present invention, comprises a multi-layer dielectric stack 20 including a plurality of first and second dielectric layer pairs 12/13. Each first dielectric layer 12 comprises, for example, silicon nitride, and each second dielectric layer 13 comprises, for example, silicon dioxide, formed on a substrate 11, e.g. a silicon substrate wafer, or other suitable substrate material or underlying semiconductor device structure.

Typical materials for thin film dielectric structures comprising multilayer dielectric stacks, e.g. for light emitting devices or in other semiconductor device structures, may comprise, for example, suitable oxides, nitrides or oxynitrides of a metal or a semiconductor. Silicon dioxide, silicon nitride and silicon oxynitride are widely used as dielectrics for silicon process technology. Other examples include silicon aluminum oxide (SiAlON) and aluminum oxide. Metal oxides, such as hafnium or zirconium oxide, or metal silicates may be used for high k gate dielectrics. Dielectrics comprising luminescent centers, such as rare earth doped silicon nitride or silicon dioxide, or rare earth oxides may be used for light emitting devices.

When the multilayer dielectric stack 20 of FIG. 3 forms part of a light emitting structure, selected layers, e.g. the first dielectric layers 12 of each layer pair, may be doped with luminescent centres, e.g. rare earth luminescent centres, to provide active layers of the light emitting structure, such as described in the Applicant's above referenced copending United States patent applications, as illustrated schematically in FIG. 1, with intervening undoped drift layers 13. In this and other semiconductor device structures, it may be required to deposit multiple dielectric layer pairs 12 and 13 having various thicknesses from one monolayer to about 10 nm thick, with careful control of the thickness of each layer, to provide layer-to-layer uniformity through many layers.

Thus, ideally, each layer 12 and 13 is deposited by a method that provides a smooth surface, with minimal surface roughness, and where there is an abrupt, and preferably atomically flat interface 16, between layers 12 and 13, as represented schematically in FIG. 3B, which represents an enlarged view of the interface 16 between first and second dielectric layers 12 and 13. On the other hand, as represented schematically (not to scale) in FIG. 3A, if the interface 17 between each layer 12 and 13 shows a significant degree of surface roughness, this will result in non-uniformities in film thicknesses, and breakdown of layer to layer uniformity.

With reference to FIG. 4, a TEM image is shown of a multi-layer device structure 10, fabricated by a method according to an embodiment of the present invention, comprising three periods (three layer pairs) of a layer stack comprising first dielectric layers 12, comprising silicon nitride, and second dielectric layers 13, comprising silicon dioxide, deposited on a substrate 11, which, in this embodiment, comprises silicon.

Relative to the structure fabricated by a conventional known process and shown in the TEM image of FIG. 2 it is apparent from the structure 10 of a the embodiment shown in the TEM image in FIG. 4, that significantly improved uniformity and lateral continuity of layers is achieved and surface roughness was significantly reduced to provide substantially atomically flat layers, with abrupt transitions at the interfaces 16 between layers 12 and 13.

With reference to FIG. 5, a TEM photomicrograph of another multi-layer device structure 20, in accordance with another embodiment of the present invention comprises forty-eight layers (twenty-four layer pairs) of the first dielectric layers 12, comprising silicon nitride, and second dielectric layers 13, comprising silicon dioxide fabricated on a silicon substrate 11, by a method according to a preferred embodiment of the present invention. As is apparent from this image, significantly improved layer-to-layer uniformity and continuity are maintained up to forty-eight layers, and surface roughness was significantly reduced to provide substantially atomically flat layers throughout the twenty-four periods (first dielectric layer 12/second dielectric layer 13 pairs) of the multi-layer light emitting device structure 20.

The multi-layer device structure 20 is provided in which the surface of each of the first and second dielectric layers 12 and 13 is characterized by a surface roughness of 0.21 nm or less, e.g. as measured by AFM (atomic force microscopy).

The multi-layer device structures 10 and 20, shown in FIGS. 4 and 5, were deposited by the process steps represented schematically in FIGS. 6 and 7. By way of example, a process is described for deposition of a first dielectric layer 12, comprising silicon nitride, and a second dielectric layer 13, comprising silicon dioxide, although it will be appreciated that alternatively deposition of the dielectric layer stack may commence with a layer of silicon dioxide. After suitable preparation of the silicon substrate 11 at 101, the chamber was preheated and the carrier gas (i.e. nitrogen) pressure and gas flow is stabilized, as at 102-1. Next, the surface of the substrate 11 was pre-treated with the nitridation source gas, i.e. ammonia NH₃ as at 102-2. A first reactant gas mixture comprising a silicon source gas, e.g. silane, the nitridation source gas, e.g. ammonia, and the inert carrier gas (nitrogen), for deposition of the first dielectric layer 12, comprising silicon nitride, was introduced into the reaction chamber at a temperature of 750° C. and a pressure of 240 Ton. The substrate 11 was exposed to the reactant gas mixture for sufficient time to deposit a desired thickness of silicon nitride for the first dielectric layer 12, as at 102-3. In this example, a deposition time of 11.5 seconds provided a first dielectric layer 12 of silicon nitride with a thickness of 5 nm. The flow of ammonia reactant gas was then turned off, but the flow of a surface activating reactant gas, e.g. the silicon source gas: silane, was allowed to continue for surface treatment of the deposited silicon nitride dielectric layer 12, as at 103, before purging the chamber with carrier gas (103-2) and cooling the chamber (103-3).

For deposition of the subsequent dielectric layer, i.e. a second dielectric layer 13 comprising silicon dioxide, the chamber was preheated again (104-1), and the surface of the first dielectric layer 12 (silicon nitride) was pre-treated with an oxidation source gas N₂O, as at 104-2. Then, a second reactant gas mixture comprising a silicon source gas, e.g. silane, and oxidation source gas, e.g. nitrous oxide, together with the carrier gas, is introduced into the chamber for deposition of the second dielectric layer 13 comprising silicon dioxide. The substrate 11 and the first dielectric layer 12 were exposed to the second reactant gas mixture for sufficient time, i.e. 8 seconds, to deposit the required thickness of the layer 13, e.g. 4 nm of silicon dioxide, as at 104-3. The flow of the oxidation source gas, i.e. nitrous oxide reactant gas, was then turned off, but the flow of the silicon source gas, i.e. silane, was continued for surface treatment of the deposited silicon dioxide dielectric layer 13, as at 105-1, and then the chamber was purged with the carrier gas (105-2) and cooled (105-3). The sequence was repeated until the required number of periods of first and second dielectric layer pairs 12/13 of the multi-layer device structure 10 or 20 were provided, as at 106.

After preparing the multilayer device structure 10 or 20 by process steps as summarized in FIG. 6, and shown in more detail in FIG. 7, then subsequent process steps 107 may proceed if required, e.g. to provide a light emitting device or other semiconductor device.

Preferably, the duration of the surface treatment with the surface activating reactant gas, e.g. silane, after deposition of each dielectric layer 12 and 13 is long enough to improve flatness, but sufficiently short to avoid formation of a layer of amorphous silicon or polycrystalline silicon on the dielectric surface. For example: for the process conditions summarized in Tables 1 and 2, surface treatment with the silicon source gas for 1 second after turning off the oxidation or nitridation source gases was sufficient to provide improved flatness, although exposure to the silicon source gas for surface treatment or surface activation may be in the range from about 0.5 seconds up to about 10 seconds.

Preferably, for the step 102 of deposition of each of the first and second dielectric layers 12 and 13, to stabilize the chamber, the chamber is preheated (102-1) with a flow of inert or non-reactive carrier gas, i.e. nitrogen, and the flow of the oxidation or nitridation source gas is initiated first before diverting flow of the silicon source gas into the chamber to initiate the reaction for deposition of the required thickness of the respective dielectric layers 12 or 13. After stopping flow of the oxidation or nitration source gas, the deposited layer 12 or 13 is surface treated by exposure to the surface activating reactant gas, e.g. silane. The chamber is purged (103-2) with the carrier gas after the step 103-1 of surface treatment of the deposited dielectric layer 12 or 13 with the silicon source gas. The process according to the embodiment was carried out in a conventional thermal CVD deposition chamber, which provides for the introduction of the carrier gas and/or reactant gas mixture in the upper region for exposure of the substrate for deposition, and a second input for a bottom flow of carrier/purge gas. The carrier gas flow maintains the chamber pressure and flow dynamics, and is continued during surface treatment of deposited layers 12 and 13 with the surface activating reactant gas, e.g. the silicon source gas: silane. Exemplary gas flows and process conditions for deposition of dielectric nano-layer pairs 12 and 13 comprising 5 nm of silicon nitride and 4 nm of silicon dioxide are summarized below, in Tables 1 and 2, respectively.

Similar process steps can also be used for the deposition of a multi-layer light emitting device structure, similar to the multi-layer device 20 shown in FIG. 5, by repeating the process steps for the deposition of twenty-four periods, i.e. twenty four active layer 12/drift layer 13 pairs, of a light emitting structure comprising rare earth doped silicon nitride active layers and silicon dioxide drift layers.

TABLE 1
Deposition of silicon nitride layers
				SiH4
				surface
		NH3 surface	Si3N4	post	N2
	Preheat	pre-treatment	deposition	treatment	purge
Temperature	750	750	750	750	750
(C.)
Pressure	240	240	240	240	240
(Torr)
Time	45	5	11.5	1	35
(second)
N2 (sccm)	13000	13000	13000	13000	10000
N2 bottom	16000	16000	16000	16000	6000
(sccm)
SiH4 (sccm)			17	17
NH3 (sccm)		100	100

TABLE 2
Deposition of silicon dioxide layers
				SiH4
		N2O surface	SiO2	surface	N2
	Preheat	pre-treatment	deposition	treatment	purge
Temperature	750	750	750	750	750
(C.)
Pressure	275	275	275	275	275
(Torr)
Time	80	20	8	1	10
(second)
N2 (sccm)		12000	12000	12000	14000
N2 bottom		10000	10000	10000
(sccm)
SiH4 (sccm)			3.5	3.5
N2O (sccm)		3000	3000

Thus, as illustrated by the TEM photomicrographs shown in FIGS. 4 and 5, a method according to this embodiment provides for improved control of the uniformity, flatness and thickness of thin film dielectric structures 10 and 20 comprising multiple nano-layers, such as active layers 12 and drift layers 13 for light emitting device structures. The surface treatment by the surface activating reactant gas, e.g. silicon source gas: silane, provides for dielectric layers 12 and 13, which are substantially atomically flat, with excellent layer-to-layer reproducibility. RMS surface roughness of <0.21 nm was maintained in the multi-layer device structures 10 and 20.

Notably, the remarkable and unexpectedly large improvement in flatness achieved with the process described above, could not be achieved using conventional known post-deposition treatment processes with oxidation or nitridation source gases. Indeed surface treatment of the deposited silicon nitride or silicon dioxide dielectric layers 12 and 13, which results in the improved flatness and uniformity, appears to be specific to treatment with the silicon source gas: e.g. silane.

By comparison, conventional post-treatment of silicon dioxide layers with the oxidation source gas (nitrous oxide) or post-treatment of a silicon nitride layers with the nitridation gas (ammonia) which has been reported to passivate each layer and terminate active silicon sites for reduced surface roughness, resulted in the rough surface structures, as shown in FIG. 2.

As exemplified by the gas flows listed by way of example in Table 1 and Table 2, during deposition of the silicon nitride or silicon dioxide layers, there is a relatively small flow of silicon source gas relative to the flow of oxidation or nitridation source gas. During surface treatment with the silicon source gas, the flows of nitridation and/or oxidation source gases are turned off, and the flow of silicon source gas is continued, so that the surface of the deposited dielectric is exposed to the silicon source gas only, or at least, a very high ratio of the silicon source gas relative to any residual reactant source gases, i.e. residual oxidation and or nitridation or source gas, that may remain in the chamber during the step of surface treatment.

Surface treatment of the deposited layers 12 and 13 with another silicon source gas, i.e. disilane, did not result in as dramatic an improvement in flatness compared with use of silane. The difference may be attributable to different surface chemistry effects, or may, in part, be due to a higher impurity level of the available disilane source compared with the silane source.

Without wishing to be limited by any particular theory, the present inventors believe that the significant improvement in surface flatness using silane chemistry for deposition, and silane surface treatment of the deposited dielectric layer is primarily due to surface chemistry effects on the dielectric surface, i.e. surface activation of the dielectric surface to create active silicon sites. Thus, it is believed that surface treatment, with silane or other silicon source gases, provides active silicon on the surface, e.g. a monolayer of silicon or a silicon rich surface, that facilitates deposition of subsequent layers with improved layer-to-layer uniformity and reduced surface roughness in multilayer structures. Surface treatment with silane is particularly effective.

While specific embodiments of the method are described above, it will be appreciated that, in other embodiments, similar doped and undoped dielectric layers, such as metal or semiconductor oxides or nitrides, e.g. silicon nitride, silicon dioxide silicon oxynitride, hafnium oxide, zirconium oxide, silicon aluminum oxynitride (SiAlON), and aluminum oxide, may be deposited from other reactant gas mixtures comprising a semiconductor or metal, e.g. silicon, source gas, and one or more reactant source gases, e.g. a nitridation and/or an oxidation source gas, using a range of process conditions, for example, systems and processes as described in the above references United States patents to Applied Materials, or other CVD apparatus and processes. However, instead of a conventional post-deposition treatment by passivation of the surface of each deposited layer with either of the reactant source gases, i.e. nitridation or oxidation sources gases, the deposited layers in embodiments of the invention are surface treated after deposition with a brief exposure to a surface activating gas, i.e. the metal or semiconductor source gas, preferably silane, together with appropriate non-reactive carrier gas(es) to maintain chamber pressure and flow dynamics, to provide active metal or semiconductor on the exposed surface before subsequent processing.

Optionally, dopants may be added to one or more of the first and second dielectric layers 12 and 13, by addition of a suitable dopant precursor to the respective reactant gas mixture. Thus, for light emitting structures in which the first dielectric layers 12 are active layers containing rare earth luminescent centres, for example, a suitable rare earth precursor is added the reactant gas mixture during deposition of the active layers.

Thus, for example, in alternative embodiments for deposition of oxides, nitrides and oxynitrides of silicon by thermal CVD, pressure in the reactor or deposition chamber may be maintained in the range from about 50 Torr to 350 Torr, temperatures in the range from about 400° C. to 900° C., and appropriate flow ratios of silicon source gas and nitridation and/or oxidation source gases in the range 1:50 to 1:10000 to provide a suitable deposition rate, e.g. approximately 30 nm/min to enable sufficient control of the thickness of the deposited layers 12 and 13 of less than 10 nm in deposition times of approximately 10 seconds per layer. The silicon source gas may be silane, disilane, methylsilane, or halogenated silanes, or other suitable silicon source gases, although silane is preferred for the step of surface treatment and surface activation of the deposited dielectric layers 12 and 13. Nitrous oxide, ozone or TEOS may be used as an oxidation source gas, for example Ammonia or hydrazine may be used as a nitridation source gas, for example. The carrier gas may be nitrogen, argon, xenon or helium, for example.

The surface activation treatment with silicon source gas, and silane in particular, is applicable to fabrication other similarly structured dielectric thin films comprising other dielectrics which are compatible with silicon technology, such as, silicon aluminium oxy nitride (SiAlON). For other doped or undoped dielectrics, which have similar surface chemistry, such as other semiconductor or metal oxides, nitrides or oxynitrides, surface treatment by exposure of the deposited dielectric layer to a respective semiconductor or metal source gas to activate the surface before deposition of subsequent dielectric layers may similarly reduce surface roughness and improve layer-to-layer uniformity in multilayer structures.

More generally, in deposition of other thin film dielectric layers, for semiconductor devices comprising oxides, nitrides, or oxynitrides of semiconductors and/or metals, a similar surface activation treatment would be beneficial in improving flatness and layer-to-layer uniformity in deposition of multilayer structures. Typically, a semiconductor or metal containing dielectric is deposited from a reactant gas mixture comprising a first reactant, which is metal/semiconductor (M) source gas, and a second reactant, e.g. at least one of an oxidation and nitridation source gas. Instead of surface passivation with the second reactant, i.e. the oxidation or nitridation source gas, as is conventional, deposition of multilayer structures, according to embodiments of the present invention, includes reducing or stopping the flow of the second reactant, during surface treatment, and to exposing of the deposited dielectric layer to the reactive gas source of the appropriate semiconductor or metal (i.e. cationic) species (M) to provide active species of M, or a monolayer of M, on the surface of a deposited dielectric layer. Thus, when the dielectric layer is deposited from a reactant gas mixture comprising a semiconductor/metal M source gas and one or more of a nitridation and an oxidation source gas, after deposition of a dielectric layer of the required thickness, the flow of the oxidation and nitridation source gases are preferably terminated, and the surface of the deposited layer is treated by continued exposure to the flow of the reactant metal/semiconductor source gas alone, together with appropriate carrier gases to maintain the chamber pressure and flow dynamics. One example would be surface treatment of aluminum oxide dielectric layers (Al₂O₃) with an aluminum source gas.

Light Emitting Device Structures

An engineered structure for a light emitting device 100, as described in the above-referenced copending patent applications by Chik et al, is illustrated in FIGS. 8A and 8B. A multi-layer light emitting structure 200, fabricated similar to the multi-layer structures 10 and 20, comprises one or more first dielectric active layers 12 (as hereinbefore described) comprising rare earth luminescent centres in a host dielectric matrix for emitting light of a first colour or wavelength, and one or more second dielectric active layers 14 comprising rare earth luminescent centres in a host dielectric matrix for emitting light of a second colour or wavelength. First and second dielectric drift layers 13 and 15 are disposed adjacent the first and second dielectric active layers 12 and 14, respectively. Top electrode 21 and back contact electrode 25, respectively, are provided for application of an electric field and current injection for excitation of light emission. In a preferred embodiment, the active layers 12 and 14 comprises a dielectric host matrix containing the rare earth luminescent centres, e.g. rare earth doped silicon nitride containing from 1 at % to 5 at. % of a rare earth species, such as cerium, and the drift layers comprise silicon dioxide. As illustrated, the multi-layer light emitting device structure 200 is provided on the substrate 11, e.g. silicon, which supports the back contract electrode 25. The top electrode 21 is transparent, e.g. ITO, and has electrical contacts 23, and a protective silicon nitride layer 42 deposited thereon. The engineered structure 100 may include a reflective layer 31 between the substrate 11 and the multi-layer light emitting structure 200 or between the substrate 11 and the back contact electrode 25 for reflecting generated light up through the top transparent electrode 21 to improve light extraction. Field oxide regions 28 define a device well region to confine current injection. An encapsulant 35, for example, a semi-spherical or semi-cylindrical mass of a material of a suitable refractive index, e.g. transparent epoxy, over the top electrode 21 acts as a lens to improve light extraction. For efficient impact excitation, corresponding drift layers 13 and 15, adjacent each respective active layer 12 and 14, each has a thickness related to the respective excitation energy of the adjacent active layer 13 and 15.

Deposition of each rare earth doped active layer 12 and 14 and each drift layer 13 and 15 by the chemical vapour deposition methods according to the above described embodiments, including surface treatment of the deposited silicon nitride 12 and 14 and silicon dioxide 13 and 15 layers with silane, provides for improved flatness, layer to layer continuity and lateral continuity of deposited layers.

In variations of the light emitting structure 200 described above, the active layers 12 and 14 may comprise, for example, rare earth doped silicon dioxide, rare earth oxides, or other materials as disclosed in the above referenced related copending applications. The drift layers 13 and 15 may comprise e.g. silicon dioxide or silicon nitride. Selected first and second active layers 12 and 14, may be doped with different rare earth luminescent species for emission of different colours, or active layers 12 and 14 may be co-doped with two or more different rare earth luminescent species, for emission of a light of a specific CRI, e.g. white light. Active layers for these and other light emitting device structures may comprise a concentration of rare earth luminescent centres from 0.1 at. % to about 50 at %. Although this embodiment shows a light emitting structure comprising two layer stacks 12/13 and 14/15 each with a plurality of layer pairs, alternative embodiments may comprise additional stacks of active layer/drift layer pairs comprising rare earth luminescent centres for producing light of different colors and wavelengths or for light emission of a particular CRI.

Preferred rare earth luminescent centres comprise one or more of Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm or Yb. One or more selected rare earth luminescent centre is incorporated into the reactant gas mixture for deposition of the active layers, 12 or 14, by including a suitable rare earth precursor, e.g. a metal organic precursor compound which is sufficiently volatile at the required deposition temperature and pressure.

Examples of rare earth precursors are disclosed, for example, in United States published patent application no. US2007/0181906 published Aug. 9, 2007 in the name of Chik et al, which is incorporated herein by reference. Suitable ligands for the rare earth element may include acetate functions, for example 2,2,6,6-tetramethyl-3,5-heptanedione, acetylacetonate, fluorolacetonate, 6,6,7,7,8,8,8-heptafluoro-2,2-dimethyl-3,5-octanedione, i-propylcyclopentadienyl, cyclopentadienyl, and n-butylcyclopentadienyl.

Typically, each active layer 12 and 14 has a thickness from 1 nm to 10 nm, although active layers 12 and 14 may be as thin as one monolayer (one atomic layer), and each drift layer 13 and 15 typically has a thickness from 2 nm to 10 nm to provide an appropriate electron excitation energy, as explained above. For electroluminescent light emitting device structures, electrodes are provided for applying a suitable electric field, which may be about 5 MV/cm to 8 MV/cm or more, for excitation of luminescent centers. Active layer/drift layer pairs 12/13 or 14/15 and electrodes may be configured for operation with an AC or DC voltage.

The thickness of the drift layers 13 and 15 are determined as a function of the wavelength, and therefore of the required excitation energy of the corresponding active layers 12 and 14 For an electric field applied perpendicular to the plane of the active layers 12 to 14, an electron must gain sufficient energy from the applied electrical field to excite the luminescent centers to the correct energy, i.e. in the ballistic regime, the energy gained in the drift layers 13 and 15 (measured in eV) is equal to the electric field multiplied by the thickness of the drift layer 12 or 14. Accordingly, the drift layers 13 adjacent active layers 12 may have a different thickness than the drift layers 15 adjacent the active layers 14. For example, for an applied electrical field of 5 MV/cm, the thickness of the drift layer must be 3.8 nm or thicker to excite a luminescent center to 1.9 eV (1.9 eV/0.5 eV/nm=3.8 nm), 4.6 nm or thicker to excite a luminescent center to 2.3 eV, or 5.6 nm or thicker to excite a luminescent center to 2.8 eV. For layered light emitting film structures 100 powered by AC electrical power, in which neighboring active layers, e.g. 12 and 14, emit at different wavelengths, the intervening drift layer, e.g. 13, must be thick enough for excitation of the luminescent centers in the higher energy layer.

Chemical vapour deposition is a preferred for commercial production of such multi-layer light emitting structures 200 at reasonable cost. Methods of fabrication of the emitter layer structure 200 comprising multiple active layer/drift layer pairs 12/13, 14/15 according to the embodiments of the present invention comprising surface treatment or activation of deposited dielectric layers with the metal or semiconductor source gas, e.g. silane, overcome limitations mentioned above of known commercial thermal CVD processes and apparatus. Improved flatness of deposited dielectric layers 12 to 15 enables scalability of multilayer nano-layer dielectric structures to a larger number of layers, e.g. 24 layer pairs or more, without breakdown of the uniformity of layer structure and thickness.

Other Electronic Device Structures Using Undoped or Rare Earth Doped Dielectrics.

As disclosed in copending provisional patent application No. 61/187,424 entitled “Cerium doped gate oxide layers”, filed Jun. 16, 2009, high quality, thin, rare earth doped dielectric layers, particularly oxide layers, may also have applications for gate oxides and tunnel oxides other electronic devices such as transistors, memory cells and flash devices. Preparation of such oxides by use of silane chemistry and silane surface treatment to provide nano-layers, which are substantially atomically flat, would also be beneficial for such structures.

Other device structures where a dielectric layer such as a layer of doped or undoped silicon dioxide, nitride, or oxynitride, or other dielectric provides a gate oxide, tunnel oxide, capacitor dielectric, may also benefit from chemical vapour deposition with surface activation treatment as disclosed above, to provide dielectric thin films or nano-layers with improved flatness and uniformity.

Alternative Embodiments

While the specific embodiments described in detail above are directed to light emitting devices, emitter structures and electroluminescent active layers comprising rare earth doped silicon dioxide or silicon nitride, it will be apparent that atomically flat, doped or undoped thin dielectric layers of high quality potentially have a number of other uses, e.g. as gate oxides and gate layer stacks for other electronic device structures, or for gate oxides and tunnel oxides for memory and flash devices. Thin dielectric layers fabricated by methods according to embodiments of the present invention may comprise luminescent species, such as rare earth ions or other light emitting species, that may also find application for light emitting diodes, optically excited light emitting devices, lasers, optical modulators and amplifiers, for example.

INDUSTRIAL APPLICABILITY

Improved chemical vapour deposition processes are provided for deposition of high quality nano-layers of dielectric materials, and particularly oxides and nitrides of silicon for light emitting device structures and other electronic devices. Low surface roughness and substantially atomically flat and abrupt layer structures provide for improved control of layer thicknesses and uniformity, particularly for multilayer stacks of thin film dielectrics. For light emitting device structures, improved quality and flatness of doped and undoped thin dielectric layers potentially offer improved performance, such as higher luminous efficacy, brightness, and reliability for solid-state lighting applications.

Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims.

Claims

1. A method of fabricating a thin film dielectric structure for a semiconductor device comprising: a) depositing a first layer, comprising a first dielectric, on a substrate; andb) surface treating the first layer with a surface activating reactant gas.

2. The method according to claim 1, wherein for step b) the surface activating reactant gas comprises a first reactant source gas of a semiconductor or metal constituent of the first dielectric.

3. The method according to claim 1, wherein the first dielectric layer comprises a dielectric compound of a metal or semiconductor; wherein step a) comprises depositing the first layer from a flow of a reactant gas mixture comprising a first reactant source gas of the metal or semiconductor and at least one second reactant source gas; andwherein step b) comprises reducing flow of the at least one second reactant source gas, and surface treating the first layer with a surface activating gas consisting essentially of the first reactant source gas of the metal or semiconductor.

4. The method according to claim 1, wherein the first dielectric comprises an oxide, a nitride or an oxynitride of a metal or semiconductor; wherein step a) comprises depositing the first layer from a reactant mixture comprising a first reactant source gas of the metal or semiconductor, and at least one second reactant source gas selected from the group consisting of an oxidation source gas and a nitridation source gas, andwherein step b) comprises terminating flow of the second reactant source gas and exposing the first layer to the first reactant source gas for surface activation of the first layer.

5. The method according to claim 2, wherein step b) comprises exposing the first layer to the first reactant source gas of the semiconductor or metal for a duration sufficient to cause surface activation and insufficient to cause deposition of a surface layer of amorphous or polycrystalline metal or semiconductor material.

6. The method according to claim 2, wherein step b) comprises exposure to the first reactant source gas only for sufficient time to form a monolayer of reactive species on a surface of the first layer.

7. The method according to claim 2, further comprising: c) depositing a second layer, comprising a second dielectric material, on the first layer from a second reactant gas mixture comprising the first reactant source gas and at least one second reactant source gas, andd) surface treating the second layer by exposure to the first reactant source gas as in step b)

8. The method according to claim 7, further comprising depositing a plurality of layer pairs, each pair comprising one of said first layers and one of said second layers wherein surface treatment is conducted after deposition of each first and second layer before deposition of a subsequent layer.

9. The method according to claim 7, wherein said first and second layers comprise active layers and drift layers, respectively, of a light emitting structure, and wherein step a) further comprises depositing said active layers from a reactant gas mixture including a precursor source gas for doping of the first layers with rare earth luminescent centres.

10. The method according to claim 9, wherein step a) comprises depositing active layers comprising rare earth doped silicon nitride, and wherein step c) comprises depositing drift layers comprising silicon dioxide.

11. The method according to claim 1, wherein the first dielectric comprises a silicon containing dielectric, and wherein step b) comprises exposing a surface of the first layer to a silicon source gas.

12. The method according to claim 11, wherein the silicon source gas comprises silane.

13. The method according to claim 1, wherein the first layer comprises an active layer of a light emitting structure comprising luminescent centres, and wherein step a) further comprises depositing said first layer from a reactant gas mixture including a precursor source gas for said luminescent centres.

14. The method according to claim 1, wherein the first dielectric layer is comprised of doped or undoped oxides, nitrides or oxynitrides of a semiconductor or metal compatible with silicon process technology.

15. A method of depositing, by chemical vapour deposition (CVD) in a CVD reaction chamber, a thin film dielectric stack comprising: a) providing a substrate;b) depositing a first dielectric layer of a first desired thickness by exposure of the substrate to a first reactant gas mixture comprising a silicon source gas and at least one of one of a nitridation source gas and an oxidation source gas;c) surface treating the first dielectric layer by exposure to the silicon source gas;d) depositing a second dielectric layer of a second desired thickness by exposure to a second reactant gas mixture comprising a mixture of a silicon source gas and at least one of one of a nitridation source gas and an oxidation source gas; ande) surface treating the second dielectric layer by exposure to the silicon source gas.

16. The method according to claim 15, further comprising repeating steps b) to e) in sequence to provided a plurality of first and second dielectric layer pairs.

17. The method according to claim 15, wherein steps c) and e) each comprise exposing the first or second dielectric layer to the silicon source gas for a duration sufficient to cause surface activation and insufficient to cause deposition of a surface layer of amorphous or polycrystalline silicon.

18. The method according to claim 15, comprising depositing each of the first and second dielectric layers as substantially atomically flat layers, characterized by a surface roughness less than 0.21 nm.

19. The method according to claim 15, wherein at least one of said first and second dielectric layers comprises a rare earth dopant.

20. The method according to claim 19, wherein step b) further comprises depositing said first dielectric layer from a reactant gas mixture including a rare earth precursor.

21. The method according to claim 15, wherein each of the first and second dielectric layers comprises a material selected from the group consisting of doped and undoped oxides, nitrides and oxynitrides of silicon.

22. The method according to claim 15, wherein each of the first and second dielectric layers is deposited with a thickness in the range from 1 monolayer to about 10 nm.

23. A semiconductor device structure comprising a thin film dielectric structure comprising a plurality of first and second dielectric layers deposited by the method of claim 8.

24. The semiconductor device structure according to claim 23, wherein the thin film dielectric structure comprises one of a gate oxide, a tunnel oxide, a capacitor dielectric, and a light emitting structure.

25. A semiconductor device structure comprising a thin film dielectric stack comprising: a first dielectric layer, comprised of an amorphous or non-crystalline nitride, oxide or oxynitride of a semiconductor or metal;a second dielectric layer, comprised of an amorphous or non-crystalline nitride, oxide or oxynitride of a semiconductor or metal, andan interface between the first and second dielectric layers comprised of a monolayer of the semiconductor or metal, and characterized by a surface roughness less than 0.21 nm;whereby each of said first and second dielectric layers comprises a substantially atomically flat layer.

26. The semiconductor device structure according to claim 25, wherein the dielectric stack is comprised of a plurality of said first and second dielectric layer pairs.

27. The semiconductor device structure according to claim 25, wherein each of the first and second dielectric layers is comprised of a material selected from the group consisting of doped and undoped oxides, nitrides and oxynitrides of silicon.

28. The semiconductor device structure according to claim 25, wherein each first dielectric layer comprises an active layer, which include luminescent centres.

29. The semiconductor device structure according to claim 28, wherein each active layer has a thickness from 1 monolayer to 10 nm.

30. The semiconductor device structure according to claim 29, wherein the second dielectric layers comprise drift layers, and each drift layer has a thickness from 2 nm to 10 nm.

31. The semiconductor device structure according to claim 28, wherein each active layer includes a concentration of rare earth luminescent centers in the range from 0.1 at. % to 50 at. %.

32. The semiconductor device structure according to claim 28, wherein each active layer includes a concentration of rare earth luminescent centers in the range from 1 at. % to 5 at. %.

33. The semiconductor device structure according to claim 30, wherein the rare earth luminescent centres are selected from the group consisting of Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb.