Patent Application
20250125216
The present application is based on and claims priority to Taiwanese Application Number 112138720, filed Oct. 11, 2023, the disclosure of which is hereby incorporated by reference herein in its entirety.
This disclosure relates to a die and a manufacturing method thereof as well as a semiconductor package with the same, and more particularly relates to a die that may prevent separation from a molding layer and a manufacturing method thereof as well as a semiconductor package with the same.
Referring to
A heat spreader (not shown) may be disposed on the top of the above-described semiconductor package to help dissipate heat from the die 110. However, since the molding layer 140 does not cover the top of the die 110, the difference in coefficient of thermal expansion between the die 110 and the molding layer 140 results in the side surfaces of the die 110 easily separating from the molding layer 140.
In view of the above, the present disclosure provides a die and a manufacturing method thereof as well as a semiconductor package with the same, in order to solve the above problems.
In one embodiment, the die of the present disclosure has a top surface, a plurality of side surfaces, a bottom surface, a circuit layer and a platform. The bottom surface is connected to the side surfaces. The circuit layer is formed on the bottom surface. The platform is disposed around the top surface and is parallel to the top surface and the bottom surface. The distance from the platform to the bottom surface is less than that from the top surface to the bottom surface. The platform is perpendicularly connected to the side surfaces.
In one embodiment, the semiconductor package of the present disclosure includes a substrate, the above die, a plurality of metal bumps and molding layer. The die is disposed on the substrate. The metal bumps are disposed between the substrate and the bottom surface of the die and are electrically connected to the circuit layer of the die. The molding layer is formed on the substrate to cover the side surfaces and the platform of the die, wherein the molding layer exposes the top surface of the die.
In one embodiment, the method of manufacturing a die according to the present disclosure comprises: providing a wafer having a front surface and a back surface opposing to the front surface, wherein a circuit layer is formed on the front surface; grinding the back surface of the wafer with a grinding bit to thin the wafer to a predetermined thickness; forming a plurality of grooves on the back surface of the wafer; and dicing the wafer from the front surface to the grooves with a dicing blade.
In the semiconductor package of the present disclosure, as the molding layer covers the platform, it hooks onto the die like a hook so that the die is not easily separated from the molding layer.
The foregoing, as well as additional objects, features and advantages of the disclosure will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatial relative terms, such as “beneath.” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein may likewise be interpreted accordingly.
In this disclosure, the symbol “>” denotes greater than, the symbol “<” denotes less than, the symbol “≥” denotes greater than or equal to, and the symbol “≤” denotes less than or equal to.
Referring to
More specifically, the die 210 has a top surface 211, a bottom surface 212, and a plurality of side surfaces 213, wherein the bottom surface 212 is an active surface having a circuit layer 216 thereon. The top surface 211 and the bottom surface 212 are located on different planes. The bottom surface 212 is perpendicularly connected to the side surfaces 213. The circuit layer 216 of the die 210 is electrically connected to the substrate 220 through the metal bumps 230.
In addition, the die 210 further has a platform 250, which is disposed around the top surface 211. The platform 250 is substantially flat and parallel to the top surface 211 and the bottom surface 212. The distance from the platform 250 to the bottom surface 212 is less than that from the top surface 211 to the bottom surface 212. It means the platform 250 is lower than the top surface 211. Therefore, a step is formed between the top surface 211 and the platform 250. An outer peripheral edge 253 of the platform 250 is connected to the side surfaces 213. The platform 250 is perpendicularly connected to the side surfaces 213.
A molding layer 240 is formed on the substrate 220. The molding layer 240 is made of a molding material, such as epoxy resin, but is not limited thereto. The molding layer 240 has opposing top surface 241 and bottom surface 242, wherein the bottom surface 242 in in contact with the substrate 220. The molding layer 240 is formed to cover the side surfaces 213 and platform 250 of the die 210, and is not formed on the top surface 211 of the die 210. The molding layer 240 exposes the top surface 211 of the die 210. The top surface 241 of the molding layer 240 is connected to the top surface 211 of the die 210 and is flush with the top surface 211 of the die 210.
The semiconductor package of the present disclosure further includes a heat spreader 260 attached to the top surface 211 of the die 210. The heat spreader 260 may be made of copper or other thermally conductive materials to help dissipate heat from the die 210. In addition, a plurality of solder balls 270 is disposed on the bottom surface of the substrate 220. The solder balls 270 are electrically connected to the substrate 220. The die 210 may be electrically connected to an external circuit through the substrate 220 using the solder balls 270.
According to the semiconductor package of the present disclosure, the distance from the top surface 211 to the platform 250 of the die 210, i.e., the depth of the platform 250 is defined as d. The distance from the top surface 211 to the bottom surface 212 of the die 210, i.e., the thickness of the die 210 is defined as D, where D has the following relationship with d:
In the semiconductor package of the present disclosure, as the molding layer covers the platform, it hooks onto the die like a hook so that the die is not easily separated from the molding layer.
Referring to
Afterwards, as shown in
Next, as shown in
Next, as shown in
In one embodiment, the thickness D of the wafer 310 and the depth d of the grooves 370 have the following relationship:
In another embodiment of the present disclosure, the grooves 370 may be formed on the back surface 311 of the wafer 310 before the wafer 310 is thinned.
Next, as shown in
In one embodiment, the width W1 of the grooves 370 and the thickness W2 of the dicing blade 392 have the following relationship:
The die 210 obtained above may be disposed on a substrate 220 through flip chip technology, and be electrically connected to the substrate 220 by a plurality of metal bumps 230. Thereafter, a molding layer 240 is formed on the substrate 220 and a plurality of solder balls 270 is formed on the bottom surface of the substrate 220. A heat spreader 260 is attached to the top surface 211 of the die 210. Finally, a semiconductor package as shown in
Although the preferred embodiments of the disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as disclosed in the accompanying claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112138720 | Oct 2023 | TW | national |
