Embodiments relate generally to a die package and a method for manufacturing the die package.
The primary trend in electronics industry is product miniaturization. Both design and manufacturing engineers are looking for ways to make electronic products lighter, smaller, less expensive, and at the same time faster, more efficient, more reliable, more user-friendly, and more functional. Today, electronic products such as cellular phones, personal and sub-notebook computers, pagers, Personal Computer Memory Card International Association (PCMCIA) cards, camcorders, palmtop organizers, telecommunications equipments, and automotive components are being made more and more compact.
With silicon chips integrating more functionality as per Moore's Law, the electronics industry is being challenged to integrate and shrink the packaging. Chips First or Embedded Chip packaging is one way to overcome the recent packaging integration challenges. Packaging researchers have worked on embedded packaging and developed a new way of embedding the chip. Plastic ball grid array (PBGA) packages have replaced the lead frame based peripheral array packages. In PBGA packages, a die is electrically connected to a circuit board (PCB) substrate by wire bonding or flip chip technology before covering with a molding compound. Embedded wafer level packaging eliminates the need of using the PCB substrate and wire bonding or flip-chip bumps to establish electrical connections. By removing the PCB substrate, packaging cost is reduced and electrical performances are improved.
However, most of the known technologies focused only on two-dimensions (2D) embedding. Further, there is no known technology for embedding passives and other structures required for system in package (SiP) integration in a cost effective manner.
In one conventional method, embedding singulated die based on PCB technology has been adopted. The singulated die is first attached onto a copper (Cu) base plate in a cavity of a PCB substrate and the subsequent Cu rewiring and vias are then built up on top of the active side based on the PCB technology. Finally, solder balls are formed on top of the Cu pads for electrical interconnection.
Another conventional method is based on wafer level processing. The fabrication method involves attaching singulated dies with active top side down onto a thermo-sensitive adhesive material coupled to a carrier plate. A wafer molding process is then used to encapsulate the attached dies on the carrier plate. The carrier plate is then separated and the dies are housed in a mold compound, forming a reconstituted wafer. A redistribution layer can be formed on the reconstituted wafer using conventional lithographic process. Solder bumps can also be formed on the wafer level prior to singulation.
However, fine feature size may be a challenge for the above-mentioned technologies, and there may be problems in the supply chain for the conventional technologies. Further, the conventional technologies focused on single die or 2D integration only. The conventional technologies are not implementable for Microelectromechanical systems (MEMS), photonics and other applications.
Since current and future innovations in packaging format will be critical to miniaturizing electronic products, there is a need to provide a new packaging method which partially overcomes at least one of the above-mentioned problems. It will also be desirable to provide a new packaging method for embedding actives and passives that will help to enable future advances in chip speed and circuit functionality.
In an embodiment, there is provided a method for manufacturing a die package, the method including: arranging a second die above a first die, the first die including an interconnect region on a surface facing the second die, wherein the second die is arranged laterally next to the interconnect region of the first die; forming a first package-internal free-standing interconnect structure on or above the interconnect region of the first die; forming a second package-internal free-standing interconnect structure on or above an interconnect region of the second die, the interconnect region of the second die being on a surface of the second die facing away from the first die; and forming package material partially around the first package-internal free-standing interconnect structure and the second package-internal free-standing interconnect structure such that a connecting portion of the first package-internal free-standing interconnect structure and a connecting portion of the second package-internal free-standing interconnect structure remains uncovered to be electrically connected to a package-external interconnect structure.
In another embodiment, there is provided a die package including: a second die arranged above a first die, the first die including an interconnect region on a surface facing the second die, wherein the second die is arranged laterally next to the interconnect region of the first die; a first package-internal free-standing interconnect structure disposed above the interconnect region of the first die; a second package-internal free-standing interconnect structure disposed above an interconnect region of the second die, the interconnect region of the second die being on a surface of the second die facing away from the first die; and package material formed partially around the first package-internal free-standing interconnect structure and the second package-internal free-standing interconnect structure such that a connecting portion of the first package-internal free-standing interconnect structure and a connecting portion of the second package-internal free-standing interconnect structure remains uncovered to be electrically connected to a package-external interconnect structure.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the various embodiments. In the following description, various embodiments are described with reference to the following drawings, in which:
a to 3j show schematic diagrams of a process for manufacturing the die package at the wafer level.
a shows a schematic diagram of chip passives embedded within the package material of the die package.
b shows a schematic diagram of chip passives embedded on the package material of the die package.
a shows a schematic diagram of chip passives and a thin film passive embedded within the package material of the die package.
b shows a schematic diagram of chip passives embedded on the package material of the die package and a thin film passive embedded within the package material of the die package.
a and 17b show schematic diagrams of a die package having dies of the same size.
Exemplary embodiments of a die package are described in detail below with reference to the accompanying figures. It will be appreciated that the exemplary embodiments described below can be modified in various aspects without changing the essence of the invention.
In an embodiment as described below in
Package material such as e.g. ceramic, plastic, epoxy, 124 may be formed around the dies 102, 104, 106 and the respective interconnect structures 108, 110, 112 such that respective connecting portions 126, 128, 130 of the interconnect structures 108, 110, 112 are not covered by the package material 124. A redistribution layer 132 may be formed on the connecting portions 126, 128, 130 of the interconnect structures 108, 110, 112. Metallic interconnects, e.g. in the form of solder bumps 134 may be formed on the redistribution layer 132. An insulating dielectric layer 142 may be formed on the redistribution layer 132. In order to form a multilayer redistribution layer, a multilayer dielectric layer 142 may be used for isolation and redistribution.
The structure of the die package 100 is not limited to the embodiment as shown in
b shows that the second interconnect structure 1712 may be further disposed above a further interconnect region 1718 on the main processing surface 1716 of the second die 1704. The interconnect region 1714 and the further interconnect region 1718 of the second die 1704 may be on two opposite ends of the main processing surface 1716 of the second die 1704 facing away from the first die 1702.
In the embodiment as described below in
The number of dies and the number of interconnect structures for each die can be different in different embodiments. Further, the shapes of the interconnect structures can be different in other embodiments. The interconnect structures can also be made of other electrically conductive materials.
A method for manufacturing the die package at a wafer level is described in the following. The method described below is used for manufacturing the die package 100 as shown in
a to 3j show schematic diagrams of the process for manufacturing the die package 100 at the wafer level. After the device wafers 202 are diced into individual dies, the dies of good working condition are selected and are attached to a support wafer or tape for reconstruction to a wafer form. A person skilled in the art will be able to determine the dies of good working condition by e.g. testing the dies to determine if the dies have certain characteristics, e.g. long operating life, etc.
a shows a schematic diagram of a tape 302 used for reconstruction to the wafer form. The tape 302 is one which can withstand high temperatures, e.g. in the range from about 100° C. to about 210° C.
c shows that a second die 104 is then disposed above the respective first die 102 and laterally between the interconnect structures 108 of the respective first die 102. Each second die 104 may include a plurality of, e.g. two interconnect structures 110. The interconnect structures 110 of each second die 104 may be disposed on two opposite ends of a main processing surface 116 of each second die 104 facing away from the respective first die 102. Referring back to
d shows that a third die 106 may be disposed above the respective second die 104 and laterally between the interconnect structures 110 of the respective second die 104. Each third die 106 may include a plurality of, e.g. two interconnect structures 112. The interconnect structures 112 of each third die 106 may be disposed on two opposite ends of a main processing surface 118 of each third die 106 facing away from the respective second die 104. Referring back to
e shows that a package material 124 is formed around the dies 102, 104, 106 and the respective interconnect structures 108, 110, 112 such that upper regions 308, 310, 312 of the interconnect structures 108, 110, 112 remain uncovered from the package material.
h shows that a redistribution layer 132 may then be formed on the respective connecting portions 126, 128, 130 of the interconnect structures 108, 110, 112. Using the redistribution layer 132 enables the removal of wire bonds or flip chip interconnects. The redistribution layer 132 interconnects the I/O pads of the dies 102, 104, 106. An insulating dielectric layer 142 may be formed on the redistribution layer 132. In order to form a multilayer redistribution layer, a multilayer dielectric layer 142 may be used for isolation and redistribution.
There are different variations of the die package 100 manufactured by the method described above. One variation of the die package 100 is embedding chip passives within the package material 124 of the die package 100.
b shows a schematic diagram of the chip passives embedded on the package material 124 of the die package 100. The chip passives including but not limited to a capacitor 502, a resistor 504 and an inductor 506 are embedded on a surface 508 of the package material 124, which is opposite to the surface 510 having the redistribution layer 132 and the solder bumps 134.
Another variation of the die package 100 is embedding thin film passives using wafer level redistribution layer processes as described above.
Other components including but not limited to heat spreaders, package antennas and electromagnetic interference (EMI) shields can also be embedded within the package material 124 of the die package 100.
In addition, the die package 100 in an embodiment allows multiple die stacking in two-dimension (2D) and three-dimension (3D) configurations.
In addition, the die package 100 can be implemented in various applications including but not limited to mobile, memory, processor, microelectromechanical system (MEMS), optical and radio frequency (RF) applications.
The die package 1400 may include a plurality of interconnect structures (e.g. two interconnect structures) 1432. The interconnect structures 1432 may be disposed on two opposite ends of the die package 1400. The interconnect structures 1432 may extend from the conductive layer 1418 to the redistribution layer 1414. The MEMS chip 1402, the memory chip 1404 and the ASIC chip 1406 may be electrically connected to the redistribution layer 1414 via the conductive layer 1418 and the interconnect structures 1432.
An insulating dielectric layer 1434 may be formed on the redistribution layer 1414. Metallic interconnects in the form of solder balls 1436 are formed on the redistribution layer 1414.
The die package 1500 may include a plurality of interconnect structures (e.g. two interconnect structures) 1532. The interconnect structures 1532 may be disposed on two opposite ends of the die package 1500. The interconnect structures 1532 may extend from the conductive layer 1518 to the redistribution layer 1514. The optical sensor chip 1502, the optical driver and EIO converter 1504 and the ASIC or logic chip 1506 may be electrically connected to the redistribution layer 1514 via the conductive layer 1518 and the interconnect structures 1532.
An insulating dielectric layer 1534 may be formed on the redistribution layer 1514. Metallic interconnects in the form of solder balls 1536 may be formed on the redistribution layer 1514.
The die package 1600 may include a plurality of interconnect structures (e.g. two interconnect structures) 1632. The interconnect structures 1632 may be disposed on two opposite ends of the die package 1600. The interconnect structures 1632 may extend from the conductive layer 1618 to the redistribution layer 1614. The RF chip 1602, the logic chip 1604 and the memory chip 1606 may be electrically connected to the redistribution layer 1614 via the conductive layer 1618 and the interconnect structures 1632.
An insulating dielectric layer 1634 may be formed on the redistribution layer 1614. Metallic interconnects in the form of solder balls 1636 may be formed on the redistribution layer 1614.
The structure of the die package and the method of manufacturing the die package may enable a wafer level reconstruction of the wafer and conventional wafer level processing can be carried over it. The method of manufacturing the die package may achieve a higher level of dies and passives integration in a smaller footprint. The method also may allow both 2D and 3D integration of the dies. The method may be suitable for multi-die, stack die and single die embedding and for fine pitch features. A lower cost may be incurred due to the simpler design and fabrication processes. There is also flexibility with the processes and the materials used for manufacturing the die package. Further, wafer level testing can be more easily conducted using the interconnect structures.
While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
Number | Date | Country | Kind |
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2007-212505 | Aug 2007 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/SG2008/000297 | 8/12/2008 | WO | 00 | 12/30/2010 |
Number | Date | Country | |
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60955795 | Aug 2007 | US |