1. Technical Field
This disclosure relates generally semiconductor devices, and more particularly to multi-die modules.
2. Description of the Related Art
Capacity of device packages such as, for example, DDR memory packages, may be improved by increasing the quantity of integrated circuit dies per package. For example, one or more pairs of stacked dies may be implemented within a memory packages to increase the memory capacity as compared to memory packages having unstacked dies, without significantly increasing the footprint of the package. Such stacked memory packages typically employ wire bonding for connecting dies to a module substrate.
Flip chip connection of integrated circuit (IC) devices may provide desirable inductance characteristics (e.g., lower signal and/or power inductance). Also, connection density may be much greater than that which is possible with wire bonded integrated circuit devices. Flip chip connections may use conductive bumps disposed on one surface of a die to facilitate connection to a substrate. Thus, flip chip connections may not be well suited for typical stacked die configurations.
Various structures and techniques providing semiconductor device packages having two or more integrated circuit dies mounted on opposing sides of a substrate are disclosed. These integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. In certain embodiments, the disclosed structures and techniques may facilitate higher device density within a package, while providing reduced inductance values and improved connector density.
One embodiment of an electronic device module may include a first die electrically connected to a first surface of a module substrate via a flip chip connection, and a second die electrically connected to a second, substantially opposite surface of the module substrate, also via a flip chip connection. Particular embodiments may further include conductors on the first side of the module substrate to facilitate connection of the electronic device module to external components. Other embodiments may include conductors disposed on one or more surfaces of the module substrate other than the first surface for external connection. Some embodiments may be configured for external connection via conductors disposed at more than one surface of the module substrate. For example, one such embodiment may be a memory module including two or more DDR dies flip chip mounted on opposite surfaces of a module substrate, where the memory module is configured for connection to a system module that includes a system-on-a-chip (SOC). The particular memory module may in some cases be further configured for connection to a third module, such as an another memory module, thereby facilitating a system that in includes the SOC and the two memory modules.
In particular embodiments, an electronic device module may include a first integrated circuit electrically connected to a first set of conductors of a module substrate, and a second integrated circuit electrically connected to a second set of conductors of the module substrate. The first and second set of conductors may be disposed on substantially opposite surfaces of the module substrate, and may be electrically connected to the first and second integrated circuits using conductive bumps, such as solder bumps. Some embodiments may include additional integrated circuits electrically connected to the module substrate. In some embodiments, the module substrate further includes one or more sets of electrical conductors that are configured for external connection (e.g., for connection to SOC modules, memory modules, or other modules). The one or more sets of electrical conductors may in some cases be configured for connection using one or more ball grid arrays.
In some embodiments of the present disclosure, a system may include a first module electrically connected to a second module. The modules may be connected via a set of electrical conductors disposed at a first module substrate. In addition to the first module substrate, the first module may include a first die and a second die. The first and second die may respectively be electrically connected to opposite surfaces of the first module substrate via flip chip connections. In some embodiments, the second module may include a SOC. The first module may be a memory module in various embodiments.
The following detailed description makes reference to the accompanying drawings, which are now briefly described.
Specific embodiments are shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the claims to the particular embodiments disclosed, even where only a single embodiment is described with respect to a particular feature. On the contrary, the intention is to cover all modifications, equivalents and alternatives that would be apparent to a person skilled in the art having the benefit of this disclosure. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise.
The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). The words “include,” “including,” and “includes” indicate open-ended relationships and therefore mean including, but not limited to. Similarly, the words “have,” “having,” and “has” also indicated open-ended relationships, and thus mean having, but not limited to. The terms “first,” “second,” “third,” and so forth as used herein are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless such an ordering is otherwise explicitly indicated. For example, a “third die electrically connected to the module substrate” does not preclude scenarios in which a “fourth die electrically connected to the module substrate” is connected prior to the third die, unless otherwise specified. Similarly, a “second” feature does not require that a “first” feature be implemented prior to the “second” feature, unless otherwise specified.
Various components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation generally meaning “having structure that” performs the task or tasks during operation. As such, the component can be configured to perform the task even when the component is not currently performing that task (e.g., a set of electrical conductors may be configured to electrically connect a module to another module, even when the two modules are not connected). In some contexts, “configured to” may be a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the component can be configured to perform the task even when the component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits.
Various components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph six, interpretation for that component.
The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
Turning to
Electronic device module 10 may provide configurability to system 1. For example, consider a prior system in which a processor and memory are disposed in a common package, on a common substrate. In such as system, inventory of common packages that include fixed configurations of processor and memory may be required to satisfy product demand within an acceptable lead time. Many fixed configuration representing the various combinations of processor and memory may be required. The stored inventory of fixed configurations may represent an inventory risk due to possible component price changes, component product evolution, and component obsolescence. For example, stored common packages including a particular memory integrated circuit may become undesirable due to the release of better performing memory, or a change in price.
A present exemplary system using a memory module and a processor module may reduce inventory risk by enabling storage of reduced inventory resulting from shorter lead time associated with assembly of a system from the various modules. Furthermore, as components of specific modules become obsolete, other modules of the present exemplary system are not affected. For example, an obsolescence of a particular memory product causes the obsolescence of only corresponding memory modules, and not of processor modules or other memory modules.
In contrast, inventory of the above-discussed prior common package may become obsolete due to obsolete memory being integrated into the common package. Because the processor is also integrated to the common package, the possible obsolescence of memory also causes inventory risk related the integrated processors.
Furthermore, the modules of the present embodiments may provide preferable units for testing and procurement. For example, a memory module in accordance with the present disclosure that is provided by a memory supplier presents an opportunity for that memory supplier to conduct quality assurance at the module level, instead of only at the die level. Accordingly, efficiencies can be gained through the higher-level testing performed by the supplier prior to delivery to the customer. Therefore, various risks associated with defect creation during assembly may be shifted to the module supplier.
Electrical connection between electronic device module 10 and module 20 via module conductors 130 may be accomplished using various interconnect formats. For example, embodiments of system 1 may include electronic device module 10 and module 20 electrically coupled using ball grid array, pin grid array, land grid array, dual in-line package, or other suitable interconnect form factors. In some cases, embodiments of system 1 may include multiple module conductors 130 employing multiple, differing interconnect formats. Module conductors 130 may be arranged symmetrically with respect to surface 110 of module substrate 100 (see
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Conductive bumps 210 may include solder bumps providing electrical connection between integrated circuit dies 200 and module substrate 100 by way of a flip chip connection formed using, for example, ultrasonic of reflow solder processes. In some embodiments, a flip chip connection may be formed using other bumps (e.g., gold stud bumps) and other processes (e.g., conductive film or tape).
Use of flip chip connections provides several advantages over alternative connection methods. For example, flip chip connections may be much shorter than wire bonded connections. Accordingly, designs providing lower inductance values (e.g., power inductance and signal inductance) may be achieved. Furthermore, the availability of an entire side of a die for placement of conductive bumps in a flip chip implementation provides an opportunity for higher conductor density (e.g., a larger number of input/output signals and power/ground signals) than is typically possible with wire bonding.
The mounting of integrated circuit dies 200 on opposing sides of module substrate 100 may allow increased density of integrated circuit dies 200 within a particular footprint for electronic device module 10 and system 1. The dense configuration that may be facilitated by such double-sided mounting of integrated circuit dies 200 may accommodate compact design constraints imposed in form factor-sensitive implementations, such as mobile devices. Various integrated circuit dies 200 mounting configurations may be used in specific embodiments of electronic device module 10, including symmetric or asymmetric configurations of varying quantities of dies. For example,
In some embodiments, electronic device module 10 may include multiple identical integrated circuit dies 200 mounted on module substrate 100. One such embodiment is a memory module in which identical memory integrated circuits may be used to provide storage for use by a system-on-a-chip. Other embodiments of electronic device module 10 may include a variety of integrated circuit dies 200 mounted on module substrate 100. For example, a particular memory module may be configured to a provide separate system memory and graphics memory to a coupled system. In this particular exemplary memory module, the system memory may be provided using one or more of a particular integrated circuit, and the graphics memory may be provided using one or more a different integrated circuit. Other embodiments of electronic device module 10 may include integrated circuit dies 200 that provide functionality other than memory, such as, for example, graphics control, digital signal processing, and communication protocol functions.
Turning now to
Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.