Patent Application
20250096142
The present disclosure relates generally to semiconductor devices and integrated circuit fabrication and, more specifically, to structures including an electro-optic bridge chip and methods of forming such structures.
Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip includes a photonic integrated circuit comprised of photonic components, such as modulators, polarizers, and optical couplers, that are used to manipulate light received from a light source, such as an optical fiber or a laser.
Improved structures including an electro-optic bridge chip and methods of forming such structures are needed.
In an embodiment, a structure comprises a photonics chip and an electro-optic bridge chip on a package substrate. The electro-optic bridge chip includes a waveguide core and an electrical trace line. A portion of the waveguide core is coupled to an optical coupler of the photonics chip.
In an embodiment, a method comprises forming an electro-optic bridge chip including a waveguide core and an electrical trace line, attaching the electro-optic bridge chip to a package substrate, and attaching a photonics chip to the package substrate. A portion of the waveguide core is coupled to an optical coupler of the photonics chip.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals are used to indicate like features in the various views.
With reference to
Multiple instances of electrical trace lines 18, 20 may be formed in a set of dielectric layers 22 disposed on the support substrate 16. The dielectric layers 22 may be comprised of a dielectric material, such as silicon dioxide, and the dielectric layers 22 may have a top surface 23. The electrical trace lines 18, 20 may be formed in the dielectric layers 22 by patterning trenches and filling the trenches with a conductor, such as copper. Vias 24 may be formed in the dielectric layers 22 that are coupled to the opposite ends of the electrical trace line 18. Vias 26 may be formed in the dielectric layers 22 that are coupled to the opposite ends of the electrical trace line 18. The vias 24, 26 may be formed by patterning via openings in the dielectric layers 22 and filling the via openings with a conductor, such as copper. The electrical trace line 18 and vias 24 define an electrical interconnect, and electrical trace line 20 and vias 26 define another electrical interconnect. In alternative embodiments, additional electrical interconnects including dielectric layers and electrical trace lines may be added to the structure 10. The support substrate 16 provides mechanical support for the dielectric layers 22.
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The top surface 32 of the dielectric layer 30 and the top surface 23 of the dielectric layers 22, except an area covered by the dielectric layer 30, are exposed after the electro-optic bridge chip 38 is attached to the package substrate 40. In an embodiment, the top surface 23 may be coplanar with the top surface 41 of the package substrate 40, which may be achieved through selection of the thickness of the electro-optic bridge chip 38 and selection of the depth of the recess 42. The vias 24, 26 are accessible at the top surface 23 of the dielectric layers 22 for establishing electric connections with the electrical trace lines 18, 20, which define electrical pathways of the electrical interconnects that extend laterally in the electro-optic bridge chip 38. In an embodiment, the electrical interconnects incorporated into the electro-optic bridge chip 38 may be used for power and ground. The top surface 32 of the dielectric layer 30 is disposed above the top surface 41 of the package substrate 40 such that the waveguide core 36 is also disposed above the top surface 41 and accessible for establishing an optical pathway in the electro-optic bridge chip 38. In an embodiment, the optical interconnect incorporated into the electro-optic bridge chip 38 may be used for signal processing.
The package substrate 40 includes package interconnects 44 for establishing electrical communication with one or more chips that are subsequently attached to the package substrate 40. The package substrate 40 may include bond pads 45 that are located at the top surface 41 and bond pads 47 that are located at a bottom surface. The bond pads 47 may be populated by solder balls 49. Each package interconnect 44 may be terminated at opposite ends by the bond pads 45, 47 to establish electrical pathways extending through the thickness of the package substrate 40. In an embodiment, the package substrate 40 may be a printed circuit board laminate that comprises an organic matrix in which the package interconnects 44 are embedded. In an embodiment, the top surface 23 of the dielectric layers 22 may be coplanar with the top surface 41.
With reference to
Each of the photonics chips 46, 48 also includes an optical coupler 50 that provides an interface for light transfer to and from the respective photonic integrated circuit. In an embodiment, each optical coupler 50 may be a tapered section 52 (
The back-end-of-line stacks 51 have dielectric layers and interconnects in the dielectric layers that may be coupled with the photonic components, such as photodetectors and modulators, of the photonic integrated circuit are electrically active. Each of the back-end-of-line stacks 51 may include bond pads 58 that are physically and electrically coupled by electrical connections 54, such as solder bumps or pillars capped by a solder layer, to the electrical trace lines 18, 20 in order to establish electrical communication between the different photonics chips 46, 48. Each of the back-end-of-line stacks 51 may include bond pads 57 that are physically and electrically coupled by electrical connections 56, such as solder bumps or pillars capped by a solder layer, to the package interconnects 44 in order to establish external electrical connections to each of the photonics chips 46, 48. The electrical connections 54, 56 may be established by a solder reflow process.
In an embodiment, each back-end-of-line stack 51 may include an opening in which the optical coupler 50 is positioned. The opening in each back-end-of-line stack 51 may be filled by a homogeneous dielectric material, such as silicon dioxide, that replaces a removed portion of the back-end-of-line stack 51.
In use, optical signals may be transferred from the photonics chip 46 to the photonics chip 48 by coupling light from the optical coupler 50 of the photonics chip 46 to the waveguide core 36 and then, after the light propagates along the length of the waveguide core 36, coupling the light from the waveguide core 36 to the optical coupler 50 of the photonics chip 48. Conversely, optical signals may be transferred from the photonics chip 48 to the photonics chip 46 by coupling light from the optical coupler 50 of the photonics chip 48 to the waveguide core 36 and then, after the light propagates along the length of the waveguide core 36, coupling the light from the waveguide core 36 to the optical coupler 50 of the photonics chip 46. Electrical signals are communicated between the photonics chips 46, 48 through the electrical trace lines 18, 20 and vias 24, 26.
Multiple photonics chips 46, 48 are directly routed through the electro-optic bridge chip 38. The electro-optic bridge chip 38 establishes an interface for optical communication and an interface for electrical communication between the photonics chips 46, 48. The electro-optic bridge chip 38 includes the electrical trace lines 18, 20 and vias 24, 26 providing the chip-to-chip electrical interconnects enabling electrical communication. The photonics chips 46, 48 may be electrically coupled to each other by the chip-to-chip electrical interconnects. The electro-optic bridge chip 38 includes the chip-to-chip optical interconnect provided by the waveguide core 36 enabling optical communication. The photonics chips 46, 48 are optically coupled to each other by the chip-to-chip optical interconnect. The hybrid combination of chip-to-chip electrical and optical interconnects may enable a high bandwidth data rate that is unachievable with metal-based interconnects alone. The electro-optic bridge chip 38 may eliminate the need for costly interposers and through-silicon vias.
With reference to
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s).
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction in the frame of reference within the horizontal plane.
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features “overlap” if a feature extends over, and covers a part of, another feature.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
