This application claims priority to French Patent Application No. 1763208, filed Dec. 26, 2017, the entire content of which is incorporated herein by reference in its entirety.
The technical field of the invention is that of non-volatile resistive random-access memories.
The present invention relates to an elementary cell comprising a resistive random-access memory and a selector, a stage comprising a plurality of the cells and a matrix comprising a plurality of the stages. The present invention also relates to the manufacturing method for obtaining the stage and the matrix.
For applications that require storage of information even when the voltage is cut, EEPROM or FLASH type non-volatile memories, which store charges on floating gates of field effect transistors, are conventionally used. These memories nevertheless have drawbacks:
Thus, this type of memory does not have the characteristics required to support the development of new technologies such as SCMs (Storage Class Memories) which are experiencing a significant surge notably thanks to their capacity to enhance the performances of computers while reducing the consumption thereof.
More recently, other types of rewritable non-volatile memories have appeared, based on active materials such as ion conducting materials (CBRAMs or Conductive Bridging RAMs), metal oxides materials (OxRAMs or Oxide Resistive RAMs), ferroelectric materials (FERAMs or Ferroelectric RAMs), magnetic materials (MRAMs or Magnetic RAMs), magnetic materials with spin transfer (STTRAMs or Spin Torque Transfer RAMs) or materials with phase change (PCRAMs or Phase Change RAMs). These memories are resistive type memories (that is to say that they can have at least two states “OFF” or “ON” corresponding to the passage from a resistive state (“OFF” state) to a less resistive state (“ON” state)).
Resistive random-access memories need two electrodes to operate. For example, CBRAMs comprise an active zone based on an ion conducting material forming a solid electrolyte with ionic conduction arranged between an electrode forming an inert cathode and an electrode comprising a portion of ionisable metal, that is to say a portion of metal being able to form metal ions easily, and forming an anode. The operation of CBRAMs is based on the formation, within the solid electrolyte, of one or more metal filaments (also called “dendrites”) between its two electrodes when these electrodes are taken to suitable potentials. The formation of the filament enables to obtain a given electrical conduction between the two electrodes. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thereby to modify the electrical conduction between the two electrodes.
PCRAMs comprise an active zone based on a chalcogenide material. The operation of PCRAMs is based on the phase transition of the chalcogenide material, induced by the heating of this material under the effect of specific electrical pulses generated by its two electrodes. This transition takes place between an ordered crystalline phase, of low resistance and thermodynamically stable, and a disordered amorphous phase, of high resistance and thermodynamically unstable.
Resistive random-access memories notably have the interest of being able to be integrated with high densities, via a “cross-bar” (also designated “cross-point”) type integration.
Such an architecture 200 is illustrated in
This type of architecture nevertheless has certain drawbacks. Thus, the phase of reading the state of a cell is carried out by polarisation of the desired line and column; it is then possible to observe a parasitic leakage current flowing through adjacent cells. The hypothesis is here made that:
The reading of the resistive state of the cell C11 involves polarising respectively the bit line 201 and the word line 204 (application of a potential difference Vbias between these two lines). In theory, the measuring current should circulate uniquely along the arrow 205 represented in dotted lines. In practice, due to the fact that the three other cells are in the ON state, a parasitic leakage current, represented by the arrow 206, flows through the non-resistive cells C21, C22 and C12. This leakage current, in particular in the unfavourable case where the adjacent elements of the cell to measure are in the ON state, may perturb the measurement up to preventing the discrimination between the ON state and the OFF state of the cell to measure.
One known solution to this problem consists in adding, in series with each of the cells, a p/n junction diode 207 to play the role of selector. Such an architecture 300 is illustrated in
The architecture as illustrated in
That is why several alternative solutions have been studied over recent years. In the literature, different types of selector are found such as FAST (Field Assisted Superlinear Threshold), MIEC (Mixed-Ionic-Electronic Conduction) and OTS (Ovonic Threshold Switching).
A selector device is composed of two electrodes and an active material, the electrodes being arranged on either side of the active material and making it possible to apply a voltage to the active material. In the case of an OTS type selector, the active material may be a chalcogen alloy. The basic principle of the operation of a selector device is represented in
In order to be able to be integrated with a resistive random-access memory, a selector has to have several specificities. Indeed, it has to have:
To further improve the integration density of resistive random-access memories, a conventional solution is to decrease the size of the surface area between the active material of the resistive random-access memory and its lower electrode to enable a reduction in the programming current of the resistive random-access memory.
Thus, in general, both for the memory device and for the selector, the reduction in the surface area, notably the contact surface area between the selector and its upper electrode and the contact surface area between the active material of the memory and its lower electrode, makes it possible to respond to all the sought-after characteristics, namely:
The integration proposed in this invention is in particular dedicated to co-integration between a PCRAM and OTS selector, but it can extend to other types of resistive random-access memories such as OxRAM or CBRAM and other types of selectors such as FAST and MIEC.
One solution for reducing both the surface area of the OTS selector and the PCRAM is described in the patent US20150123066A1. This patent proposes etching the two devices at the same time by carrying out lithographic operations in the two directions of the plane. This solution has numerous drawbacks, of which the most important are:
There thus exists a need to reduce the dimensions of the OTS selector and to reduce the contact surface area between the PCRAM and its lower electrode within a device having a “cross-bar” type architecture, without the device encountering problems of stability at the end of its manufacture and without limiting the choice of its constituent materials.
An aspect of the invention offers a solution to the aforementioned problems by proposing an elementary memory cell suitable for being integrated in a device with a “cross-bar” type architecture having a selector and a contact surface area between the memory cell and its lower electrode of reduced dimensions with respect to conventional “cross-bar” structures while not limiting the choice of materials and not degrading the stability of the final device.
A first aspect of the invention relates to an elementary cell comprising a non-volatile resistive random-access memory mounted in series with a volatile selector device, the memory comprising:
Thanks to the invention, the dimensions of the selector device are defined by:
The dimensions of the contact surface between the memory and its lower electrode are defined by the dimensions of the first branch of the one-piece conductor element.
The dimensions of the two branches of the one-piece conductor element being independent of each other, issues regarding the reduction in the contact surface between the memory and its lower electrode are dissociated from issues regarding the reduction in the dimensions of the selector device, which makes it possible not to limit the choice of materials. In addition, this avoids having to etch the resistive random-access memory and the selector device at the same time, which would destabilise the final device.
Apart from the characteristics that have been described in the previous paragraph, the elementary cell according to an aspect of the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations thereof.
Beneficially, the selector device comprises a one-piece selector element comprising:
Thus, the first branch of the one-piece selector element enables better isolation of the one-piece conductor element.
Beneficially, the angle between the two branches of the one-piece conductor element is substantially a right angle.
Beneficially, the selector device is of OTS, FAST or MIEC type.
Beneficially, the resistive random-access memory is of PCRAM, OxRAM or CbRAM type.
Beneficially, a stage comprises a plurality of cells according to a first aspect of the invention distributed along several straight lines parallel with each other.
Beneficially, a matrix comprises a plurality of stages laid out one on top of the other and the direction of the straight lines along which are distributed the cells of a stage alternate from one stage to the next in such a way that the direction of the straight lines of a stage is perpendicular to the direction of the straight lines of the stage immediately below and/or above.
Thus, the stage and the matrix of stages make it possible to integrate resistive random-access memories with high densities. In addition, it enables a compact integration of the cells.
A second aspect of the invention relates to a method for manufacturing a stage comprising:
Thus, the method according to a second aspect of the invention makes it possible to obtain a stage of cells according to a first aspect of the invention.
Beneficially, a method for manufacturing a matrix reproduces the same steps as the method according to a second aspect of the invention for each stage of the matrix in such a way that the direction of the trenches of a stage is perpendicular to the direction of the trenches of the stage immediately below and/or above.
Thus, this method makes it possible to obtain a matrix of stages of cells according to a first aspect of the invention.
Beneficially, a method for manufacturing a matrix of stages of cells according to a first aspect of the invention comprises a step of etching several final trenches along the direction of the trenches etched at the etching step for producing the final stage, etching of final trenches in the memory active layer and the conductor material layer of the upper electrode of the resistive random-access memory of the final stage so as to only conserve the memory active layer and the conductor material layer of the upper electrode of the resistive random-access memory at the level of the contact surfaces between the memory active layer and the material layer of the one-piece conductor element.
A third aspect of the invention relates to a method for manufacturing at least one elementary cell comprising a non-volatile resistive random-access memory mounted in series with a volatile selector device, the memory comprising:
The invention and its different applications will be better understood on reading the description that follows and by examining the figures that accompany it.
The figures are presented for indicative purposes and in no way limit the invention.
Unless stated otherwise, a same element appearing in different figures has a single reference.
A first aspect of the invention illustrated in
The elementary cell 500 comprises:
The first active material is able to form a resistive random-access memory 510 and the second active material is able to form a selector device 511, the selector device 511 and the resistive random-access memory 510 each requiring an upper electrode and a lower electrode to ensure their operation.
An upper electrode of a device is defined as the electrode situated above the device and the lower electrode of a device is defined as the electrode situated below the device, the electrodes being situated on either side of the device. Obviously, the adjectives “upper” and “lower” are here relative to the orientation of the assembly including the upper electrode, the device and the lower electrode so that in turning over this assembly, the electrode previously qualified as upper becomes the lower electrode and the electrode previously qualified as lower becomes the upper electrode.
The one-piece conductor element 504 comprises two branches 504a and 504b having a substantially rectangular parallelepiped shape. The two branches 504a and 504b are laid out so as to have an “L” shape. In an embodiment, the angle θ1 between these two branches is comprised between 70 and 110° and for example between 90° and 110°. In another embodiment, the angle θ1 between these two branches is substantially a right angle, as represented in
The one-piece selector element 503 also has an “L” shape with two branches 503a and 503b. In an embodiment, the angle θ2 between these two branches is comprised between 70 and 110° and in another embodiment between 90° and 110°. In an embodiment, the angle θ2 between these two branches is substantially a right angle, as represented in
The one-piece conductor element 504 and the one-piece selector element 503 are laid out so as to form a single “L”, the one-piece selector element 503 fitting the outlines of the “L” which constitutes the one-piece conductor element 504. The assembly E formed of the one-piece conductor element 504 and the one-piece selector element 503 thus comprises two assembly branches being substantially perpendicular, a first assembly branch being along the direction {right arrow over (X1)} and having a dimension along the direction {right arrow over (X1)} equal to the dimension of the first branch 503a of the one-piece selector element 503 along the direction {right arrow over (X1)} and a second assembly branch being along the direction {right arrow over (Y1)} and having a dimension along the direction {right arrow over (Y1)} equal to the dimension of the second branch 503b of the one-piece selector element 503 along the direction {right arrow over (Y1)}.
The conductor material layer of the upper electrode of the resistive random-access memory 509 and the assembly E including the one-piece conductor element 504 and the one-piece selector element 503 are situated on either side of the memory active layer 508, the assembly E being in contact with the memory active layer 508 at the level of the end of the first assembly branch, along a plane containing the directions {right arrow over (Y1)} and {right arrow over (Z1)}.
The memory active layer 508 is thus in contact with a lower electrode at the level of the contact surface S1 between the memory active layer 508 and the end of the first branch 504a of the one-piece conductor element 504 and with an upper electrode at the level of the contact surface between the memory active layer 508 and the conductor material layer of the upper electrode of the resistive random-access memory 509, the assembly formed by the one-piece conductor element 504 of the memory active layer 508 and the conductor material layer of the upper electrode of the resistive random-access memory 509 forming a resistive random-access memory 510.
The assembly E is in contact with the conductor material layer of the lower electrode of the selector device 501 at the level of the face of the assembly E defined along a plane containing the direction {right arrow over (Y1)} and {right arrow over (Z1)}, the furthest from the memory active layer 508.
The one-piece selector element 503 is thus in contact with an upper electrode at the level of the contact surface S2 between the second branch 503b of the one-piece selector element 503 and the second branch 504b of the one-piece conductor element 504 and with a lower electrode at the level of the contact surface between the second branch 503b of the one-piece selector element 503 and the conductor material layer of the lower electrode of the selector device 501, the assembly formed by the one-piece conductor element 504, the one-piece selector element 503 and the conductor material layer of the lower electrode of the selector device 501 forming the selector device 511.
The one-piece selector element 503 may not have an “L” shape. Indeed, only the second branch or selector active layer 503b, in contact both with the one-piece conductor element 504 and the conductor material layer of the lower electrode of the selector device 501 participates in the operation of the selector device 511. The first branch 503a of the one-piece selector element 503 is not involved in the operation of the cell 500 but, the material of the first branch 503a being not very conductive, it enables better isolation of the one-piece conductor element 504.
The material of the memory active layer 508 is chosen as a function of the desired type of memory, for example, a PCRAM, OxRAM or CBRAM type memory: this choice then conditions the choice of the conductor materials of the electrodes of the memory. Indeed, for example, in order that a CBRAM operates, it has to have two electrodes arranged on either side of its active material with ionic conduction, of which one electrode comprising a portion of ionisable metal, that is to say a portion of metal being able to form metal ions easily.
The material of the one-piece conductor element 503 is chosen as a function of the desired type of selector device, for example, an OTS, FAST or MIEC type selector. For a PCRAM, the material of the memory active layer 508 is for example GeSbTe, SbTe or GeTe. For an OTS selector, the material of the one-piece conductor element 503 is for example GeSe, GeSiAsSe, GeSiAsTe, AsTe or GeSeSbN.
In the case of an OTS type selector and of a PCRAM type resistive random-access memory, the material used for the one-piece conductor element 504 is for example TiN, TaN, W, TiWN, TiSiN or WN.
Thus, the contact surface area between the memory active layer 508 and the lower electrode of the resistive random-access memory 510 depends on the dimension along the direction {right arrow over (Y1)}, on the end of the first branch 504a of the one-piece conductor element 504 and the dimensions of the selector device 511 depend on the dimension along the direction {right arrow over (Y1)}, on the face of the second branch 504b of the one-piece conductor element 504 extended along a plane containing the directions {right arrow over (Y1)} and {right arrow over (Z1)}, the furthest from the memory active layer 508, and on the dimension along the direction {right arrow over (X1)} of the second branch 503b of the one-piece conductor element 503. The “L” shape of the one-piece conductor element 504 thus makes it possible to dissociate problems linked to the reduction in the contact surface between the resistive random-access memory 510 and its lower electrode from those of the reduction in the dimensions of the selector device 511.
The method 400 makes it possible to manufacture a stage 600 referenced in
The deposition step 401 represented in and the direction
. The orthogonal reference frame (
,
;
) defines the sides of the stage 600 if it is of rectangular parallelepiped shape. The dimension of the layers along the direction
is called thickness. Thus, the first dielectric material layer 603 has a thickness “h”.
The dielectric material of the first dielectric material layer 603 is for example SiN, SiO2, SiC, SiON, SiCN or SiHN. The depositions of this step, like those of the following steps, may be CVDs (Chemical Vapour Depositions) or ALDs (Atomic Layer Depositions).
The etching step 402 represented in . The trenches 605 are all parallel with each other. A trench 605 is etched in such a way that the edges of the trench 605 are substantially of same height and that the sides of the trench 605 are comprised in planes orthogonal to the bottom of the trench 605 containing the direction
and substantially parallel with each other. The etching depth is substantially the same for all the trenches 605.
The deposition step 403 is represented in
The material used for the second dielectric material layer 608 is for example SiN, SiO2, SiC, SiON, SiCN or SiHN.
The step 404 of anisotropic etching represented in on the second dielectric material layer 608. At the bottom of the trenches 605, this etching enables a stoppage on the conductor material layer of the lower electrode of the selector device 602 and on the parts 604 of the first dielectric material layer that have not been etched during the etching step 402, a stoppage on the first dielectric layer 603. There is no etching on the sides of the trenches 605 which thus remain orthogonal to the bottom of the trenches 605. This anisotropic etching is, for example, a dry etching of RIE (Reactive Ion Etching) type.
The filling step 405 represented in
The lithography step 406 represented in , perpendicular to
, so as to etch the conductor material layer of the lower electrode of the selector device 602, that is to say with stoppage on the substrate 601. The etching depth is substantially the same for all the lithographic trenches 612 and the sides of the lithographic trenches 612 are substantially of same height. In addition, the sides are orthogonal to the bottom of the lithographic trenches 612, sides extended along the planes containing the direction
.
The filling step 407 represented in
The planarization step 408 represented in and
. The planarization is for example a planarizing polishing.
The deposition step 409 represented in
A stage 600 is thereby obtained comprising a plurality of elementary cells 500, distributed along lines that correspond to the sides of the trenches 605 etched at the etching step 402 but not continually distributed on these same lines on account of the lithographic trenches 612 of the lithography step 406 which intersect perpendicularly the trenches 605 etched at the etching step 402. Thus, a cell 500 elaborated on the side of a trench 605 has a counterpart on the opposite side of the same trench 605 and is separated from another cell 500 laid out on the same side of the trench 605 by the fourth dielectric material layer 614 having served to fill the lithographic trenches 612.
To produce a second stage 600, the first dielectric material layer 603 is deposited on the conductor material layer of the upper electrode of the resistive random-access memory 616 of the first stage 600, that is to say by considering the conductor material layer of the upper electrode of the resistive random-access memory 616 of the preceding stage 600 as the conductor material layer of the lower electrode of the selector device 602 and by considering the rest of the stage as substrate 601. The same operations as for the first stage 600 are next carried out except for the fact that the etching directions are alternating, that is to say that the trenches 605 of the etching step 402 are etched along the direction and the lithographic trenches 612 of the lithography step 406 along the direction
. In other words, if the stages 600 of the matrix 700 are numbered, all the stages numbered by a multiple of 2 have trenches 605 etched at the etching step 402 along the direction
and the lithographic trenches 612 along the direction
and all the other stages have trenches 605 etched at the etching step 402 along the direction
and the lithographic trenches 612 along the direction
.
A matrix 700 is a device having a plurality of stages 600.
When the desired number of stages has been produced, an etching step 410 represented in
Number | Date | Country | Kind |
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17 63208 | Dec 2017 | FR | national |
Number | Name | Date | Kind |
---|---|---|---|
8830739 | Oh | Sep 2014 | B2 |
10128315 | Russo | Nov 2018 | B2 |
20100163832 | Kau | Jul 2010 | A1 |
20100227438 | Ha | Sep 2010 | A1 |
20130270507 | Park et al. | Oct 2013 | A1 |
20140312296 | Jo et al. | Oct 2014 | A1 |
20150123066 | Gealy et al. | May 2015 | A1 |
20160005461 | Jo | Jan 2016 | A1 |
20170243922 | Eun | Aug 2017 | A1 |
20180151623 | Terai | May 2018 | A1 |
20180286919 | Terai | Oct 2018 | A1 |
20180294408 | Yasuda | Oct 2018 | A1 |
Number | Date | Country |
---|---|---|
1801896 | Jun 2007 | EP |
2016043657 | Mar 2016 | WO |
Entry |
---|
International Search Report and Written Opinion dated Sep. 4, 2018 in French Application 1763208. |
Number | Date | Country | |
---|---|---|---|
20190198570 A1 | Jun 2019 | US |