Patent Application
20100155931
The present disclosure is in the field of integrated circuits. More specifically, the present disclosure involves embedded and through silicon stack integrated circuit packaging.
Integrated circuits are the cornerstone of most modern day electronic devices. Integrated circuits are a microscopic array of electronic circuits and components made together or integrated-hence the name. Initially, integrated circuits held only a few devices, probably as many as ten diodes, transistors, resistors and capacitors that allow the integrated circuit to fabricate one or more logic gates. Today, very-large-scale integration (VLSI) has created integrated circuits with millions of gates and hundreds of millions of individual transistors. Integrated circuits are found in devices such as computers and cellular phones. Over the years, scientists have significantly reduced the size of integrated circuits. In turn, these smaller integrated circuits bring about smaller electronic devices. The decrease in size of integrated circuits over the years, has been so dramatic that to decrease their size even further is difficult.
Usually, integrated circuits are produced on a single wafer of electronic grade silicon and then cut into pieces. Each piece represents a copy of the circuit and is called a die. An integrated circuit package is a die mounted within a protective housing where pads of the die interconnect to external pins, (e.g., dual in-line packages) or pads (e.g., ball grid array packages) of the housing using bond wires or flip chip bumps. Typically, an integrated circuit package includes one die. Integrated circuit packages that contain more than one die conventionally have dies stacked adjacent to each other.
A recent method of producing dies involves stacking dies that have small openings through them wherein these small openings include conductive material therein to provide an electrical path through the dies. These openings with conductive material are known as through silicon vias (TSVs). Integrated circuits that have stacked dies interconnected with through silicon vias are known as through silicon stacks or “TSS.”
Separately, specialists in the package substrate field have recently developed technology that embeds dies in package substrates. This is known as embedded die in a package substrate or “EDS.” In the methods of production described above, the packages are either bulky and/or the degree of interconnection amongst the dies and other components is limited. For example, in the EDS method, interconnections to a die can only be made on one face of the die.
In the TSS method, the dies are placed on top of the package substrate. This limits the effectiveness of the TSS method when manufacturers must incorporate passive devices such as inductors, antennas, diodes, transistors, resistors and capacitors in the integrated circuit package because of size and cost.
Wire bond or solder electrically couples the layers of TSS devices. The wire bond or solder connections are problematic because they require the application of heat and/or pressure to metals forming the bond or solder. Thus, wire bond or solder installation is difficult because the application of heat or pressure, if not done properly, can damage layers of the TSS device.
Additionally, because the dies in the TSS method are on top of the package substrate these TSS integrated circuit packages are large. The larger the packages are, the longer the length of the electrical connections between devices. The longer the connections between devices, the higher the level of power required to pass electricity through these connections.
In sum, issues of package size and effectiveness of making electrical connections to devices in integrated circuit packages remain despite the significant developments in the various fields over the years.
The present disclosure solves the problems of large package size and ineffective or insufficient die connection sites by providing electrical paths through a die (by through silicon vias in the die) and, simultaneously, to the die (by a conductive layer in a package substrate). Further, the package substrate forms a protective cover over the die. One embodiment of the disclosure involves at least partially embedding at least one die having through silicon vias, in a package substrate. Another embodiment involves at least partially embedding a die stack with through silicon vias in a package substrate. Embedding a die or die stack in a package substrate, instead of placing the die or die stack on top of the package substrate as done in some integrated circuit packages, allows the efficient use of space in the package while utilizing the package substrate for providing electrical paths to couple the die to other devices. Moreover, the through silicon vias of the die or die stack that are embedded in the package substrate allow coupling to both faces of the die and thus avoid routing electrical paths around the die.
Embedding the die in the package substrate eliminates the need to interconnect the die on top of the package substrate by solder. This in turn lowers manufacturing costs. Further, embedding a die or die stack with through silicon vias in the package substrate eliminates cross-talk amongst devices in the integrated circuit package. The reduction of cross-talk is achieved by several factors. First the interconnect node physical size is reduced, lowering interconnect capacitance and thus reducing the size and power required to switch the nodes. Accordingly, signal integrity is improved. Second, the physically smaller loops lower both loop and mutual inductance.
In one embodiment, an integrated circuit includes a die having through silicon vias; and a package substrate in which the die is at least partially embedded. At least one of the through silicon vias is electrically coupled to electrical paths in the substrate.
In another embodiment, an integrated circuit package includes stacked dies, at least one of the stacked dies having at least one through silicon via. The integrated circuit also includes a package substrate in which the stacked dies are at least partially embedded.
In yet another embodiment, a method producing an integrated circuit is disclosed. The method includes at least partially embedding at least one die having at least one through silicon via in a package substrate.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawing.
Conventionally, dies have only one electrically active face. Consequently, electrical connections are usually made only to that active face. Because electrical connections are only made to the active face, the input and output (I/O) of the dies and integrated circuit package are in one direction only. In the current example, faces L11b and L11a are active while U11a and U11b are not. Therefore, wire bond 19 couples point p1 on face L11b by a route around 11b to point p2 on face L11a. Significantly, wire bond 19 is not the shortest possible distance coupling points p1 and p2.
Solder balls 13 attach die 11b to package substrate 12. Conductors 13A, which run through package substrate 12, electrically couple die 11b to external solder balls 18. External solder balls 18 serve to couple, electrically and physically, integrated circuit package 10 to any external device or circuitry such as a main board of an electronic device (not shown). Over mold 14 covers and protects dies 11a and 11b. Apart from dies, integrated circuit packages sometimes include passive devices such as antenna 15 and inductor 16. Wire bond 17a couples antenna 15 to a device (not shown) external to integrated circuit package 10. Wire bond 17b couples inductor 16 to die 11b. Other passive devices include, but are not limited to a diode, a transistor, a resistor and a capacitor.
As discussed above, the size of an integrated circuit package is important. It should be noted, therefore, that the total height C of integrated circuit package 10 is the sum of the package substrate height A and the height B of over mold 14.
The types of connections between devices in an integrated circuit package are important. Wire bond 19 requires high loads to pass electrical signals through them, in part, because the wire bonds are long and the longer the wire bonds the higher the load required to route electrical signals from one die's active face to another.
Because die 21a occupies so much space, it limits the ways in which devices may be coupled. For example, it is difficult for die 21b to have access to solder balls 18 because die 21a is a barrier between die 21b and solder balls 18.
The height D of package substrate 32 is substantially the same as height A of package substrate 12 (
Moreover, because devices such as antenna 34 and inductor 35 are in the over mold they have to be coupled to by wire bonds or bumps. The length of the interconnects and consequently the load to pass electricity through them is unsuitable for high speed and high performance applications.
Additionally, through silicon vias 49 gives die 41b short access not only to both faces of die 41a but also to solder balls 18 through path 47a. Without through silicon vias 49, the path from die 41b to solder balls 18 would have to be around die 41a which is necessarily a longer path, similar to paths 23 and 24 in
If desired, at least one more die may be placed on top of substrate 42 (as shown in
As depicted in
Package substrate 42 also facilitates package substrate connections, for example, paths 43 and 44 to faces L41a and U41b respectively. In addition, substrate interconnect technology may also provide connections for inductor 45 and antenna 46. Paths 47 and 48 eliminate the need to use wire bonds when coupling inductor 45 and antenna 46 to other devices. As described above, coupling to devices such as inductors and antennas is difficult. This difficulty is avoided in integrated circuit package 40 where embedded device substrate technology is used. In this case (not shown), the passive elements 45, 46 are placed on top of the package substrate 42
Furthermore, embedding dies 41a and 41b in package substrate 42 uses package substrate 42 as a protective cover for dies 41a and 41b and thereby eliminates the need for an over mold. Thus, integrated circuit package 40's height G is less than height C of today's integrated circuit package 10 (
Another advantage of the present disclosure is that a tier of a stacked IC device need not be thicker to enable coupling with a package substrate. Conventionally, the bottom tier of a stacked IC device is manufactured as a thicker tier to withstand the forces necessary to electrically bond the stacked IC device to the package substrate. The present disclosure, however, encapsulates the stacked IC device in the package substrate reducing (or possibly eliminating) forces needed to electrically bond the stacked IC device to the package substrate.
In sum, embedding dies, which have through silicon vias, into a package substrate, according to embodiments, simultaneously creates many benefits in an integrated circuit package. Embedding dies, according to embodiments, reduces integrated circuit package size and/or increases the density or capacity of the integrated circuit package to accommodate devices. Further, it increases the flexibility to couple to devices inside and outside of the integrated circuit and thus allows circuit configurations that were not previously possible. Additionally, embedding the dies in the package substrate avoids long electrical paths and thereby reduces power consumption. Moreover, embedding the dies improves the quality of connectors for passive devices such as inductors and antennas. It should be noted that in some embodiments of the disclosure a die may be partially embedded, i.e., not completely covered with the package substrate.
In one embodiment, substrate build up layer technology can bond die 51a with another stacked die (not shown) that is part of a TSS device (not shown). In this embodiment, the substrate lamination process avoids the need to separately bond dies of the stack as is conventionally done with stacked integrated circuit devices. For example, the force and heat from the substrate lamination could bond the dies of the stacked IC device. In one embodiment, indium can facilitate bonding of the dies.
Although
Passive devices, such as antenna 53 may be placed in particular layers as the package substrate is built up from 52a. In the current example, a passive device such as antenna 53, is placed above layer 52b. The antenna 53 and die 51-b are embedded with package substrate layer 52c. Substrate layer 52c also provides sealing and protection to dies 51a, 51b and antenna 53.
It should also be noted that the electrical paths are fabricated in the substrate layers by metallization within the layers. Further, substrate vias from one package substrate layer to another can be provided to electrically couple across layers or from one layer to another layer. For example, substrate through silicon vias TSV1 and TSV2 allow antenna 53 to couple to any external or internal device or circuit such as solder balls 54 which in turn may couple to an external device (not shown).
Embodiments of the current disclosure provide more flexibility in how dies are stacked in an integrated circuit. A comparison between
In contrast, in
Although the terminology “through silicon via” includes the word silicon, it is noted that through silicon vias are not necessarily constructed in silicon. Rather, the material can be any device substrate material.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
