Claims
- 1. A homoepitaxial gallium nitride based electronic device comprising:
at least one epitaxial semiconductor layer disposed on a single crystal substrate comprised of gallium nitride, the substrate having a dislocation density less than about 105 per cm2, wherein the at least one semiconductor layer is included in the electronic device which comprises one of a transistor, rectifier and thyristor.
- 2. The electronic device of claim 1, wherein the dislocation density is less than about 103 per cm2.
- 3. The electronic device of claim 1, wherein the substrate has an oxygen impurity concentration of less than 3×1018 cm−3.
- 4. The electronic device of claim 3, wherein the substrate has an oxygen impurity concentration of less than 3×1017 cm−3.
- 5. The electronic device of claim 1, wherein the electronic device is a high-electron mobility transistor (HEMT), and the oxygen impurity concentration of the substrate is less than 3×1018 cm3.
- 6. The electronic device of claim 5, wherein the at least one semiconductor layer comprises a buffer layer disposed over the substrate.
- 7. The electronic device of claim 6, wherein the buffer layer comprises undoped GaN.
- 8. The electronic device of claim 6, wherein the at least one semiconductor layer further comprises a barrier layer formed over the buffer layer.
- 9. The electronic device of claim 8, wherein the barrier layer comprises undoped AlInGaN.
- 10. The electronic device of claim 8, wherein the barrier layer includes a top sub barrier layer and a bottom sub layer, wherein the bottom sub layer has a higher bandgap than the top sub barrier layer.
- 11. The electronic device of claim 10, wherein the bottom sub barrier layer comprises AlN and the top sub barrier layer comprises AlGaN.
- 12. The electronic device of claim 5, wherein the at least one semiconductor layer comprises a contact layer disposed over the substrate.
- 13. The electronic device of claim 12, wherein the contact layer comprises n-doped GaN.
- 14. The electronic device of claim 5, further comprising source and drain contacts disposed over the substrate.
- 15. The electronic device of claim 14, further comprising a gate contact disposed between the source and drain contacts.
- 16. The electronic device of claim 14, further comprising an InGaN channel.
- 17. The electronic device of claim 15, further comprising a trench, wherein the gate contact is disposed within the trench.
- 18. The electronic device of claim 1, wherein the electronic device is a metal semiconductor field effect transistor (MESFET).
- 19. The electronic device of claim 18, wherein the at least one semiconductor layer comprises a channel layer disposed over the substrate.
- 20. The electronic device of claim 19, wherein the channel layer comprises GaN.
- 21. The electronic device of claim 1, wherein the electronic device is a metal oxide field effect transistor (MOSFET).
- 22. The electronic device of claim 21, wherein the at least one semiconductor layer comprises a channel layer disposed over the substrate, the electronic device further comprising:
a gate oxide over the channel layer.
- 23. The electronic device of claim 22, wherein the channel layer comprises GaN.
- 24. The electronic device of claim 1, wherein the electronic device is a metal insulator field effect transistor (MISFET).
- 25. The electronic device of claim 24, wherein the at least one semiconductor layer comprises a channel layer disposed over the substrate, the electronic device further comprising:
a gate insulating layer over the channel layer.
- 26. The electronic device of claim 25, wherein the channel layer comprises GaN.
- 27. The electronic device of claim 1, wherein the electronic device is a heterojunction bipolar transistor (HBT).
- 28. The electronic device of claim 27, wherein the at least one semiconductor layer comprises a subcollector layer disposed over the substrate.
- 29. The electronic device of claim 28, wherein the subcollector layer comprises one of n-doped and p-doped GaN.
- 30. The electronic device of claim 28, wherein the at least one semiconductor layer further comprises a collector layer disposed over the subcollector layer.
- 31. The electronic device of claim 30, wherein the subcollector layer comprises one of n-doped and p-doped GaN or AlGaN.
- 32. The electronic device of claim 28, wherein the at least one semiconductor layer further comprises a base layer disposed over the subcollector layer.
- 33. The electronic device of claim 32, wherein the base layer comprises one of n-doped and p-doped GaN.
- 34. The electronic device of claim 28, wherein the at least one semiconductor layer further comprises an emitter layer disposed over the subcollector layer.
- 35. The electronic device of claim 34, wherein the emitter layer comprises one of n-doped and p-doped AlGaN.
- 36. The electronic device of claim 34, wherein the at least one semiconductor layer further comprises a cap layer disposed over the emitter layer.
- 37. The electronic device of claim 36, wherein the cap layer comprises one of n-doped and p-doped GaN.
- 38. The electronic device of claim 1, wherein the electronic device is a bipolar junction transistor (BJT).
- 39. The electronic device of claim 38, wherein the at least one semiconductor layer comprises a subcollector layer disposed over the substrate.
- 40. The electronic device of claim 39, wherein the subcollector layer comprises one of n-doped and p-doped GaN.
- 41. The electronic device of claim 39, wherein the at least one semiconductor layer further comprises a collector layer disposed over the subcollector layer.
- 42. The electronic device of claim 41, wherein the subcollector layer comprises one of n-doped and p-doped GaN.
- 43. The electronic device of claim 39, wherein the at least one semiconductor layer further comprises a base layer disposed over the subcollector layer.
- 44. The electronic device of claim 43, wherein the base layer comprises one of p-doped and n-doped GaN.
- 45. The electronic device of claim 39, wherein the at least one semiconductor layer further comprises an emitter layer disposed over the subcollector layer.
- 46. The electronic device of claim 45, wherein the emitter layer comprises one of n-doped and p-doped GaN.
- 47. The electronic device of claim 1, wherein the electronic device is a Schottky rectifier.
- 48. The electronic device of claim 47, wherein the at least one semiconductor layer comprises a voltage blocking layer disposed over the substrate.
- 49. The electronic device of claim 48, wherein the voltage blocking layer comprises one of undoped GaN and undoped AlGaN.
- 50. The electronic device of claim 48, further comprising:
at least one guard ring disposed in the voltage blocking layer.
- 51. The electronic device of claim 50, wherein the at least one guard ring comprises ring regions of GaN or AlGaN implanted with Mg or Zn.
- 52. The electronic device of claim 50, further comprising:
at least one field ring disposed in the voltage blocking layer within the at least one guard ring.
- 53. The electronic device of claim 48, further comprising:
an oxide layer disposed on the voltage blocking layer.
- 54. The electronic device of claim 48, further comprising:
an voltage blocking layer contact disposed on the voltage blocking layer, wherein the voltage blocking layer contact is a Schottky contact.
- 55. The electronic device of claim 1, wherein the electronic device is a p-i-n rectifier.
- 56. The electronic device of claim 55, wherein the at least one semiconductor layer comprises a voltage blocking layer disposed over the substrate.
- 57. The electronic device of claim 56, wherein the voltage blocking layer comprises one of undoped GaN and undoped AlGaN.
- 58. The electronic device of claim 56, wherein the at least one semiconductor layer comprises:
a contact layer disposed on the voltage blocking layer.
- 59. The electronic device of claim 58, wherein the contact layer comprises p-doped GaN.
- 60. The electronic device of claim 58, further comprising:
an ohmic contact layer contact on the contact layer.
- 61. The electronic device of claim 1, wherein the electronic device is a thyristor.
- 62. The electronic device of claim 61, wherein the at least one semiconductor layer comprises a voltage blocking layer disposed over the substrate.
- 63. The electronic device of claim 62, wherein the voltage blocking layer comprises one of undoped GaN and undoped AlGaN.
- 64. The electronic device of claim 62, wherein the at least one semiconductor layer further comprises a first doped layer disposed between the substrate and the voltage blocking layer.
- 65. The electronic device of claim 62, wherein the at least one semiconductor layer further comprises a second doped layer disposed over the voltage blocking layer.
- 66. The electronic device of claim 62, wherein the at least one semiconductor layer further comprises a cap layer disposed over the voltage blocking layer layer.
- 67. The electronic device of claim 66, wherein the cap layer comprises one of n-doped and p-doped GaN.
- 68. The electronic device of claim 1, wherein the device is one of a power metal oxide semiconductor field effect transistor (power MOSFET) and a power metal insulator semiconductor field effect transistor (power MISFET).
- 69. The electronic device of claim 68, wherein the at least one semiconductor layer comprises a voltage blocking layer.
- 70. The electronic device of claim 69, wherein the voltage blocking layer comprises GaN.
- 71. The electronic device of claim 69, wherein the at least one semiconductor layer further comprises:
a p-type channel layer disposed over the voltage blocking layer; and a n-type source layer disposed over the p-type channel layer.
- 72. The electronic device of claim 71, wherein the n-type source layer and the p-type channel layer comprise GaN.
- 73. The electronic device of claim 71, further comprising a gate metal layer disposed over the p-type channel layer and the n-type source layer.
- 74. The electronic device of claim 71, further comprising a gate metal layer disposed lateral to the p-type channel layer and the n-type source layer.
- 75. The electronic device of claim 1, wherein the device is a power insulated gate bipolar transistor (power IGBT).
- 76. The electronic device of claim 75, wherein the at least one semiconductor layer comprises a voltage blocking layer.
- 77. The electronic device of claim 76, wherein the voltage blocking layer comprises GaN.
- 78. The electronic device of claim 76, wherein the at least one semiconductor layer further comprises:
a heavily doped p-type base layer disposed over and in the voltage blocking layer; a lightly doped p-type base layer disposed over the heavily doped p-type base layer; and a n-type emitter layer disposed over and in the lightly doped p-type base layer.
- 79. The electronic device of claim 78, further comprising:
a gate metal layer disposed over a portion of the n-type emitter layer and the lightly doped p-type base layer.
- 80. The electronic device of claim 1, wherein the device is a power vertical junction field effect transistor (power vertical JFET).
- 81. The electronic device of claim 80, wherein the at least one semiconductor layer comprises a voltage blocking layer.
- 82. The electronic device of claim 81, wherein the voltage blocking layer comprises GaN.
- 83. The electronic device of claim 81, wherein the at least one semiconductor layer further comprises:
a source layer disposed over the voltage blocking layer; and a gate layer disposed over the voltage blocking layer and lateral to the source layer.
- 84. The electronic device of claim 83, wherein the source layer and the gate layer comprise GaN.
- 85. The electronic device of claim 83, further comprising:
a source contact disposed on the source layer; and a gate contact disposed on the gate layer.
- 86. The electronic device of claim 1, wherein the device is a cascode switch.
- 87. The electronic device of claim 86, wherein the at least one semiconductor layer comprises a voltage blocking layer.
- 88. The electronic device of claim 87, wherein the voltage blocking layer comprises GaN.
- 89. The electronic device of claim 87, wherein the at least one semiconductor layer further comprises:
a buried gate layer disposed in the voltage blocking layer; and a field stop layer disposed over and in the voltage blocking layer and lateral to the buried gate layer.
- 90. The electronic device of claim 89, wherein the buried gate layer and the field stop layer comprise GaN.
- 91. The electronic device of claim 89, wherein the at least one semiconductor layer further comprises:
a well layer disposed over the buried gate layer; a source layer disposed in the well layer and lateral to the field stop layer; and a drain layer disposed in the well layer and lateral to the field stop layer.
- 92. The electronic device of claim 1, wherein the electronic device is a high-electron mobility transistor (HEMT) array, and the oxygen impurity concentration of the substrate is less than 3×1018 cm−3.
- 93. The electronic device of claim 92, wherein the HEMT array further comprises:
an active region comprising a plurality of HEMT components.
- 94. The electronic device of claim 93, wherein the HEMT array further comprises:
gate contacts connecting to the HEMT components; source contacts connecting to the HEMT components; and drain contacts connecting to the HEMT components.
- 95. The electronic device of claim 94, wherein the source contacts are connected to the HEMT components by air bridges.
- 96. A method of forming an electronic device comprising:
providing a single crystal substrate comprised of gallium nitride having a dislocation density less than about 105 per cm2; homoepitaxially forming at least one semiconductor layer on the substrate, wherein the electronic device is one of a transistor, rectifier and thyristor.
- 97. The electronic device of claim 96, wherein the substrate has an oxygen impurity concentration of less than 3×1018 cm−3.
- 98. The electronic device of claim 97, wherein the substrate has an oxygen impurity concentration of less than 3×1017 cm−3.
- 99. The method of claim 96 further comprising:
forming source, drain and gate contacts on the at least one semiconductor layer.
- 100. The method of claim 99, wherein the forming source, drain and gate contacts comprises at least one of electron beam evaporation and sputtering.
- 101. The method of claim 96, wherein the forming source, drain and gate contacts comprises:
depositing the source and drain contacts; and annealing the source and drain contacts after depositing the source and drain contacts.
- 102. The method of claim 96, wherein the homoepitaxially forming comprises at least one of molecular beam epitaxy (MBE) and metalorganic vapor-phase epitaxy (MOVPE).
- 103. The method of claim 102, wherein the homoepitaxially forming comprises MOVPE.
- 104. The method of claim 103, wherein the homoepitaxially forming comprises providing at least one organometallic precursor selected from trimethylgallium, Ga(CH3)3, trimethylaluminum, Al(CH3)3, and trimethylindum, In(CH3)3.
- 105. The electronic device of claim 2, wherein the dislocation density is less than about 102 per cm2.
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
[0001] This application is related to U.S. patent application entitled “IMPROVED GALLIUM NITRIDE CRYSTAL AND METHOD FOR MAKING”, Attorney Docket No. 040849-0216, filed concurrently herewith.