Claims
- 1. An insulating film with improved punching characteristics, comprising:
- a polyimide insulating base film having an edge tearing resistance in a range of 56 to 70 kgf/20 mm; and
- one of insulating thermoplastic and insulating thermosetting adhesive layers provided on at least one surface of said insulating base film.
- 2. A lead frame using an insulating film with improved punching characteristics, comprising:
- inner lead portions to be connected to a semiconductor chip;
- outer lead portions to be connected to external circuits; and
- polyimide insulating films punched to a predetermined configuration, said punched films being adhesively fixed to said inner lead portions;
- wherein said punched films have an edge tearing resistance in a range of 56 to 70 kgf/20 mm.
- 3. A lead frame using an insulating film with improved punching characteristics, according to claim 2, wherein:
- each of said polyimide insulating films comprises at least one surface layer which is one of insulating thermoplastic and insulating thermosetting adhesive layers.
- 4. A semiconductor chip package, comprising:
- a semiconductor chip;
- a lead frame comprising inner lead portions connected to said semiconductor chip, and outer lead portions to be connected to external circuits;
- polyimide insulating films punched to a predetermined configuration for adhesively fixing said semiconductor chip and said inner portions of said lead frame,
- wherein said punched films have an edge tearing resistance in a range of 56 to 70 kgf/20 mm.
- 5. A semiconductor chip package, according to claim 4, wherein;
- each of said polyimide insulating films comprises at least one surface layer which is one of insulating thermoplastic and insulating thermosetting adhesive layers.
- 6. A semiconductor chip package, according to claim 4, wherein said inner lead portions of said lead frame are connected to electrodes provided on a surface of said semiconductor chip by bonding wires; and
- said inner lead portions of said lead frame, said surface of said semiconductor chip, and said bonding wires are sealed by a resin layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
5-146989 |
May 1993 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 08/586,478, filed Jan. 16, 1996, now U.S. Pat. No. 5,593,774 which is a continuation of Ser. No. 08/249,734, filed May 26, 1994, now abandoned.
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4862245 |
Pashby te al. |
Aug 1989 |
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5102722 |
Iida et al. |
Apr 1992 |
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5277972 |
Sakumoto et al. |
Jan 1994 |
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Continuations (2)
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Number |
Date |
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Parent |
586478 |
Jan 1996 |
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Parent |
249734 |
May 1994 |
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