The present invention relates to an integrated circuit device which combines multiple chips in one package.
Integrated circuit devices include several functions such as CPU, logic circuit, memory and so on, each function in a separate chip or multiple functions in one chip. Technology of System in Package (SiP) which integrates multiple functions into one systematized package is advancing rapidly.
The SiP involves a Chip-on-Chip (COC) structure, which includes a plurality of semiconductor chips in such a way that a semiconductor chip stacked on top of another semiconductor chip. For example, in the Chip-on-Chip SiP, two semiconductor chips are connected by face-down bonding, with their circuit surfaces facing each other. In the explanation below, the circuit surface refers to the surface on which an integrated circuit is formed.
Referring first to
This integrated circuit device places the memory BIST circuit 201, which tests the memory chip 300, in the logic chip 200. Thus, after completing SiP, it is possible to test the memory chip 300 with the memory BIST circuit 201 via the logic COC I/O pad 212 and the memory I/O pad 222.
To meet the increasing demand for higher-speed and more sophisticated integrated circuits, higher integration and higher density integrated circuits are rapidly developed, resulting in an increase in the number of I/O pads and a decrease in the pitch between the pads. However, the present invention has recognized that conventional integrated circuit devices, such as shown in
Testing of the Chip-on-Chip SiP generally involves a unit test and a system test in order to increase yield. The unit test tests a semiconductor chip alone before forming SiP to remove defective chips. The system test tests the SiP after combining the semiconductor chips to form SiP. Further, the SiP system test involves a test which checks the operation of the whole SiP and a test which checks the operation of each of the semiconductor chips of the SiP in order to clarify the defective portion. In the unit test of the semiconductor chip and the system test of the SiP, probes of a tester are brought into contact with the I/O pads.
For example, when testing the memory chip 300 alone before forming the SiP, the probing to the memory I/O pads 222 is performed. If the pitch of the memory I/O pads 222 is smaller than the pitch of the probes of a normal tester, a normal tester fails the simultaneous probing to adjacent pads. Further, if the number of the memory I/O pads 222 is larger than the number of probes of a normal tester, a normal tester fails the simultaneous probing to all the pads. This causes untested pattern to exist, reducing the test coverage. Furthermore, since a normal tester allows the limited number of pads to be probed at the same time, some pads which are not probed are floating. This unstabilizes input and output logics or current consumption, which can inhibit accurate testing.
When testing the memory chip 300 after completing the SiP, the memory BIST circuit 201 of the logic chip 200 tests the memory chip 300 via the memory I/O pads 222. If a large number of the memory I/O pads 222 are placed with a very small pitch, wiring capacity can affect input and output signals. Due to the wiring capacity, it may be unable to conduct the test with a high-speed clock like the unit test of the memory chip 300 before forming SiP, which can further reduce the test coverage.
According to one aspect of the present invention, there is provided an integrated circuit device which includes a first semiconductor chip having a plurality of first input/output pads in an array and a plurality of test pads placed in line at a position outer than the plurality of first input/output pads and being larger than the first input/output pads; and a second semiconductor chip having a plurality of second input/output pads connected to the plurality of first input/output pads. The integrated circuit device enables probing and testing with a normal tester in testing of a semiconductor chip before packaging. This allows increase in test coverage and yield.
According to another aspect of the present invention, there is provided an integrated circuit device which includes a memory chip having a plurality of first input/output pads and a plurality of probe test pads larger than the plurality of first input/output pads; and a non-memory chip placed below the memory chip and having a plurality of second input/output pads connected to the plurality of first input/output pads by a bump. The integrated circuit device enables probing and testing with a normal tester in testing of a semiconductor chip before packaging. This allows increase in test coverage and yield.
The present invention provides an integrated circuit with high test coverage and high yield.
The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.
An integrated circuit device of a first embodiment of the invention is explained hereinafter with reference to
As shown in
The memory cell block 21, the data I/O circuit 22, and the address control circuit 23 are internal circuits located in substantially central part of the circuit surface of the memory chip 2. The memory cell block 21 is, for example, a memory cell array which includes a plurality of memory cells to store data. The address control circuit 23 is, for example, a decoder which decodes data write address or read address and selects a given memory cell of the memory cell block 21. The data I/O circuit 22 is, for example, a buffer circuit which amplifies and writes data into or amplifies the data read from the memory cell of the memory cell block 21 selected by the address control circuit 23.
The test pads 121 are placed in the peripheral part of the circuit surface of the memory chip 2 at the position outer than the memory I/O pads 122. The test pads 121 are used for probing in the testing of the memory chip 2 before forming SiP. The test pads 121 are arranged in such a position that tester's probes can directly touch them. Thus, the test pads 121 are preferably arranged with substantially the same pitch as a probe pitch of a normal tester. The number of pads is preferably substantially the same as the number of probes of a normal tester. This allows easy testing of the semiconductor chip using a normal tester and a probe card.
In this example, the test pads 121 are arranged in one line along each of two opposite sides of the circuit surface of the memory chip 2. The test pads 121 have a larger pitch than the memory I/O pads 122, and the number of pads is smaller than the number of the memory I/O pads 122. Further, the test pad 121 is larger than the memory I/O pads 122 to facilitate probing. The test pad 121 is large enough for probing. The test pad 121 has a rectangular shape elongated in the probing direction in case the probing position deviates from a predetermined position. Thus, the side of the test pad 121 is longer in the direction perpendicular to the array direction than in the array direction.
The memory I/O pads 122 are placed in the peripheral part of the circuit surface of the memory chip 2. The memory I/O pads 122 are not probed in the testing before forming SiP. The memory I/O pads 122 are used to electrically connect the memory chip 2 to the logic chip 1 in the SiP. The memory I/O pads 122 exchange signals with the logic chip 1 and receive a power supply voltage or a ground voltage from the logic chip 1.
In this example, the memory I/O pads 122 are arranged in a lattice (array) pattern at the position inner than the test pads 121. Since the memory I/O pads 122 are not probed in the test before forming SiP, a large number of pads are arranged with a small pitch regardless of the pitch or the number of tester's probes. The pitch between the memory I/O pads 122 is several tens of μm or smaller, for example. The number of the memory I/O pads 122 is preferably large in order to enable high-speed and high-volume data transmission between the memory chip 2 and the logic chip 1. The arrangement pattern of the memory I/O pads 122 is not limited to this example. The pads may be arranged in another pattern as long as a large number of pads can be placed.
The memory I/O pad 122 is large enough for connection with the logic COC I/O pad 112 by a bump. For example, the memory I/O pad 122 may have a rectangular shape of 20 μm and arranged at the pitch of 40 μm. The test pad 121 may have a rectangular shape of 20 μm in the array direction and 60 μm in the direction perpendicular to the array direction.
As shown in
The logic external I/O pads 113 are placed in the peripheral part of the circuit surface of the logic chip 1. The logic external I/O pads 113 are used for electrical connection with an external device (external terminal) of the integrated circuit device. For example, the logic external I/O pads 113 exchange signals with the external device or receive a power supply voltage or a ground voltage from the external device in normal operations. The logic external I/O pads 113 are probed by a tester in the unit test of the logic chip before forming SiP or in the system test of the SiP.
The logic COC I/O pads 112 are placed on the circuit surface of the logic chip 1 in such a position that they face the memory I/O pads 122 when the memory chip 2 is mounted on top so as to make an electrical connection with the memory chip 2. The logic COC I/O pads 112 have the same shape and pitch as the memory I/O pads 122.
The test pads 111 are placed on the circuit surface of the logic chip 1 in such a position that they face the test pads 121 when the memory chip 2 is mounted on top so as to make an electrical connection with the memory chip 2. The test pads 111 have the same shape and pitch as the test pads 121. The test pads 111 are connected to the test pads 121 to supply a given voltage and so on to the memory chip 2. If the memory chip 2 can operate stably without connecting the test pads 111 to the test pads 121, this connection is unnecessary and the test pads 111 may be eliminated. Some of the test pads 111 or some of the test pads 121 may input or output the signal similar to the logic COC I/O pads 112 or the memory I/O pads 122 after completing the SiP.
The memory I/O pads 122 and the logic COC I/O pads 112 may be pads for inputting a signal from an external device, pads for outputting a signal to an external device, pads used both for inputting and outputting a signal, pads for receiving a power supply voltage from an external device, or pads for receiving a ground voltage from an external device. The test pads 121 and the test pads 111 are used for testing a wafer or a single semiconductor chip. Some of the test pads 121 and the test pads 111 may serve just like the memory I/O pads 122 and the logic COC I/O pads 112 after the integrated circuit device is completed.
Since it is only required that the test pads 121 of the memory chip 2 be probed by a normal tester, they are not necessarily arranged in one line as shown in
Alternatively, the test pads 121 may be arranged in one line along each of the four sides of the circuit surface of the memory chip 2 as shown in
As shown in
To overcome the above disadvantages, this embodiment places a selector circuit 51 in the I/O part between the pad and the internal circuit as shown in
The selector circuit 51 selects a signal from the test pad 121 or a signal from the memory I/O pad 122 and outputs the selected signal to an internal circuit 52. The selector circuit 51 has an input terminal H01 connected to the memory I/O pad 122, an input terminal H02 connected to the test pad 121, an input terminal H03 connected to a test mode selection pad 123, and an output terminal N01 connected to the internal circuit 52 via a buffer circuit 53.
The test mode selection pad 123 receives a selection signal to control the selection operation of the selector circuit 51. The test mode selection pad 123 is one of the test pads 121 of
As described earlier, the memory I/O pads 122 are not probed and thus floating in the unit test of the semiconductor chip before forming SiP. In the SiP, the memory I/O pads 122 are connected to the logic chip 1 to exchange signals therewith. The test pads 121 are probed in the unit test of the single semiconductor chip before forming SiP as described earlier.
The selector circuit 51 selects between a signal from the test pad 121 and a signal from the memory I/O pad 122 according to a selection signal from the test mode selection pad 123, and outputs the selected signal to the buffer circuit 53. For example, the selector circuit 51 selects the signal from the test pad 121 if, in the unit test before forming SiP, a signal for selecting test mode is input to the test mode selection pad 123 from a tester through a probe. On the other hand, the selector circuit 51 selects the signal from the memory I/O pad 122 if, after completing the SiP, a selection signal is not input to the test mode selection pad 123. The buffer circuit 53, for example, amplifies the signal selected by the selector circuit 51 and outputs the amplified signal to the internal circuit 52. The selector circuit 51 prevents pad floating in the unit test of the semiconductor chip before forming SiP or pad floating after completing the SiP.
In the testing, the signal from the test pad 121 may be directly input to the selector circuit 51, or a test pattern generated in a test circuit such as a BIST circuit or a fixed logic signal may be input to the selector circuit 51. Though the example of
The selector circuit 51 may have a transfer gate as shown in
The selector circuit 51 of
The transfer gate 61 has transistors 61a and 61b, and the transfer gate 62 has transistors 62a and 62b. The transistors 61a, 61b, 62a, and 62b are turned on or off according to an inverted signal from an inverter 63 which inverts the selection signal from the input terminal H03, or a non-inverted signal from an inverter 64 which inverts the inverted signal. If the input terminal H03 is at low level, the transistors 61a and 61b are turned on to connect the input terminal H01 and the output terminal N01. If, on the other hand, the input terminal H03 is at high level, the transistors 62a and 62b are turned on to connect the input terminal H02 and the output terminal N01.
The selector circuit 51 of
The AND circuit 71 has transistors 71a to 71d, and the AND circuit 72 has transistors 72a to 72d. The transistors 71b, 71c, 72b, and 72c are turned on or off according to a selection signal from the input terminal H03 and an inverted signal from an inverter 73 which inverts the selection signal.
For example, if the input terminal H03 is at low level, the transistors 71b and 71c are turned on. The signal corresponding to the signal from the input terminal H01 being inverted by the inverter 74 is thereby output from the output terminal N01. If, on the other hand, the input terminal H03 is at high level, the transistors 72b and 72c are turned on. The signal corresponding to the signal from the input terminal H02 being inverted by the inverter 74 is thereby output from the output terminal N01.
The integrated circuit device 10 has a large number of the logic COC I/O pads 112 and the memory I/O pads 122 in a lattice pattern and connects those pads by the gold bump 5. This allows high-speed clock operation with the data transfer width of several hundreds of bits or greater and several hundreds of MHz or greater, and also allows data writing or reading with a low latency.
In the above example, the test pads 121 used for the unit test of the memory chip 2 before forming SiP are connected to the test pads 111 of the logic chip 1. However, the voltage of the test pads 111 may be set to a fixed logic (ground voltage or power supply voltage) by the wiring pattern in the logic chip 1. This prevents the pad floating in the SiP without placing the selector circuit like
As described in the foregoing, this embodiment has test pads to be probed in a unit test of a semiconductor chip before forming SiP in addition to pads for inputting or outputting signals after completing SiP. It is thereby possible to test a single chip in a semiconductor wafer easily using a normal tester and a probe card. This increases the test coverage of the semiconductor chip, decreases testing time and cost, and improves yield of the semiconductor chip and the integrated circuit device.
Further, this embodiment has a selector circuit for selecting between a signal from a test pad and a signal from an I/O pad, which is placed in an I/O part of the semiconductor chip. This prevents pad floating in testing before forming SiP and pad floating in the SiP, thereby stabilizing the logic of the pad and the current consumption in the chip. This allows accurate testing of a wafer or a single chip before forming SiP, thereby stabilizing the operation of the SiP. Several hundreds of memory I/O pads in the memory chip are grouped into units of several tens by the test pads to be probed, and it is possible to conduct the test equivalent to the case of inputting test signals from all the memory I/O pads, which further improves yield.
Furthermore, this embodiment connects the test pads to the pads of another semiconductor chip when forming SiP. This eliminates the need for a circuit and so on to control the logic of the test pads, thereby decreasing the number of lines and the scale of circuit which are used exclusively for the testing, thus allowing more flexible design.
An integrated circuit device according to a second embodiment of the invention is explained hereinafter with reference to
The memory BIST circuit 3 is an internal circuit placed in the memory chip 2 to test the memory chip 2. The memory BIST circuit 3, particularly, tests the data writing operation or reading operation of the memory chip 2. For example, the memory BIST circuit 3 generates a test pattern, tests the data writing operation or reading operation of the memory cell block 21 based on input clock and address, and outputs the test results.
The test control circuit 13 is an internal circuit of the logic chip 1. It serves both as a control circuit for controlling the testing on the memory chip 2 and a transfer circuit for transferring signals from a tester or the memory BIST circuit 3. When testing the memory chip 2 after completing SiP, the test control circuit 13 transfers the clock and address input by the tester to the memory BIST circuit 3, and transfers the test result of the memory BIST circuit 3 to the tester.
The operation when the memory BIST circuit 3 tests the memory chip 2 is explained below.
The tester 4 inputs a clock for testing and a data writing address and reading address to the memory BIST circuit 3 via the test pad 121.
The memory BIST circuit 3 generates a test pattern and writes or reads the test pattern to or from the memory cell block 21 according to the clock and address from the tester 4. Then, the memory BIST circuit 3 compares the read value with an expected value to determine if a defect exists. The test pattern is written to or read from the memory cell block 21 via the address control circuit 23 and the data I/O circuit 22. The memory BIST circuit 3 outputs the test result to the tester 4 via the test pad 121.
The tester 4 inputs a clock for testing and a data writing address and reading address to the test control circuit 13 via the logic external I/O pad 113. The test control circuit 13 transfers the clock and address from the tester 4 to the memory BIST circuit 3 via the logic COC I/O pad 112 and the memory I/O pad 122.
The memory BIST circuit 3 operates in the same manner as in the unit test shown in
In this embodiment, the signals exchanged between the memory BIST circuit 3 and the test control circuit 13 are only clocks and addresses. Thus, the parasitic capacitance causes no substantial effect in the logic COC I/O pad 112 and the memory I/O pad 122, thereby allowing high-speed and accurate testing just like the unit test of the memory chip 2.
The logic chip 1 includes a logic circuit 11 and a memory control circuit 12. The logic circuit 11 performs logical operations. The memory control circuit 12 controls data writing or reading to or from the memory chip 2. The logic circuit 11 and the memory control circuit 12 operate in normal operations of the integrated circuit device 10 or in testing of the integrated circuit device 10 as a whole.
For example, when testing the whole system of the integrated circuit device 10, the tester 4 inputs a clock and test pattern to the logic circuit 11 via the logic external I/O pad 113. The logic circuit 11 performs a certain logical operation on the input test pattern. The data necessary for the logical operation and the operation results are read from or written to the memory chip 2 by the memory control circuit 12. The memory control circuit 12 inputs or outputs the address or data instructed by the logic circuit 11 to or from the address control circuit 23 or the data I/O circuit 22 via the logic COC I/O pad 112 and the memory I/O pad 122, thereby writing or reading data to or from the memory cell block 21. Then, the logic circuit 11 outputs the operation result to the tester 4 via the logic external I/O pad 113.
As shown in
The multiply circuit 25 may operate also in the unit test of the memory chip 2 as shown in
As described above, this embodiment places a BIST circuit for memory testing in the memory chip 2, in addition to the configuration of the first embodiment. This embodiment thereby not only allows the unit test of the memory chip 2 before forming SiP just like the first embodiment, but also further improves the efficiency of the testing. For example, by testing the memory chip 2 alone with the memory BIST circuit 3 before forming SiP to sort defective chip and nondefective chip by the operation speed, it is possible to form the SiP using the memory chip 2 appropriate for the specification of the logic chip 1 requiring a different operation speed.
Further, use of the memory BIST circuit 3 reduces the effect of the parasitic capacitance between the logic chip 1 and the memory chip 2 in the testing of the memory chip 2 after completing the SiP, thereby allowing the testing of the memory chip 2 with a high-speed clock just like the testing before forming the SiP. This increases the test coverage and improves the yield of the integrated circuit device. Though this embodiment explains the case where the memory chip 2 has the test pads 121, the same advantage can be obtained after completing the SiP if the test pads 121 are eliminated.
Though the present invention is applied to the Chip-on-Chip SiP in the above example, it is not limited thereto, and the invention may be applied to other SiP. For example, the present invention may be applied to SiP in which a logic chip 600 and a memory chip 700 are mounted in one substrate 500 as shown in
It is apparent that the present invention is not limited to the above embodiment that may be modified and changed without departing from the scope and spirit of the invention.
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