Patent Application
20170287847
The disclosure herein relates generally to integrated circuit packages and more particularly to electromagnetic interference (EMI) shields for such structures.
Current EMI shielding for molded system in package (SiP) use a physical vapor deposition (PVD) sputtering process to coat the mold surface with a conductive material. The sputtering process has many disadvantages including high cost of the sputtering equipment, long through put time to increase conductive material thickness, complex process for uniform material coverage on package sidewalls, mold surface pre-clean to improve adhesion etc. In the case of EMI shielding between components, laser trenches are made between components and filled with a conductive material. The expensive laser ablation tool and long process for laser trenching can negatively impact cost and throughput time in high volume manufacturing.
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. Some embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which:
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
The present inventors have recognized apparatus and techniques for providing EMI shielding of integrated circuits assembled within integrated packages. In certain examples, an EMI shield can be integrated within over mold material surrounding an integrated circuit with an integrated circuit package. In some examples, an EMI shield can be integrated with a substrate and can be positioned about a cavity of the substrate that houses an integrated circuit. In some examples, an EMI shield can be built up about an integrated circuit housed in a cavity of a substrate. Each of the above examples, can use standard package fabrication methods including, but not limited to, formation of through mold interconnections, package via formation, cavity package construction, etc. Such methods can typically offer lower cost and short processing times to provide an EMI shield. In each case, the high cost of the sputtering equipment, long through put time to increase conductive material thickness and complex process for uniform material coverage on package sidewalls can be avoided. In addition, the package form factor and thickness are not increased by the above EMI shielding solutions.
In certain examples, the substrate 301 can include routing structures (not shown) to electrically connect terminations of the integrated circuit die 302 with external terminations 303 of the substrate 301 such as, but not limited to, solder balls located on an underside of the substrate. In certain examples, the substrate 301 can include a series of closely stacked vias 314 that surround the cavity 312. In certain examples, the substrate 301 can include multiple layers and the stacked vias can include alternating layers of conductive pads 316 and conductive vias, The vias and conductive pads 316 can be coupled directly together and integrated with each of the multiple layers of the substrate 301 to form the stacked vias 314. The stacked vias 314 can be coupled to an optional grounding plane or a ground terminal of the substrate 301. In certain examples, the stacked vias 314 can include a conductive material or paste 318 located at a top surface of the substrate. A conductive sheet 308 or foil can span the top of the cavity 312 and can be electrically coupled to the stacked vias 314 for example, via the conductive paste 318. The conductive sheet 308 and stacked vias 314 can form an EMI shield about the integrated circuit die 302. In certain examples, the substrate 301 can optionally include a lower conductive mesh 315 to provide EMI shielding underneath the integrated circuit die 302. Openings in the underlying conductive mesh 315 can be used to route electrical connections between the integrated circuit die 302 and external connections 303 on the underside of the substrate 301. FIG, 313 illustrates a top-down cross-section of the device 300 and shows that traces 305 can be used to electrically connect the stacked vias 314. In some examples, the traces 305 can be located on one or more of the substrate layers.
In Example 1, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on a first major surface (e.g., bottom) of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, and a conductive film coupled to the conductive fence, the film located above a second major surface (e.g., top) of the integrated circuit and coextensive with a footprint defined by the conductive fence, the second major surface of the integrated circuit opposite the first major surface of the integrated circuit.
In Example 2, the integrated circuit package of Example 1 optionally includes an over-mold configured to encapsulate the integrated circuit about the side surfaces and the second major surface and to house the conductive fence.
In Example 3, the conductive fence of any one or more of Examples 1-2 optionally includes a plurality of solder balls coupled to a plurality of ground pads on a first major surface of the substrate.
in Example 4, the integrated circuit of any one or more of Examples 1-3 optionally is positioned within a cavity of the substrate.
in Example 5, the substrate of any one or more of Examples 1-4 optionally includes the conductive fence surrounding the side surfaces of the integrated circuit and a second conductive fence underlying the integrated circuit.
In Example 6, the second conductive fence of any one or more of Examples 1-5 optionally is configured to allow electrically isolated vertical connections between the integrated circuit and external connections exposed on a second major surface of the substrate, the second major surface of the substrate opposite the first major surface of the substrate.
In Example 7, the conductive fence of any one or more of Examples 1-6 optionally includes a plurality of conductive traces and a plurality of conductive vias alternately stacked within the substrate.
In Example 8, the plurality of vias of any one or more of Examples 1-7 optionally includes a first via and a second via, wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces, wherein the first via and the second are positioned in different vertical layers of the substrate, and wherein the first via is laterally offset from the second via.
in Example 9, the plurality of vias of any one or more of Examples 1-3optionally includes a first via and a second via, wherein the first via and the second via are directly coupled by a conductive trace of the plurality of conductive traces, wherein the first via and the second are positioned in different vertical layers of the substrate, and wherein the first via is vertically aligned with the second via.
In Example 10, the conductive fence of any one or more of Examples 1-9 optionally includes conductive paste configured to fill at least a portion of the cavity about the integrated circuit not filled by the integrated circuit.
In Example 11, the integrated circuit package of any one or more of Examples 1-10 optionally includes underfill configured to isolate the connections on the first major surface of the integrated circuit from the conductive paste.
in Example 12, the substrate of any one or more of Examples 1-11 optionally includes a plurality of traces configured to electrically couple with the conductive paste.
In Example 13, a first conductive trace of the plurality of conductive traces of any one or more of Examples 1-12 optionally is configured to couple the conductive film to the conductive fence.
In Example 14, a first conductive trace of the plurality of conductive traces of any one or more of Examples 1-13 optionally is configured to couple the conductive fence to terminal on the second major surface of the substrate.
in Example 15, a method for providing EMI shielding for in integrated circuit package can include electrically coupling and mounting an integrated circuit to terminations on a top surface of a substrate, electrically coupling a plurality of solder balls to a plurality of pads of the substrate, the plurality of pads located about a perimeter of the integrated circuit, encapsulating the integrated circuit and the solder balls with a non-conductive compound, creating a plurality of vias in the non-conductive compound through a surface opposite the substrate, each via of the plurality of vi as extending to a solder ball of the plurality of solder balls, filling each via with a conductive material, covering the surface with a conductive sheet, and coupling the conductive sheet with the conductive material.
in Example 16, the creating a plurality of vias of any one or more of Examples 1-15 optionally includes laser ablating the non-conductive compound.
In Example 17, the method of any one or more of Examples 1-9 optionally includes electrically coupling the plurality of solder balls together to each other.
In Example 18, the method of any one or more of Examples 1-9 optionally includes electrically coupling the plurality of solder balls to a termination on a bottom side of the substrate.
in Example 19, a method for providing EMI shielding for in integrated circuit package can include creating a first conductive fence about a cavity of the substrate, electrically coupling and mounting an integrated circuit to terminations of the substrate within the cavity of the substrate, covering the cavity with a conductive sheet, and coupling the conductive sheet with the conductive fence.
In Example 20, the creating the conductive fence of any one or more of Examples 1-19 optionally includes fabricating an opening in a first layer of the substrate, the opening configured to form a portion of a sidewall of the cavity, fabricating a plurality of traces of the first layer, the plurality of traces positioned about the opening, and fabricating a plurality of conductive vias, each via coupled to a corresponding trace of the plurality of traces.
In Example 21, the creating the conductive fence of any one or more of Examples 1-20 optionally includes fabricating a second conductive fence within a second layer of the substrate, the second conductive fence configured to underlie the cavity.
In Example 22, the method of any one or more of Examples 1-9 optionally includes coupling the second conductive fence with the first conductive fence.
Each of these non-limiting examples can stand on its own, or can be combined with one or more of the other examples in any permutation or combination.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are legally entitled.
