LC RESONANT CLOCK RESOURCE MINIMIZATION USING COMPENSATION CAPACITANCE

Abstract

VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock inductor. The presence of a compensation capacitance reduces the overhead associated with the inductor and the decoupling capacitor. The compensation capacitor (s) can be selectively switched into the network to create scalable resonant frequencies.

Description

FIELD OF THE INVENTION

The presently disclosed subject matter is directed towards clock distribution networks that use distributed inductor-capacitor (LC) resonant tanks. More particularly, the present invention relates to the use of compensation capacitors to reduce the overhead of on-chip tank resources of Very Large Scale Integration (VLSI) clock distribution networks while enabling frequency scaling of resonant clocks.

BACKGROUND OF THE INVENTION

The on-going demand for high performance electronic systems has driven the need for high-speed Very Large Scale Integration (VLSI) chips. VLSI implementations are demand driven to proceed in two inter-related directions: higher performance and higher density (more devices per unit area). While modern VLSI chips have achieved astonishingly high levels of performance and chip density the demand for even higher levels keeps growing.

A serious impediment to achieving higher performance and higher density is power consumption. As a general rule higher performance requires more power, which produces more heat, which increases failure rates which can render VLSI devices unsuitable for some tasks. The result is that power consumption is often the predominant challenge in improving high performance VLSI devices.

Almost all modern VLSI devices are clocked. As long as all gates can keep up the higher the clock rate the faster the performance. As clock rates and VLSI devices densities increase it becomes difficult to ensure that all gates can be properly clocked. One reason for this is that each sequential gate element in a VLSI device needs its own clock signal, but not all sequential gate elements are the same distance from the clock source. This means that all clock lines are not the same length and thus associated parameters such as distributed capacitances and resistances differ between elements. Different lengths coupled with unavoidable signal delays caused by distributed resistances and capacitances can cause clock signals to arrive at different elements at different times. This is referred to as clock skew.

Compounding VLSI clocking problems is that clocking requires power. In fact, the on-chip clock distribution network (CDN) of modern VLSI devices often consume more than 35% of the total device power and can occasionally require as much as 70%. This is expected since dynamic power is determined by:

P=αCV ² f

where α is the switching activity, C is the clock distribution network (CDN) capacitance, V is the supply voltage and f is the operating frequency.

Many works have attempted to reduce power consumption by decreasing one or more of these factors, but the savings are often limited during peak activity and the requirement that clock quality must not be degraded.

One successful approach to reducing VLSI power consumption is the use of Distributed LC resonant clocks. Referring now to FIG. 1, a distributed LC resonant clock network 2 circumvents problems by oscillating input energy 4 between electrical potentials and magnetic fields using a parallel clock capacitance C_clk 6 and an inductance L 8. An additional decoupling capacitance C_d 10 offsets the voltage range to 0-V_dd by forming a series LC tank with the inductance L 8.

The approach shown in FIG. 1 has proven the power savings of distributed LC resonant clocks. Distributed LC resonant clocks have also been shown to have stable clock phases and magnitudes when compared to alternative approaches such as standing waves and rotary/salphasic resonant clocks. Academic algorithms have further optimized distributed LC resonant clocks to show the possibility of power savings of up to 90%. Unfortunately, such large power savings come at the expense of relatively large inductors and decoupling capacitors.

Inductors such as the inductor 8 of FIG. 1 can be readily fabricated on-chip. For example, VLSI spiral inductors can be manufactured on-chip using well-known CMOS processes. For example, high-Q spiral inductors can be fabricated using modern processes with thick (˜10 μm) oxides. But, on-chip VLSI inductors come with parasitic resistances and capacitances that decrease the inductor quality factor. But parasitic resistances can be included in the model of the inductor, and parasitic capacitances can be treated as part of the decoupling capacitance in a resonant clock. FIG. 2 shows a square spiral inductor L 14 having an inductance that can be approximated as:

$L=0.0002l〚\ln \frac{2l}{w+t}+0.5+\frac{w+t}{3l}〛\mathrm{nH}$

where n is the number of turns, w is the width of a trace, t is the thickness of the metal, l is the length of trace and s is the spacing between turns. Given n, s, w, d_i (inner diameter of the square spiral inductor), d_o (outer diameter of the square spiral inductor) the chip areas occupied by the inductor L 14 is:

Area=d₀²=(d_i+2n(s+w))²

On-chip capacitors are most effectively created as MOS (metal-oxide-semiconductor) capacitors that have both parallel-plate and fringe-field capacitances as illustrated by capacitor 20 shown in FIG. 3. The capacitance of capacitor 20 can be approximated as:

$C=C_{\mathrm{pp}}+C_{\mathrm{fringe}}=\frac{e_{\mathrm{di}}}{t_{\mathrm{di}}}\mathrm{WL}+\frac{2\pi e_{\mathrm{di}}}{\log \left(\frac{t_{\mathrm{di}}}{H}\right)}$

where W and L are the width and length of the metal representing the area of the capacitor, H is the height of the metal, and ∈_di and t_di are the permittivity and thickness of the dielectric layer. In the case of SiO₂, ∈_di=∈_r ∈₀=3.9×8.854×10⁻¹² F/m, where ∈_r is the relative permittivity of the insulating material, and ∈_o is the permittivity of free space.

As the W/H ratio reduces below unity the fringing capacitance of the capacitor 20 becomes dominate and significantly contributes to the overall capacitance. In a modern 90 nm CMOS technology, a MOS capacitor 20 can reach a capacitive density of 10˜20 fF/μm².

These on-chip VLSI inductors and capacitors can be used to form a series or parallel LC “tank” circuit which resonates at a particular frequency. The resonant frequency f_r of an ideal LC tank is the frequency when the network has zero total reactance. The resonant frequency of a tank (C and L) is ideally:

$\mathrm{fr}=\frac{1}{2\pi \sqrt{\mathrm{LC}}}$

When the impedance of the LC tank is near infinite due to the reactances cancelling the drive capability requirement of the clock buffer is minimized and clock energy can be saved.

Referring once again to FIG. 1, the resonant clock topology contains two LC tanks: one parallel and one series. The parallel LC tank ideally has infinite impedance at resonance while the series impedance ideally has zero impedance. These tanks would counteract each other if they resonate at the same frequency. Therefore, the decoupling capacitor C_d 10 is typically much larger than C_clk 6 to separate the resonant frequencies of the parallel LC_clk and extra series LC_d tanks according to

½π√{square root over (LC_d)}<<½π√{square root over (LC_clk)}

This ensures a wide margin such as f_clk/f_d˜3 by making C_d 10 for example 10 times C_clk 6 or more. The magnitude at the resonant frequency, w₀=2πf₀ is referred to as the characteristic impedance of the distributed LC resonant clock network 2.

In practice, the inductor L 8 area is the most significant obstacle to widespread acceptance of distributed LC resonant clock networks. Another problem is that the decoupling capacitance C_d 10 represents an extra burden on that acceptance. Reducing the inductor area and simplifying the decoupling capacitance would be highly beneficial and would make distributed LC resonant clock networks more practical.

Another issue with the wide spread acceptance of distributed LC resonant clock networks is achieving a configurable frequency of operation without significant efficiency degradation. Frequency scaling would be highly advantageous.

Therefore a distributed LC resonant clock network having reduced inductor dimensions would be beneficial. Even more beneficial would be a distributed LC resonant clock network having a simplified decoupling capacitance. Ideally such a distributed LC resonant clock network ideally would enable scalable frequency resonant clocks.

BRIEF SUMMARY OF THE INVENTION

The present invention discloses an LC resonant clock network having a compensation capacitor C_c in parallel with a capacitor C_clk and/or in parallel with an inductor. Those compensation capacitors can be permanently placed in parallel or switched into place.

The principles of the present invention provide for distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances. Furthermore, the principles of the present invention provide for scalable frequency distributed LC resonant clock networks.

A distributed LC resonant clock network in accord with the present invention minimizes inductor and capacitor overhead using and added coupling capacitor. That added coupling capacitor also enables scalable frequency.

A VLSI clock distribution network in accord with the present invention includes a VLSI substrate, a clock distribution capacitor C_clk fabricated on the VLSI substrate and having a lead that is connected to ground and an open lead. A decoupling capacitor C_d is also fabricated on the VLSI substrate as is a clock distribution inductor L. The inductor L connects to the open lead and to the decoupling capacitor. A buffer is also fabricated on the VLSI substrate with the buffer driving the capacitor C_clk and the inductor L at a clock frequency. A compensation capacitor C_c is in parallel with the capacitor C_clk. The clock distribution network is resonant at a clock frequency set by:

$f_{\mathrm{clk}}^{\prime }=\frac{1}{2\pi }\sqrt{\frac{C_{\mathrm{clk}}+C_c+C_d}{L\left(C_{\mathrm{clk}}+C_d\right)C_d}}.$

The capacitor C_clk, the capacitor C_d, and/or the capacitor C_c are fabricated as MOS capacitors. The inductor L is beneficially a spiral wound inductor having an inductance approximately equal to:

$L=0.0002l〚\ln \frac{2l}{w+t}+0.5+\frac{w+t}{3l}〛\mathrm{nH}.$

Another VLSI clock distribution network that is in accord with the present invention includes a VLSI substrate, a clock distribution capacitor C_clk fabricated on the VLSI substrate and having a lead that is connected to ground and an open lead. A decoupling capacitor C_d is also fabricated on the VLSI substrate as is a clock distribution inductor L. The inductor L connects to the open lead and to the decoupling capacitor. A buffer is also fabricated on the VLSI substrate with the buffer driving the capacitor C_clk and the inductor L. A compensation capacitor Cc is in parallel with the inductor L. The clock distribution network is resonant at the clock frequency which is determined as:

$f_{\mathrm{clk}}^{\prime }=\frac{1}{2\pi }\sqrt{\frac{C_{\mathrm{clk}}+C_d}{L\lceil C_{\mathrm{clk}}C_d+C_c(C_{\mathrm{clk}}+C_d\rceil }}.$

The capacitor C_clk, the capacitor C_d, and/or the capacitor C_c are fabricated as MOS capacitors. The inductor L is beneficially a spiral wound inductor having an inductance approximately equal to:

$L=0.0002l〚\ln \frac{2l}{w+t}+0.5+\frac{w+t}{3l}〛\mathrm{nH}.$

Another VLSI clock distribution network that is in accord with the present invention includes a VLSI substrate, a clock distribution capacitor C_clk fabricated on the VLSI substrate and having a lead connected to ground and an open lead. A decoupling capacitor C_d is fabricated on the along with a clock distribution inductor L. The inductor L is connected to the open lead and to the decoupling capacitor. A buffer is also fabricated on the VLSI substrate. The buffer drives the capacitor C_clk and the inductor L at a clock frequency. The VLSI clock distribution network further includes a first compensation capacitor C_c1 that is connected to ground and a first pass switch that is disposed between the first compensation capacitor C_c1 and the lead. The selectable resonant frequency changes when the first pass switch closes.

The frequency scalable VLSI clock distribution network may also include a second pass switch and a second compensation capacitor that are in series. The series combination of the second pass switch and the capacitor C_c2 are in parallel with the inductor L. The selectable resonant frequency changes when the second pass switch closes.

BRIEF DESCRIPTION OF THE DRAWINGS

The advantages and features of the present invention will become better understood with reference to the following detailed description and claims when taken in conjunction with the accompanying drawings, in which like elements are identified with like symbols, and in which:

FIG. 1 illustrates a prior art distributed LC resonant clock network 2;

FIG. 2 illustrates a spiral inductor 14 suitable for use in the present invention;

FIG. 3 illustrates a MOS capacitor 20 suitable for use in the present invention;

FIG. 4 is a schematic depiction of a distributed LC resonant clock network 50 that is in accord with the present invention;

FIG. 5 illustrates the Miller Effect in distributed LC resonant clock network 50;

FIG. 6 illustrates a distributed LC resonant clock network 100 that provides for selectable frequency scaling; and

FIG. 7 illustrates a VLSI device 200 including a VLSI chip that carries LC resonant clocks in accord with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The presently disclosed subject matter now will be described more fully hereinafter with reference to the accompanying drawings in which one embodiment is shown. However, it should be understood that this invention may take different forms and thus the invention should not be construed as limited to the specific embodiment set forth herein.

All publications mentioned herein, specifically including “DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS,” a patent application filed on Jun. 22, 2011 under Attorney Docket No.:SC2011-196_PROV having inventors Dr. Matthew Guthaus and Xuchu Hu, are incorporated by reference for all purposes to the extent allowable by law.

In addition, in the figures like numbers refer to like elements throughout. Additionally, the terms “a” and “an” as used herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items.

FIG. 7 illustrates a VLSI device 200 including a VLSI chip 204. The VLSI device 200 further includes a protective package 202 that spaces the VLSI chip 204 above internal contacts (shown as ball contacts) as well as external ball contacts 208. The VLSI chip 204 is suitable for carrying the LC resonant tanks that form the VLSI clocks.

FIG. 4 illustrates a distributed LC resonant clock network 50 that is in accord with the present invention and which illustrates two different topologies for insertion of a compensation capacitance C_c 54. One position is in parallel with C_clk 56 while the other in parallel with L 58. In addition, FIG. 4 includes a signal source 60 operating at f₀, an amplifier 62, and a decoupling capacitor C_d 66.

If C_c 54 is in parallel with C_clk 56 the size of the inductance L 58 can be reduced to obtain the same frequency f₀ according to the formula:

$f_0=\frac{1}{2\pi \sqrt{\mathrm{LC}}}$

However, if C_c 54 is in parallel with L 58 the often undesired Miller Effect can be used to good effect. Its application is shown in FIG. 5 which suggests that C_c 54 can be divided as C_c1 and C_c2 in parallel with, and thus adding to C_clk 56 and C_d 66, respectively. This reduces the size of both L 58 and C_d 66 to obtain the same operating frequency f₀. In this manner the impact of a relatively small capacitor can be magnified to great advantage in distributed LC resonant clock network while still retaining the required very high frequency operation.

If both the parallel and series tank circuits are considered in the distributed LC resonant clock network 2 of FIG. 1 the resonant clock frequency becomes:

$f_{\mathrm{clk}}=\frac{1}{2\pi }\sqrt{\frac{C_{\mathrm{clk}}+C_d}{{\mathrm{LC}}_{\mathrm{clk}}C_d}}$

If as usual C_d=10C_clk this reduces to:

$f_{\mathrm{clk}}=\sqrt{\frac{11}{10}}\times \frac{1}{2\pi \sqrt{{\mathrm{LC}}_{\mathrm{clk}}}}$

The result is a 4.9% increase in resonant frequency due to the parasitic series LC_d tank. That fact alone can be utilized to reduce the required inductor size of L 58 and save area at a fixed frequency f₀.

Referring again to FIG. 4, if C_c 54 is added in parallel with C_clk 56 the resonant frequency will add C_c 54 to C_clk 54 to give a resonant frequency of:

$f_{\mathrm{clk}}^{\prime }=\frac{1}{2\pi }\sqrt{\frac{C_{\mathrm{clk}}+C_c+C_d}{L\left(C_{\mathrm{clk}}+C_d\right)C_d}}$

The result is a decrease in resonant frequency given by:

$\frac{f_{\mathrm{clk}}^{\prime }}{f_{\mathrm{clk}}}=\sqrt{\frac{1+\frac{C_c}{C_{\mathrm{clk}}+C_d}}{1+\frac{C_c}{C_{\mathrm{clk}}}}}$

Now if C_c 54 is added in parallel with L 58 the resonant frequency is:

$f_{\mathrm{clk}}^{\prime }=\frac{1}{2\pi }\sqrt{\frac{C_{\mathrm{clk}}+C_d}{L\lceil C_{\mathrm{clk}}C_d+C_c\left(C_{\mathrm{clk}}+C_d\right)\rceil }}$

The result is a decrease in resonant frequency found by.

$\frac{f_{\mathrm{clk}}^{\prime }}{f_{\mathrm{clk}}}=\sqrt{\frac{1}{1+\frac{C_c}{C_{\mathrm{clk}}}+\frac{C_c}{C_d}}}$

This result is even better as far as reducing the size of the inductor than putting C_c in parallel with C_clk 56.

A specific example may be helpful. If C_c=0.5×C_clk and C_d=10×C_clk, then the resulting clock f′_clk given C_c 54 is in parallel with C_clk 56 in FIG. 4 is:

$f_{\mathrm{clk}}=\sqrt{\frac{11}{15}}÷2\pi \sqrt{{\mathrm{LC}}_{\mathrm{clk}}}$

Now, if Cc 54 is in parallel with L 58 then:

$f_{\mathrm{clk}}=\sqrt{\frac{11}{15.5}}÷2\pi \sqrt{{\mathrm{LC}}_{\mathrm{clk}}}$

This suggests that in the tank network of FIG. 4 that f′_clk when C_c 54 is in parallel with L 58 has a 3.8% lower frequency (in this example) than when in parallel with C_clk 56. Again, this can be used to reduce the size of the inductor L 58.

Still referring to FIG. 4 while taking into consideration of the Miller Effect in FIG. 5, a significant difference in the topologies is the addition of C_c2 to C_d 66 when the compensation capacitor C_c 54 is in parallel with L 58. In this case, the decoupling resonant frequency is:

$f_d=\frac{1}{2\pi \sqrt{L\left(\mathrm{Cd}+C_c\right)}}$

which is a factor

$\frac{1}{\sqrt{C_c}}$

lower than the case without C_c 54. Consequently, it offers the advantage of sharing C_c 54 directly from C_d 66 for the same f_d.

Based on the basic resonant frequency formula:

$f_0=\frac{1}{2\pi \sqrt{\mathrm{LC}}}$

L 58 can be reduced by adding C_c 54 and considering the Miller Approximation to get C_c1 and C_c2. If C_c1+C_clk=α_1xC_clk, where α₁ is the ratio or capacitive effect between C_c1+C_clk and C_clk, then L 58 can be reduced as L×α₁ for the same resonant frequency. The result is:

$L^{\prime }=\frac{L}{{\alpha }_1}=\frac{L}{{\left(\frac{f_{\mathrm{clk}}}{f_{\mathrm{clk}}^{\prime }}\right)}^2}$

α1 therefore represents the capacitive effect between C_c1, while L′ and f′_clk are the inductance and resonant frequency after adding the effect of C_c 54. A higher α1 means a better capacitive effect and a lower resonant frequency f′_clk.

Experimental results confirm the foregoing. Smaller inductors L 58 can be used to produce a fixed resonant frequency f₀ by incorporating a compensation capacitance C_c 54 in parallel with C_clk 56 with L 58, or with both. In addition, a fixed inductor L 58 and fixed C_clk 56 can be used to produce a scaled frequency by incorporating C_c 54 in parallel with C_clk 56, with L 58, or with both. Significant on-chip area can be saved by incorporating C_c 54. All of these results are highly beneficial and useful when incorporating distributed LC resonant clocks.

Incorporating compensation capacitors C_c 54 also enables dynamic frequency scaling. This enables a new, useful and unobvious enhancement to distributed LC resonant clocks.

Reference FIG. 6 for a distributed LC resonant clock network 100 suitable for selectable frequency scaling. The distributed LC resonant clock network 100 includes a signal source 102 that operates at f₀, an amplifier 104, a first compensation capacitor C_c 106, a second compensation capacitor C_c 108, a capacitor C_clk 110, an inductor L 112 and a decoupling capacitor C_d 114. In addition, the distributed LC resonant clock network 100 includes a first pass switch 120 and a second pass switch 122 for selectively connecting the first and second compensation capacitors C_c 106, 108, respectively into the network 100.

The distributed LC resonant clock network 100 enables multiple selectable (i.e. scalable) resonant frequencies selected by enabling or disabling the first pass switch 120 and the second pass switch 122. The selectable (scalable) resonant frequencies are selected in accord with the frequencies provide above. Both compensation capacitors C_c 106, 108 can be disabled, resulting in the resonant frequency provided above without the use of compensation capacitances. If only compensation capacitor Cc 106 is enabled by turning on pass switch 120 the result is the resonant frequency provided above with a compensation capacitor C_c 106 in parallel with C_clk 110. Compensation capacitor C_c 108 could be enabled by turning on pass switch 122, resulting in the resonant frequency provided above with compensation capacitor C_c 108 in parallel with L. Both compensation capacitors C_c 106, 108 could be enable by turning on pass switches 120, 122, resulting in the resonant frequency provided above with compensation capacitors C_c 106, 108 in parallel with both C_clk and L. Four different selectable resonant frequencies can be selected by selectively turning on pass transistors 120 and 122.

It is to be understood that while the figures and the above description illustrates the present invention, they are exemplary only. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. Others who are skilled in the applicable arts will recognize numerous modifications and adaptations of the illustrated embodiments that remain within the principles of the present invention. Therefore, the present invention is to be limited only by the appended claims.

Claims

1. A VLSI clock distribution network, comprising: a VLSI substrate;a clock distribution capacitor Cclk fabricated on said VLSI substrate, said capacitor Cclk having a lead connected to ground and an open lead;a decoupling capacitor Cd fabricated on said VLSI substrate;a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor;a buffer fabricated on said VLSI substrate, said buffer driving said capacitor Cclk and said inductor L at a clock frequency; anda compensation capacitor Cc in parallel with said capacitor Cclk;wherein said clock distribution network is resonant at said clock frequency, and wherein said clock frequency is determined as:

2. The VLSI clock distribution network according to claim 1, wherein said capacitor Cclk is fabricated as a MOS capacitor.

3. The VLSI clock distribution network according to claim 1, wherein said capacitor Cd is fabricated as a MOS capacitor.

4. The VLSI clock distribution network according to claim 1, wherein said capacitor Cc is fabricated as a MOS capacitor.

5. The VLSI clock distribution network according to claim 1, wherein said inductor L is a spiral wound inductor.

6. The VLSI clock distribution network according to claim 1, wherein said inductor L has an inductance approximately equal to:

7. A VLSI clock distribution network, comprising: a VLSI substrate;a clock distribution capacitor Cclk fabricated on said VLSI substrate, said capacitor Cclk having a lead connected to ground and an open lead;a decoupling capacitor Cd fabricated on said VLSI substrate;a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor;a buffer fabricated on said VLSI substrate, said buffer driving said capacitor Cclk and said inductor L at a clock frequency; anda compensation capacitor Cc in parallel with said inductor L;wherein said clock distribution network is resonant at said clock frequency, and wherein said clock frequency is determined as:

8. The VLSI clock distribution network according to claim 7, wherein said capacitor Cclk is fabricated as a MOS capacitor.

9. The VLSI clock distribution network according to claim 8, wherein said capacitor Cd is fabricated as a MOS capacitor.

10. The VLSI clock distribution network according to claim 8, wherein said capacitor Cc is fabricated as a MOS capacitor.

11. The VLSI clock distribution network according to claim 7, wherein said inductor L is a spiral wound inductor.

12. The VLSI clock distribution network according to claim 7, wherein said inductor L has an inductance approximately equal to:

13. A VLSI clock distribution network, comprising: a VLSI substrate;a clock distribution capacitor Cclk fabricated on said VLSI substrate, said capacitor Cclk having a lead connected to ground and an open lead;a decoupling capacitor Cd fabricated on said VLSI substrate;a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor;a buffer fabricated on said VLSI substrate, said buffer driving said capacitor Cclk and said inductor L at a clock frequency; anda compensation capacitor Cc in parallel with said capacitor Cclk;wherein said clock distribution network is resonant at said clock frequency, and wherein said clock frequency is determined as:

14. A frequency scalable VLSI clock distribution network having a selectable resonant frequency, comprising: a VLSI substrate having a ground;an amplifier fabricated on said VLSI substrate;a clock distribution capacitor Cclk fabricated on said VLSI substrate, said capacitor Cclk having a lead connected to ground and an open lead;a decoupling capacitor Cd fabricated on said VLSI substrate;a clock distribution inductor L fabricated on said VLSI substrate, said inductor L connected to said open lead and to said decoupling capacitor;a first compensation capacitor Cc1 connected to ground;a first pass switch disposed between said first compensation capacitor Cc1 and said lead;wherein said selectable resonant frequency changes when said first pass switch closes.

15. The frequency scalable VLSI clock distribution network according to claim 14, further including a second compensation capacitor Cc2; a second pass switch;wherein said second pass switch and said capacitor Cc2 are in series;wherein said series combination of said second pass switch and said capacitor Cc2 are in parallel with said inductor; andwherein said selectable resonant frequency changes when said second pass switch closes.

16. The VLSI clock distribution network according to claim 15, wherein said capacitor Cclk is fabricated as a MOS capacitor.

17. The VLSI clock distribution network according to claim 15, wherein said capacitor Cd is fabricated as a MOS capacitor.

18. The VLSI clock distribution network according to claim 15, wherein said capacitor Cc is fabricated as a MOS capacitor.

19. The VLSI clock distribution network according to claim 15, wherein said inductor L is a spiral wound inductor.

20. The VLSI clock distribution network according to claim 19, wherein said inductor L has an inductance approximately equal to: