Patent Application
20240421096
This application claims the priority benefit of Taiwan application serial no. 112122520, filed on Jun. 16, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to an electronic component, and in particular relates to a manufacturing method of an electronic package and an electronic package.
There are many types of electronic packaging technologies currently used for multi-chips, one of which is to form a redistribution structure on a bridge element, and then bond multiple chips to the redistribution structure in a flip-chip manner. Therefore, the bridge element overlapping with the adjacent chips can shorten the signal transmission path between the adjacent chips. In order to protect the chips and the bridge element, a conventional method is to adopt a molding compound to cover the bridge element and the chips. However, even if the chips are correctly positioned, the injection of the molding compound may still cause alignment shift of the chips, and the thermal curing process of the molding compound may accumulate stress on the contact surface between the chips and the material due to the large difference in thermal expansion coefficient.
The disclosure provides a manufacturing method of an electronic package, which is used to manufacture the electronic package.
The disclosure provides an electronic package, which is used to provide preferable packaging quality.
A manufacturing method of an electronic package according to an embodiment of the disclosure includes the following steps. Multiple chips are fixed to a temporary carrier via a temporary bonding layer. At least one bridge element is installed on active surfaces of the adjacent chips, so that the bridge element respectively partially overlaps with the adjacent chips. Multiple bridging pads of the bridge element are respectively directly bonded to multiple first chip pads of the active surfaces of the adjacent chips. A base dielectric layer is formed to cover the temporary bonding layer, the chips, and the bridge element, and the base dielectric layer fills a gap between adjacent two of the chips. A material of the base dielectric layer is a silicate composite material or a material available for chemical-mechanical polishing. The bridge element and the base dielectric layer are thinned and planarized. Multiple base conductive vias are formed. The base conductive vias respectively pass through the base dielectric layer and are respectively connected to multiple second chip pads of the active surfaces of the chips. A redistribution structure is formed on the base dielectric layer and the base conductive vias. Multiple conductive bumps are formed on the redistribution structure. The temporary bonding layer and the temporary carrier are removed to expose a back surface of each of the chips.
An electronic package according to an embodiment of the disclosure includes a sub-package. The sub-package includes multiple chips, at least one bridge element, a base dielectric layer, multiple base conductive vias, a redistribution structure, and multiple conductive bumps. The chips are arranged on a plane. The at least one bridge element respectively partially overlaps with the adjacent chips. Multiple bridging pads of the bridge element are respectively directly bonded to multiple first chip pads of active surfaces of the adjacent chips. The base dielectric layer covers the chips and the bridge element, and exposes back surfaces of the chips, and the base dielectric layer fills a gap between adjacent two of the chips. A material of the base dielectric layer includes a silicate composite material or a material suitable for chemical-mechanical polishing. The base conductive vias pass through the base dielectric layer and are respectively connected to multiple second chip pads of the active surfaces of the chips. The redistribution structure is disposed on the base dielectric layer and the base conductive vias. The conductive bumps are disposed on the redistribution structure.
Based on the above, the material of the base dielectric layer can reduce the interface stress between the material and each chip, so that the control of the material and processing is easier to obtain a finished product with high reliability. Moreover, the direct copper bond of the bridge element to the chips also helps to drastically improve transmission performance and power cost performance ratio. In other words, the bridging pads of the bridge element are respectively directly bonded to the first chip pads of the active surfaces of the adjacent chips, which helps to reduce circuit power, increase bridging density, and achieve high-performance computing applications.
A manufacturing method of an electronic package according to an embodiment of the disclosure will be described below with reference to
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In the embodiment, one of the chips 110 may be a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency (RF) chip, or an integrated circuit chip with a specific function. In other words, the chips 110 may include a combination of the chips of different functional types, so that the electronic package may be used in a chiplet packaging technology, which is similar to system in package (SiP). Since the chips 110 may have different functions, the sizes of the chips 110 may be different. In some embodiments, the chips may be a combination of a central processing unit chip and a logic chip, a combination of a central processing unit chip and an input/output chip, a combination of a graphics processing chip and a memory chip, or a combination of a radio frequency chip and a base band chip, and may also be a combination of two chips with the same function.
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In an embodiment, the material of the bridge element 120 may include an inorganic material such as silicon, glass, and ceramics or an organic material. The bridge element 120 may be an active element or a passive element. Furthermore, in the embodiment, the connection between the bridge element 120 and the chip 110 is a direct connection (pad to pad) between the bridging pad 121 and the first chip pad 111. Compared with the prior art in which each chip is connected to a bridge element through a redistribution structure (a redistribution layer, RDL), the embodiment can further shorten the transmission distance of electrical signals between the chips, and there is less issue of alignment shift. Furthermore, in an embodiment, the size of the first chip pad 111 is not greater than the size of a second chip pad 112. The pitch of two adjacent first chip pads 111 is not greater than the pitch of two adjacent second chip pads 112, and the pitch of two adjacent first chip pads 111 is, for example, less than 10 μm. In addition, the distribution density of the first chip pads 111 may be greater than the distribution density of the second chip pads 112.
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In addition, each of the chips 110 has multiple conductive pillars P, and the conductive pillars P are respectively located on multiple second chip pads 112 of the active surfaces 110a of the chips 110. Therefore, in the step of forming the base dielectric layer 131, the base dielectric layer 131 covers the conductive pillars P.
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In the embodiment, the redistribution structure 140 may be formed by a build-up process. The redistribution structure 140 may include multiple redistribution patterned conductive layers 142, multiple redistribution dielectric layers 144, and multiple redistribution conductive vias 146. The redistribution patterned conductive layers 142 are alternately stacked with the redistribution dielectric layers 144. The redistribution conductive vias 146 are respectively connected to the redistribution patterned conductive layers 142. In addition, multiple under bump metallurgy (UBM) layers 148 are further formed on multiple parts of the redistribution patterned conductive layer 142 farthest from the chips 110.
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Please refer to 1H. The conductive bumps 150 are connected to a circuit carrier 12, and multiple conductive balls 14 are connected to the circuit carrier 12. In the embodiment, after the conductive bumps 150 are connected to the circuit carrier 12, an underfill 16 may be filled between the sub-package 100 and the circuit carrier 12 to cover the conductive bumps 150. So far, an electronic package 10 is completed.
A manufacturing method of an electronic package according to another embodiment of the disclosure will be described below with reference to
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In the embodiment, one of the chips 110 may be a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency (RF) chip, or an integrated circuit chip with a specific function. In other words, the chips 110 may include a combination of the chips of different functional types, so that the electronic package may be used in a chiplet packaging technology, which is similar to system in package (SiP). Since the chips 110 may have different functions, the sizes of the chips 110 may be different. In some embodiments, the chips may be a combination of a central processing unit chip and a logic chip, a combination of a central processing unit chip and an input/output chip, a combination of a graphics processing chip and a memory chip, or a combination of a radio frequency chip and a base band chip, and may also be a combination of two chips with the same function.
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In an embodiment, the material of the bridge element 120 may include an inorganic material such as silicon, glass, and ceramics or an organic material. The bridge element 120 may be an active element or a passive element. Furthermore, in the embodiment, the connection between the bridge element 120 and the chip 110 is a direct connection (pad to pad) between the bridging pad 121 and the first chip pad 111. Compared with the prior art in which each chip is connected to the bridge element through a redistribution structure (a redistribution layer, RDL), the embodiment can further shorten the transmission distance of electrical signals between the chips, and there is less issue of alignment shift. Furthermore, in an embodiment, the size of the first chip pad 111 is not greater than the size of the second chip pad 112. The pitch of two adjacent first chip pads 111 is not greater than the pitch of two adjacent second chip pads 112, and the pitch of two adjacent first chip pads 111 is, for example, less than 10 μm. In addition, the distribution density of the first chip pads 111 may be greater than the distribution density of the second chip pads 112.
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In the embodiment, the redistribution structure 140 may be formed by a build-up process. The redistribution structure 140 may include the redistribution patterned conductive layers 142, the redistribution dielectric layers 144, and the redistribution conductive vias 146. The redistribution patterned conductive layers 142 are alternately stacked with the redistribution dielectric layers 144. The redistribution conductive vias 146 are respectively connected to the redistribution patterned conductive layers 142. In addition, the under bump metallurgy layers 148 are further formed on the parts of the redistribution patterned conductive layer 142 farthest from the chips 110. During the process of forming the redistribution structure 140, the conductive material may also be filled in the via holes 131a of the base dielectric layer 131 to form the base conductive vias 132.
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The electronic package 10 according to an embodiment of the disclosure will be described below with reference to
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The base dielectric layer 131 covers the chips 110 and the bridge element 120, and exposes the back surfaces 110b of the chips 110, and the base dielectric layer 131 fills the gap G between two adjacent chips 110. The material of the base dielectric layer 131 includes a silicate composite material or a material suitable for chemical-mechanical polishing. The silicate composite material is preferably a silicate nanocomposite material. The material suitable for chemical-mechanical polishing is preferably a composite material or an inorganic compound. It is worth mentioning that known molding compounds are usually polymer materials with filler particles, and are not suitable to be used as the material for chemical-mechanical polishing due to particle issues, so the polymer material (the molding compound) cannot be used as the material of the base dielectric layer 131.
The base conductive vias 132 pass through the base dielectric layer 131 and are respectively connected to the second chip pads 112 of the active surfaces 110a of the chips 110. The redistribution structure 140 is disposed on the base dielectric layer 131 and the base conductive vias 132. The conductive bumps 150 are disposed on the redistribution structure 140.
In the embodiment, the base dielectric layer 131 may fill the gap G between two adjacent chips 110. The base dielectric layer 131 has a material with a relatively low coefficient of thermal expansion. The coefficient of thermal expansion is, for example, less than 10 ppm/° C., and more preferably may be controlled to be less than 5 ppm/° C. Therefore, the coefficient of thermal expansion of the base dielectric layer 121 is similar to the coefficient of thermal expansion of silicon. In other words, the coefficient of thermal expansion of the base dielectric layer 131 is similar to the coefficient of thermal expansion of the chip 110, so that warpage of the chip caused by a large difference between the thermal expansion coefficients of the chip 110 and the base dielectric layer 131 in the past can be prevented.
In the embodiment, the distribution density of the first chip pads 111 may be greater than the distribution density of the second chip pads 112.
In the embodiment, one of the chips 110 may be a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency (RF) chip, or an integrated circuit chip with a specific function. In other words, the chips 110 may include a combination of the chips of different functional types, so that the electronic package 10 may be used in a chiplet packaging technology, which is similar to system in package (SiP). Since the chips 110 may have different functions, the sizes of the chips 110 may be different. In some embodiments, the chips may be a combination of a central processing unit chip and a logic chip, a combination of a central processing unit chip and an input/output chip, a combination of a graphics processing chip and a memory chip, or a combination of a radio frequency chip and a base band chip. In some embodiments, the chips may also be a combination of two chips with the same function.
In the embodiment, the bridge element 120 may be an active element or a passive element. The material of the bridge element 120 may include an inorganic material (for example, silicon, glass, and ceramics) or an organic material. The bridge element 120 may have multiple bridge conductive vias 122, and the chips 110 are electrically connected to the redistribution structure 140 via the bridge conductive vias 122. In addition, the thickness of the bridge element 120 is less than the thickness of the chips 110.
In the embodiment, the electronic package 10 may include the circuit carrier 12. The sub-package 100 is installed on the circuit carrier 12. In addition, the electronic package 10 may further include the conductive balls 14. The conductive balls 14 are connected to the circuit carrier 12. In addition, the electronic package 10 may further include the underfill 16. The underfill 16 is filled between the redistribution structure 140 and the circuit carrier 12, and covers the conductive bumps 150.
In summary, in the above embodiments, the material of the base dielectric layer can reduce the interface stress between the material and each chip, especially at the junction of the horizontal and vertical planes of the chip, so that the control of the material and processing is easier to obtain a finished product with high reliability. Moreover, the direct copper bond of the bridge element to the chips also helps to drastically improve transmission performance and power cost performance ratio. In other words, the bridging pads of the bridge element are respectively directly bonded to the first chip pads of the active surfaces of the adjacent chips, which helps to reduce circuit power, increase bridging density, and achieve high-performance computing applications. Under the selected material of the base dielectric layer, when the base dielectric layer is formed by spray coating, spin coating, or deposition, the gap between adjacent chips may be easily filled at low temperature, and the formation of the base dielectric layer is less likely to cause deflection of the chips to maintain alignment precision.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112122520 | Jun 2023 | TW | national |
