Patent Application
20210125906
This description relates to wafer-level packaging of integrated circuit devices.
Fan-out wafer-level (FOWL) packaging (also known as wafer-level fan-out packaging, fan-out) is an integrated circuit (IC) packaging technology, and an enhancement of standard wafer-level packaging (WLP) solutions. In standard WLP packaging solutions, the ICs are packaged while still part of the wafer, and the wafer (with outer layers of packaging already attached) is diced afterwards; the resulting package is practically of the same size as the die (or chip) itself. However, the advantage of having a small package comes with a downside of limiting the number of external contacts that can be accommodated in the limited package footprint. This downside is a significant limitation with complex ICs requiring a large number of contacts. In contrast with standard WLP solutions, in fan-out WLP the wafer is diced first. The die (i.e., chips) are very precisely re-positioned on a carrier wafer or panel with space for fan-out maintained around each chip. The carrier wafer is then reconstituted by molding, followed by making a redistribution layer atop the carrier (extending over the chip and the adjacent fan-out area), and then forming solder balls on contacts pads on top.
In a general aspect, a method includes disposing a patterned conductor layer directly on a mold material in a fan-out space adjacent to an integrated circuit (IC) chip in a reconstituted wafer made of the mold material and the IC chip, The patterned conductor layer overlies the mold material of the reconstituted wafer in the fan-out space. The method further includes configuring the patterned conductor layer disposed directly on the mold material of the reconstituted wafer as a redistribution layer (RDL), the RDL layer being configured to carry a signal associated with at least one input-output (I/O) contact on the IC chip in a fan-out package of the IC chip.
In a general aspect, a package includes a reconstituted wafer made of a mold material and an IC chip. A patterned conductor layer overlies the mold material of the reconstituted wafer in a fan-out space lateral to the IC chip in the reconstituted wafer. The patterned conductor layer is configured as a redistribution layer (RDL) in the package of the IC chip to carry a signal associated with at least one input-output (I/O) contact on the IC chip.
In a general aspect, a package includes an integrated circuit (IC chip) disposed in a wafer made of mold material and a patterned conductor layer disposed directly on the mold material of the reconstituted wafer within a fan-out space adjacent to the IC chip in the wafer, the patterned conductor layer being a redistribution layer (RDL) disposed between the mold material of the reconstituted wafer and a stack of one or more additional RDLs interleaved with passivating layers. The patterned conductor layer is configured to carry a signal associated with at least one input-output (I/O) contact on the IC chip.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.
Modern integrated circuits (IC) (chips) that are fabricated with increasingly narrow input-output (I/O) pitch can have an increasing number of functions and a correspondingly increasing number of contacts that must be accommodated in fan-out wafer-level packages. Multiple redistribution layers (RDLs) (i.e., metallization levels) are needed for numerous conductor lines (e.g., metal connections) to carry signals for these functions to, and from, the I/O contacts on the chip. Processes for fabricating a fan-out wafer-level package with multiple RDLs become more and more complex as the number of RDLs increases. Each additional RDL layer requires a corresponding additional re-passivation layer (i.e., an insulating layer) for electrical isolation from other RDLs and the chip. Further, every additional RDL placed directly on top of the chip can aggravate quality issues in fabricating the multi-layer fan-out wafer-level package. The quality issues, may, for example, arise from film stress in the RDLs and the re-passivation layers caused by uneven surface topography of the chip.
The present disclosure describes a multi-layer fan-out wafer-level package in which a first RDL (e.g., a metal layer) is placed directly on mold material in a fan-out area adjacent to the chip on a carrier. While the first RDL extends over the mold material in the fan-out area, it does not extend over, or above, the chip itself. Placing the first RDL on (e.g., only on) the mold material (in other words, limiting or confining the RDL to the fan-out space) avoids the need for a re-passivation layer that would be required to separate or insulate the first RDL from the chip (e.g., as would be required if the first RDL was instead placed on, or over, the chip).
Further, the mold material in the fan-out space of the carrier is usually planarized. Placing the first RDL over the planar surface of the mold material in the fan-out space avoids, or at least reduces, stresses in the fan-out wafer-level package that can be caused by, for example, uneven surface topography of the chip (e.g., if the first RDL was instead placed on, or over, the chip).
Package 100 may be fabricated from a planarized reconstituted wafer (e.g., reconstituted wafer 190,
In the example shown in
In metallization structure 160, a first re-passivation layer (e.g., layer 140-1) separates the first RDL (i.e. RDL 130-1) from the second RDL (e.g., RDL 130-2), while a second re-passivation layer (e.g., layer 140-2) separates the second RDL (i.e. RDL 130-2) from the third RDL (e.g., RDL 130-3). The first re-passivation layer (e.g., layer 140-1) separates the first RDL (i.e. RDL 130-1) from the second RDL overlies (is directly coupled to and in contact with) RDL 130-1 within fan-out space 111 and overlies chip 120.
As shown in
In example implementations, the first RDL (i.e. RDL 130-1) may be a conductive film (e.g., a thin metallic film) that is deposited (e.g., by sputtering, evaporation, or electro-plating) on top surface 112 of mold material 110. Sputtered films and evaporated films, which can be thinner than plated films, may be used for applications that do not have high current requirements.
In example metallization structure 160, the first RDL (i.e., RDL 130-1) that is deposited on top surface 112 of mold material 110 can be used to connect all chip I/O contacts (e.g., contacts 123-125, etc.) that have a same function. For example, contact 123 and contact 125 may have a same function (e.g., a ground function). In this example, RDL 130-1 may be used to connect to contact 123 and contact 125.
Method 200 includes re-positioning individually diced IC chips (i.e., semiconductor die) on a wafer carrier with space for fan-out maintained around each chip, and reconstituting a wafer including the individually diced IC chips on the wafer carrier by molding (210). The molding material makes a fan-out area adjacent to each semiconductor die (chip) in the reconstituted wafer. I/O contacts of each chip may be exposed on a top surface of the chip, which is also a top surface of the reconstituted wafer. The top surface of the reconstituted wafer may be co-planar with a top surface of the molding material in the fan-out area.
Method 200 further includes depositing a conductor layer (e.g., a metal layer) on the top surface of the reconstituted wafer (220). The conductor layer (e.g., a metal) may be deposited (e.g., blanket deposited) over the top surface of the reconstituted wafer using, for example, sputtering, or evaporation techniques. An initially deposited conductor layer may be used as a seed layer for electroplating additional conductive material. The conductor layer may be a precursor of a first redistribution layer of the multi-layer fan-out wafer-level package (e.g., package 100).
For forming the first redistribution layer of the package, method 200 may next involve lithographic patterning of a photoresist mask on top of the conductor layer that has been deposited (e.g., blanket deposited) on the top surface of the reconstituted wafer (230); and removing portions of the blanket deposited conductor layer through openings in the photoresist mask to form a patterned conductor layer and limit the patterned conductor layer in spatial extent to the fan-out space adjacent to the IC chip (240). In other words, the patterned conductor layer spatially extends only over molding material adjacent to a semiconductor die (chip) in the reconstituted wafer but does not touch or overlie the IC chip. The patterned conductor layer is not buried in the molding material but overlies the molding material adjacent to the semiconductor die (chip) in the reconstituted wafer and is limited in spatial extent to be within the fan-out space.
Method 200 also includes configuring the patterned conductor layer as a first redistribution layer (RDL) in the fan-out package of the IC chip to carry signals to, and from, at least one input-output (I/O) contact on the chip (250).
Method 200 further includes disposing alternating passivating layers and additional redistribution layers (e.g., a second redistributing layer and a third redistribution layer) (260). Method 200 also includes forming external contacts of the package to complete the wafer-level packaging (270). The external contacts may be solder balls. Forming the external contacts may include forming an under-bump metallization (UBM) structure in contact with the last RDL (e.g., the third redistribution layer) followed solder ball drop to complete the wafer-level -package.
Chip 120 may be an integrated circuit fabricated on a semiconductor wafer (not shown), for example, in semiconductor device fabrication facility. The semiconductor wafer may be processed up to a final metallization stage for making I/O contact pads (e.g., contacts 123-125, etc.) on a top surface (e.g., surface 122) of chip 120. The semiconductor wafer may be then diced, and chips 120 may be retrieved, for example, as individual semiconductor die.
As shown in
In some implementations, the first redistribution layer may be formed by lithographic patterning of the evaporated or sputtered conductive material of conductor layer 193.
Next,
In some implementations, the evaporated or sputtered conductive material of conductor layer 193 may be used as a seed layer for electroplating additional conductive material to form the first redistribution layer.
Next,
As shown in
Patterned conductor layer 196 may be configured (e.g., shaped or patterned) to serve as the first redistribution layer (RDL) to carry signals to, and from, at least one I/O contact on the chip in the fan-out package of the IC chip (at step 250 of method 200). A shape or pattern of patterned conductor layer 196 is defined, for example, by a layout of openings 195 in patterned photoresist mask layer 194 (
By using different layouts of openings 195 in patterned photoresist mask layer 194, different shapes or patterns of patterned conductor layer 196 in fan-out space 111 surrounding chip 120 can be obtained. The different shapes or patterns of patterned conductor layer 196 may include any kind of geometrical shape (e.g., wide area or trace).
Further, the wafer-level processing steps to make the multi-layer fan-out wafer-level package (e.g., package 100) of chips 120 may include forming alternating additional passivating layers and additional RDLs (e.g., at step 260 of method 200) to complete metallization structure 160 on the reconstituted wafer 190.
Additional wafer-level processing steps (e.g., at step 270 of method 200) to complete the multi-layer fan-out wafer-level package (e.g., package 100) of chips 120 may include forming external contacts (e.g., solder balls 150) of package 100. As shown in
After the external contacts (e.g., solder balls) are formed on reconstituted wafer 190, wafer 190 may be singulated or diced (not shown) to retrieve individual multi-layer packages of individual chips 120.
It will be understood that, in the foregoing description, when an element, such as a layer, a region, a substrate, or component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.
As used in the specification and claims, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.
Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.
While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.
