Method and structure of monolithically integrated IC and resistive memory using IC foundry-compatible processes

Abstract

The present invention relates to integrating a resistive memory device on top of an IC substrate monolithically using IC-foundry compatible processes. A method for forming an integrated circuit includes receiving a semiconductor substrate having a CMOS IC device formed on a surface region, forming a dielectric layer overlying the CMOS IC device, forming first electrodes over the dielectric layer in a first direction, forming second electrodes over the first electrodes in along a second direction different from the first direction, and forming a two-terminal resistive memory cell at each intersection of the first electrodes and the second electrodes using foundry-compatible processes, including: forming a resistive switching material having a controllable resistance, disposing an interface material including p-doped polycrystalline silicon germanium—containing material between the resistive switching material and the first electrodes, and disposing an active metal material between the resistive switching material and the second electrodes.

Description

BACKGROUND OF THE INVENTION

The present invention relates to monolithic techniques for integrating CMOS integrated circuit devices and solid state resistive devices used for memory storage. More particularly, some embodiments of the present invention provide methods and resulting devices including resistive memory devices and/or integrated circuits using standard IC foundry-compatible processes. Merely by way of example, embodiments of the invention can be applied to logic devices, PLD, processors, controllers, memories, and the like.

Resistive random-access memories (RRAMs) have generated significant interest recently as a potential candidate for ultra-high density non-volatile information storage. A typical RRAM device has an insulator layer provided between a pair of electrodes and exhibits electrical pulse induced hysteretic resistance switching effects.

The resistance switching has been explained by the formation of conductive filaments inside the insulator due to Joule heating and electrochemical processes in binary oxides (e.g. NiO and TiO2) or redox processes for ionic conductors including oxides, chalcogenides and polymers. Resistance switching has also been explained by field assisted diffusion of ions in TiO2 and amorphous silicon (a-Si) films.

In the case of a-Si structures, voltage-induced diffusion of metal ions into the silicon leads to the formation of conductive filaments that reduce the resistance of the a-Si structure. These filaments remain after the biasing voltage is removed, thereby giving the device its non-volatile characteristic, and they can be removed by reverse flow of the ions back toward the metal electrode under the motive force of a reverse polarity applied voltage.

Resistive devices formed by an a-Si structure provided between two metal electrodes have been shown to exhibit this controllable resistive characteristic. However, such devices typically have micron sized filaments which may prevent them from being scaled down to the sub-100 nanometer range. Such devices may also require high forming voltages that can lead to device damage and can limit production yields.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to solid state resistive devices used for memory storage. More particularly, the present invention relates to integrating a resistive random access memory on top of an IC substrate monolithically using IC-foundry compatible processes (e.g. a CMOS compatible backend process). In various embodiments, the IC substrate is completed first using standard IC processes. An insulating layer, e.g. dielectric, oxide layer is then added on top of the IC substrate. Subsequent CMOS compatible processes then define a solid-state resistive device. In some embodiments, the solid-state resistive device may be formed using standing CMOS processes from a semiconductor foundry.

In an embodiment, a monolithic integrated circuit and resistive memory device is disclosed. An integrated circuit (IC) substrate is provided having one or more electronic devices formed upon a substrate. The electronic devices may include transistors. On top of the IC substrate, memory devices having a crossbar array structure are formed thereon using CMOS-compatible processes, i.e. IC foundry compatible processes. In various embodiments, the memory device comprises a first array of first electrodes extending along a first direction; a second array of second electrodes extending along a second direction, each second electrode having a polycrystalline semiconductor layer including silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. Each intersection of the first array and the second array defines a two-terminal resistive memory cell. In some embodiments, the IC substrate may be formed at the same foundry as the foundry that forms the two-terminal resistive memory cell. In other embodiments, the IC substrate may be formed at a first semiconductor foundry, and the two-terminal resistive memory cell may be formed on top of the IC substrate at a second semiconductor foundry.

In another embodiment, the monolithic integrated circuit includes a resistive memory device where the non-crystalline silicon structure includes amorphous silicon, and the polycrystalline semiconductor layer includes a polycrystalline silicon-germanium.

In another embodiment, the monolithic integrated circuit includes a resistive memory device that includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a noncrystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell.

In yet another embodiment, a method for fabricating a monolithic integrated circuit and resistive memory device includes the following steps. The method includes providing a first semiconductor substrate having a first surface region and forming one or more CMOS integrated circuit devices, e.g. transistors, logic, etc., overlying the first surface region. The CMOS integrated circuit device region has a CMOS surface region. A dielectric layer is formed overlying the CMOS surface region. The method includes: forming a bottom electrode over the CMOS surface region, the bottom electrode including a polycrystalline semiconductor layer that includes silicon; forming a switching medium over the bottom electrode, the switching medium defining a region wherein a filament is to be formed when a program voltage is applied; and forming a top electrode over the switching medium, the top electrode configured to provide at least part of metal particles needed to form the filament in the region defined in the switching medium. Interconnections may be formed between one or more CMOS integrated circuit devices and the top electrode and/or the bottom electrode. Using this architecture and fabrication flow, it is feasible and cost-effective to make an array of resistive memory devices on a single CMOS chip.

The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

As used herein, the term “nanoscale” or “nanostructure” refers to a structure having at least one dimension in the nanoscale range; for example, structures having a diameter or plural cross-sectional dimensions within the general range of 0.1 to 200 nanometers. This includes structures having all three spatial dimensions in the nanoscale; for example, a cylindrical nanocolumn or nanopillar having a length that is on the same order as its nanoscale diameter. Nanostructures can include the various nanoscale structures known to those skilled in the art; for example, nanotubes, nanowires, nanorods, nanocolumns, nanopillars, nanoparticles, and nanofibers.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and wherein:

FIG. 1 illustrates a non-volatile solid state resistive device including a bottom electrode, a switching medium, and a top electrode according to an embodiment of the present invention;

FIG. 2 illustrates resistance switching characteristics of device according to an embodiment of the present invention;

FIG. 3A illustrates a two-terminal device that is placed in an ON state by applying a program voltage Vpth to the top electrode;

FIG. 3B illustrates a two-terminal device that is placed in an OFF state by applying an erase voltage Veth to the top electrode;

FIG. 4 illustrates a semiconductor device having a substrate with a CMOS device implemented in a frontend CMOS process and a two-terminal resistive memory implemented in a backend CMOS process according to an embodiment of the present invention;

FIG. 5 illustrates two-terminal resistive memory cells arranged in a crossbar memory array according to an embodiment of the present invention;

FIG. 6A illustrates a nanoscale non-volatile solid state resistive memory having a polysilicon layer as part of a bottom electrode according to an embodiment of the present invention;

FIG. 6B illustrates a nanoscale non-volatile solid state resistive memory having a polycrystalline silicon-germanium (poly-SiGe) layer as part of a bottom electrode according to an embodiment of the present invention; and

FIGS. 7A-7E illustrate a process for forming a resistive memory according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a memory cell 101 in a non-volatile solid state resistive device 100 including a bottom electrode 102, a switching medium 104, and a top electrode 106 according an embodiment of the present invention. Switching medium 104 exhibits a resistance that can be selectively set to various values, and reset, using appropriate control circuitry. Memory cell 101 is a two-terminal nanoscale resistive random-access memory (RRAM) in the present embodiment. Although not shown, one skilled in art would understand that device 100 includes a plurality of memory cells 101. One skilled in art would also appreciate that that memory cell 100 may be used as a programmable interconnect, variable capacitor or other types of devices.

RRAM is a two terminal memory having a switching medium provided between top and bottom electrodes. The resistance of the switching medium can be controlled by applying electrical signal to the electrodes. The electrical signal may be current-based or voltage-based. As used herein, the term “RRAM” or “resistive memory device” refers to a memory device (or memory cell) that uses a switching medium whose resistance can be controlled by applying electrical signal without ferro electricity, magnetization and phase change of the switching medium. For illustrative convenience, memory cell 101 and device 100 are referred collectively as “device 100” hereinafter unless the context makes it clear that the term refers solely to device 100.

In the present embodiment, device 100 is amorphous-silicon-based RRAM and uses amorphous silicon as switching medium 104. The resistance of the switching medium 104 changes according to formation or retrieval of a conductive filament inside the a-Si switching medium according to voltage applied. Top electrode 106 is a conductive layer containing silver (Ag) and acts as the source of filament-forming ions in the a-Si structure. Although silver is used in the present embodiment, it will be understood that the top electrode can be formed from various other suitable metals, such as gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), and cobalt (Co). Bottom electrode 102 is a boron-doped or other p-type polysilicon electrode 130 that is in contact with a lower end face of the a-Si structure.

FIG. 2 illustrates resistance switching characteristics of device 100 according to an embodiment of the present invention. The switching medium displays a bipolar switching mechanism. The resistance of the switching medium changes depending on the polarity and magnitude of the signal applied to the switching medium via the top and bottom electrodes. The device is changed into ON-state (low resistance state) when a positive voltage equal to or greater than a program threshold voltage (or program voltage) Vpth is applied. In an embodiment, the program voltage ranges between 1 volts to 4 volts depending on the materials used for the switching medium and the top electrode. The device is switched back to OFF-state (high resistance state) when a negative voltage of equal or greater magnitude than erase threshold voltage (or erase voltage) Veth is applied. In an embodiment, the erase voltage ranges from −1 volts to −4 volts. The device state is not affected if the bias applied is between two threshold voltages Vpth and Veth, which enables the low-voltage read process. Once device 100 is set to a specific resistance state, the device retains the information for a certain period (or retention time) without electrical power, as explained in U.S. patent application Ser. No. 12/575,921, filed on Oct. 8, 2009, U.S. patent application Ser. No. 12/582,086, filed on Oct. 20, 2009, and U.S. patent application Ser. No. 12/814,410, filed on Jun. 11, 2010, which are all incorporated by reference in their entirety.

In an embodiment, device 100 illustrates a rectifying switching characteristic. Device 100 shows a diode-like behavior at ON-state so that the current in ON-state only flow at positive bias but not at negative bias. Device 100, however, remains in ON-state even though no current is detected as long as the applied negative voltage does not equal or exceed Veth.

FIGS. 3A and 3B illustrate a switching mechanism of device 100 during ON and OFF states according to an embodiment of the present invention. The switching in an a-Si medium 104 is based on formation and retrieval of a nanoscale conductive filament (or a plurality of filaments) in a filament region in the a-Si medium according to the program and the erase voltages applied to the electrodes of device 100.

FIG. 3A illustrates device 100 that is placed in an ON state by applying a program voltage Vpth to the top electrode. Switching medium 104 made of a-Si is provided between bottom electrode 102 and top electrode 106. An upper portion of the switching medium includes a metallic region (or conductive path) 302 that extends from the top electrode to about 10 nm above the bottom electrode. Metallic region 302 is formed during an electro forming process when a slightly larger voltage (e.g., 3˜5 volts), than a subsequent program voltage is applied to the top electrode. Alternatively, an extended voltage pulse (e.g., 100 μs to 1 s) may be applied to the top electrode to form the metallic region. This relatively large or voltage pulse causes the electric field induced diffusion of the metal ions from the top electrode toward the bottom electrode, thereby forming a continuous conductive path 303. A lower portion of the switching medium defines a filament region 304 wherein a filament 305 is formed when a program voltage Vpth is applied after the electroforming process. In certain implementations, the conductive path 303 and the filament 305 can be also formed together in a single step, e.g., during the electroforming process or when program voltage Vpth is applied. The filament comprises a series of metal particles that are trapped in defect sites in a lower portion of the switching medium when a program voltage applied provides sufficient activation energy to push a number of metal ions from metallic region 302 toward the bottom electrode.

Filament 305 is believed to be comprised of a collection of metal particles that are separated from each other by the non-conducting switching medium and does not define a continuous conductive path, unlike the path 303 in the metallic region. Filament 305 extends about 2-10 nm depending on implementation. The conduction mechanism in the ON state is electrons tunneling through the metal particles in the filament. The device resistance is dominated by the tunneling resistance between a metal particle 306 and the bottom electrode. Metal particle 306 is the metal particle in the filament region that is closest to the bottom electrode and is the last metal particle in the filament region in the ON state.

FIG. 3B illustrates device 100 that is placed in an OFF state by applying an erase voltage Veth to the top electrode. The erase voltage exerts sufficient electromagnetic force to dislodge the metal particles trapped in the defects sites of the a-Si and retrieves at least part of the filament from filament region 304. A metal particle 308 that is closest to the bottom electrode in the OFF state is separated from the bottom electrode by a greater distance than the metal particle 306 during the ON state. This increased distance between the metal particle 308 and the bottom electrodes places the device 100 in a high resistance state compared to the ON state.

In an embodiment, the resistance ratio between the ON/OFF states ranges from 10E3 to 10E7. Device 100 behaves like a resistor in the ON state and a capacitor in the OFF state (i.e., the switching medium does not conduct current in any meaningful amount and behaves as a dielectric in the OFF state). In an implementation, the resistance is 10E5 Ohm in the ON state and 10E10 Ohm in the OFF state. In another implementation, the resistance is 10E4 Ohm in the ON state and 10E9 Ohm in the OFF state. In yet another implementation, the resistance is at least 10E7 Ohm in the OFF state.

In an embodiment, device 100 exhibits controllable ON-state current flow of 10 nA-10 mA and endurance of greater 10E6. Device 100 exhibits relatively a retention time of 6 years at room temperature.

FIG. 4 illustrates a semiconductor device 400 having a semiconductor substrate 410 including CMOS device, e.g. transistor 412, and a two-terminal resistive memory 402, implemented in a backend process according to an embodiment of the present invention. In various embodiments, resistive memory 402 is integrated with conventional CMOS circuitry, such as transistor 412, in one transistor-one-resistive-device (1T 1R) configuration. As illustrated, semiconductor substrate 410 includes a conventional dielectric material 414 with metal interconnects 416 formed therethrough that couple resistive memory 402 to transistor 412.

Resistive memory 402 includes a bottom electrode 404, a switching medium 406, and a top electrode 408. Switching medium 406 exhibits a resistance that can be selectively set to various values according to the voltages applied to the top and bottom electrodes 408, 404. Resistive memory 402 corresponds to memory cell 100 and in this example, is connected with a select transistor 412 in series. Select transistor 412 controls the location of the switching element to be accessed.

FIG. 5 illustrates two-terminal resistive memory cells arranged in a crossbar memory array 500 according to an embodiment of the present invention. Crossbar memory array 500 is implemented in a backend CMOS compatible process, i.e. using standard IC foundry compatible processes. Metal interconnects, transistors, or other circuits including one or more other crossbar memory arrays may be formed below crossbar memory array 500 using standard IC foundry compatible processes.

Crossbar memory array 500 includes a parallel array of bottom electrodes 502 extending along a first direction. In an embodiment, bottom electrodes 502 includes a bottom metal (not shown) and a polycrystalline silicon-germanium (not shown) formed on the bottom metal. The bottom electrodes are nanoscale in the present embodiment. For example, the bottom electrodes have a width of about 40 nm and pitch of about 60 nm.

A parallel array of top electrodes 504 extends along a second direction to intersect the bottom electrodes. The top electrodes include metal capable of supplying filament forming ions such as silver (Ag), gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co). In an embodiment, the top electrodes and the bottom electrodes are orthogonal to each other. The top electrodes are nanowires having a width of about 60 nm and a pitch of about 150 nm.

Each intersection 506 of the two arrays defines a two-terminal resistive memory cell 508. Examples of cell 508 include two-terminal device 100 shown in FIG. 1 and two terminal devices 600 and 650 shown in FIG. 6A and 6B. The memory cell at each intersection 506 includes two electrodes separated by a switching layer 510. In the present embodiment, the switching layer includes amorphous silicon or other non-crystalline silicon. The switching structure can be the same width or narrower than the bottom electrode. In some embodiments, each memory cell in a crossbar memory array can store a single bit. In other embodiments, the memory cells exhibit multi-level resistance thereby allowing storage of a plurality of bits at each cell.

The crossbar memory array as described above may be fabricated on a silicon substrate, as illustrated in FIG. 4, in an embodiment. In another embodiment, III-V type semiconductor compounds (such as Gallium Arsenide GaAs, Gallium Nitride GaN, Boron Nitride BN etc.) or II-VI type semiconductor compounds (such as Cadmium Selenide, Zinc Telluride etc.) may also be used as the substrate.

FIG. 6A illustrates a nanoscale non-volatile solid state resistive memory 600 having a polysilicon layer as part of a bottom electrode according to an embodiment of the present invention. Resistive memory 600 is a two-terminal RRAM in the present embodiment. Resistive memory 600 includes a bottom electrode 604, a switching layer 606, and a top electrode 608. Resistive memory 600 is formed over a substrate 602. In an embodiment, substrate 602 is a semiconductor substrate, e.g., a silicon substrate or a compound substrate of a III-V or II-VI type, having CMOS devices formed therein, as illustrated in FIG. 4. In an embodiment, the substrate is not made of semiconductor material, e.g., is made of plastic.

Bottom electrode 604 includes a bottom metal layer 610 formed on a substrate and a p-type polysilicon layer 612 formed on the bottom metal layer. The p-type polysilicon layer has a thickness of 10˜30 nm, and the bottom metal layer has a thickness of about 150 nm according to an implementation. The thicknesses of these layers may vary depending on implementation. In the present embodiment, p-type polysilicon layer 612 is a boron-doped polysilicon, and bottom metal layer 610 is made of metal, e.g., tungsten, aluminum or copper, or an alloy thereof. In an implementation, the bottom metal is replaced with non-metal material that has a higher conductivity than the p-type polysilicon layer.

P-type polysilicon 612 facilitates the defect site formation in the a-Si switching medium to be controllable by enabling the tuning of the amorphous silicon deposition on the p-type polysilicon, so that the defect density in the filament region does not become too high. When metal, e.g., Nickel or other metal, is used as a platform whereon the amorphous silicon switching layer is formed, the inventors have found that the filament formation was difficult to control due to the excess number of defect sites formed at the a-Si/metal interface. Furthermore, a-Si can react with the bottom metal electrode during the a-Si deposition, giving a-Si and metal alloy (silicide) at the interface. Accordingly, in addition to serving as an electrode, p-type polysilicon 612 serves as a platform that enables defect formation in the aSi switching layer to be controllable, e.g. layer 612 is an interface layer.

One issue associated with the use of polysilicon as part of bottom electrode 604 is the relatively high deposition temperature needed for polysilicon. Typically, polysilicon is deposited by pyrolyzing silane (SiH4) at 580 to 650° C. and the dopants provided therein are activated at 800° C. or higher temperature. However, a CMOS compatible backend process preferably should have thermal budget of 450° C. to limit damage or degradation of the existing structures (underlying CMOS devices, e.g. transistor 412). For example, if exposed to high temperature, aluminum interconnect may be degraded due to its low melting temperature. The relatively high deposition temperature of polysilicon can limit the use of resistive memory 600 in a backend process. Reducing the polysilicon deposition temperature to 450° C. or less, however, may hinder crystal formation and cause the resulting material to have undesirably high resistance. In addition, lowering the temperature decreases the deposition rate of polysilicon significantly and could make the fabrication process impractical.

FIG. 6B illustrates a nanoscale non-volatile solid state resistive memory 650 having a polycrystalline semiconductor layer, e.g., a polycrystalline silicon-germanium layer, as part of a bottom electrode according to an embodiment of the present invention. The polycrystalline semiconductor layer comprises material that can be deposited at a low temperature. One example such a polycrystalline semiconductor layer is polycrystalline silicon-germanium (poly-SiGe). Poly-SiGe can be deposited at a lower temperature than polysilicon because the low transition temperature from amorphous to polycrystalline of SiGe. In addition, boron doping has also been found to enhance the crystallization which further lowers the crystallization temperature. Poly-SiGe can be used to bring the thermal budget for deposition to be 450° C. or less, e.g., 400° C., and allow resistive memory 650 to be implemented more easily with a conventional CMOS technology. In other words, embodiments of the present invention, can be formed using IC foundry-compatible processes. Resistive memory 650 is an RRAM in the present embodiment, but may be other types of device in other embodiments.

Resistive memory 650 includes a bottom electrode 654, a switching layer 656, and a top electrode 658. Switching layer 656 is provided between the top and bottom electrodes and includes a-Si material whose resistance can be made to vary according to voltages applied. Resistive memory 650 is formed over a substrate 652. Substrate 652 maybe a semiconductor substrate, e.g., a silicon substrate or a compound substrate of a III-V or II-VI type. In an embodiment, the substrate is not made of semiconductor material, e.g., is made of plastic.

In an embodiment, resistive memory is formed in a backend process. Accordingly, substrate 652 may include transistors, metal interconnects, and other circuits so that resistive memory 650 overlies one or more of these circuit components. Because these are formed before the resistive memory, these are termed herein as front-end CMOS processes.

In an embodiment, bottom electrode 654 includes a bottom metal layer 660 formed on a substrate and a polycrystalline semiconductor layer (e.g., poly-SiGe layer) 662 (e.g. an interface layer) formed on the bottom metal layer. Poly-SiGe layer 662 has a thickness of 10 30 nm, and bottom metal layer 660 has a thickness of about 150 nm according to an implementation. The thicknesses of these layers may vary depending on implementation. Poly-SiGe layer 662 is boron-doped, and bottom metal layer 660 is made of metal, e.g., tungsten, aluminum or copper, or an alloy thereof. In an implementation, the bottom metal is replaced with nonmetal material that has a higher conductivity than the poly-SiGe layer.

Poly-SiGe 662 film exhibits many properties comparable to polysilicon. Like polysilicon, poly-SiGe 662 facilitates the defect site formation in the a-Si switching medium, so that the defect density in the filament region does not become too high. In addition to poly-SiGe, the polycrystalline semiconductor layer may include III-V type semiconductor compounds (such as Gallium Arsenide GaAs, Gallium Nitride GaN, Boron Nitride BN etc.) or II-VI type semiconductor compounds (such as Cadmium Selenide, Zinc Telluride etc.).

Switching layer 656 exhibits a resistance that can be selectively set to various values, and reset, using appropriate control circuitry. In an embodiment, switching layer 656 includes an a-Si structure having a thickness of 20-80 nm. The thickness of the amorphous silicon structure varies depending on the device size and configuration. In an embodiment, the a-Si structure is a film wherein the width and length are substantially greater than the thickness. Alternatively, the a-Si structure may be a pillar wherein the vertical dimension is more pronounced than the dimensions of width and length.

In an embodiment, switching layer 656 includes non-crystalline silicon structures, such as amorphous polysilicon (sometimes called nanocrystalline silicon, an amorphous phase that includes small grains of crystalline silicon). As used herein, the term “noncrystalline silicon” refers to amorphous silicon or amorphous poly-SiGe that exhibits controllable resistance, a combination thereof, or the like.

Top electrode 658 contains silver (Ag) as the source of filament-forming metal ions in the switching medium. In an embodiment, top electrode 658 includes an Ag film with a thickness of 150 nm. In other embodiments, the top electrode includes a stacked structure. For example, a Ag layer of about 50 nm is deposited on top of a-Si and another metal (e.g., TiN/W) of about 100 nm can be deposited on top of the Ag layer. The thickness may vary depending on the device size and implementation. Although silver is used in the present embodiment, it will be understood that the top electrode can be formed from various other suitable metals, such as gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co) or a metal stack (or stacks).

FIGS. 7 A-7E illustrate a process for forming a monolithically integrated device including integrated circuits and resistive memory, e.g., resistive memory cell 650, according to an embodiment of the present invention. FIG. 7A illustrates a simplified cross section diagram of components of a starting substrate 702 whereon a plurality of resistive memories is to be defined (FIG. 7A) various embodiments, substrate 702 may be a prime grade silicon substrate in the present embodiment. In other embodiments, other semiconductor materials such as III-V and II-VI type semiconductor compounds may be used as the substrate. Resistive memory cell 650 may be formed as part of a front-end process (e.g. before IC devices are formed) or a back-end process (e.g. after IC devices are formed on the IC substrate) depending on implementation. If used in a backend process, substrate 702, may include one or more layers of material formed and patterned thereon when the substrate is provided for the present process. For example in some embodiments, upon a starting substrate, a plurality of devices, such as transistor 412 (FIG. 4) are formed thereon, and then a dielectric layer such as oxide and/or nitride layer is deposited on top of a top metal layer of the IC wafer, as also sown in FIG. 4. In some embodiments, the dielectric layer is then patterned to form IC substrate 702, as illustrated.

A bottom metal layer 704 is formed over substrate 702 (FIG. 7B). One purpose of the bottom metal is to minimize the resistance of the bottom electrode to be formed. The bottom metal may not be needed in certain implementations. For example, as illustrated in FIG. 4, a bottom metal may be formed as part of IC substrate 420. The bottom metal can be gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), titanium nitride (TiN) or a stack (or stacks) of metals. The bottom metal may comprise metal having a high voltage threshold for ion migration (e.g., higher than that of the metal used for the top electrode).

An interfacelayer, e.g. polycrystalline semiconductor layer (e.g., poly-SiGe layer) 706 is formed over bottom metal layer 704 to define the bottom electrode having the bottom metal and the polycrystalline semiconductor layer (FIG. 7B). In some embodiments, the polycrystalline semiconductor layer (or poly-SiGe) is a p-type and has high doping concentration of 10E17˜10E21/cm³. In an embodiment, the poly-SiGe has a doping concentration of at least 1E20/cm³, e.g., about 5 E20/cm³. Poly-SiGe layer 706 may be doped with acceptors such as Boron (B) or Aluminum (AI). A certain amount of silicon within poly-SiGe layer 706 enables the formation of a-Si thereon to be controllable so that the defect density in the filament region does not become too high. Increasing the concentration of Ge, however, results in lower deposition temperature which is desirable when implementing or integrating resistive memory 650 in a CMOS compatible backend process. In an embodiment, the Ge concentration in poly-SiGe 706 is 60-95%. In another embodiment, the Ge concentration is 75-80%. In yet another embodiment, the Ge concentration is about 70%.

Poly-SiGe 706 layer is deposited over the bottom electrode at a relatively low temperature of 450° C. or less, e.g., 380-420° C., so that the formation of resistive memory 650 may be implemented in a CMOS compatible back-end process on IC substrate 702.

In an embodiment, poly-SiGe layer 706 is deposited by using a low pressure chemical vapor deposition (LPCVD) process at a chamber pressure of 2 Torr, at 400° C. The deposition temperature is lowered by increasing the concentration of Ge, so that the resulting poly-SiGe has the Ge concentration of about 70%. Gases input into the process chamber include: diborane (1%, H2 balance) at 10 sccm, SiH4 at 7 sccm, and GeH4 (10%) at 40 sccm. P-type impurities are doped into poly-SiGe by in-situ doping using B2H6 or BCh, or both. In various embodiments, the process for forming the interface layer is also compatible with IC foundry compatible processes.

In addition to LPCVD, other deposition techniques may also be used to deposit poly-SiGe over the bottom electrode, e.g., atmospheric pressure CVD (APCVD), ultra-high vacuum CVD (UHVCVD), aerosol assisted CVD (AACVD), plasma enhanced CVD (PECVD), microwave plasma assisted CVD (MPCVD), atomic layer CVD (ALCVD) or atomic layer epitaxy, hybrid physical-chemical vapor deposition (HPCVD), hot wire CVD (HWCVD), direct liquid injection CVD (DLICVD) and vapor phase epitaxy (VPE).

Referring to FIG. 7C, bottom metal 704 and p-type poly-SiGe 706 are patterned to obtain a bottom electrode 708 (corresponding to bottom electrode 604 of device 650) extending along a direction (e.g., horizontal direction). Although not shown, a plurality of bottom electrodes 708 extending along the direction in parallel is formed at this step. An insulating layer f5 is formed over the patterned bottom electrode and then planarized to expose the p-type poly-SiGe layer. Insulating layer 710 is silicon dioxide in an embodiment.

An amorphous silicon layer 712 is formed on the p-type poly-SiGe to a thickness of 2-30 nm (FIG. 7D). The a-Si layer defines a switching medium wherein a filament will be formed when a program voltage is applied to place the resistive memory in ON state. In an embodiment, the defect density of a-Si layer 712 may be increased to enable more metal particles to be trapped therein, thereby increasing the retention time and lowering the ON resistance of the device. For example, a-Si layer 712 may be provided with a relatively high defect density region provided proximate the bottom electrode and a relatively low defect density region provided proximate the top electrode.

Referring to FIG. 7E, a filament-forming-ion-supplying metal layer (or top electrode) 716 is formed over the a-Si layer. In the present embodiment, metal layer 716 includes silver. In other embodiments, metal layer 716 may include gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co). Palladium (Pd), Titanium nitride (TiN) or other materials 718, may be deposited over silver layer 716 as a passivation layer. The metal layer is patterned to form a top electrode (see top electrode 504 of device 500). The top electrode extends along a direction (e.g., a vertical direction in and out of the page) to form an angle with the bottom electrode, e.g., 90 degrees. Although not shown, resistive memory 650 includes a plurality of top electrodes extending along a first direction and a plurality of bottom electrodes 402 extending along a second direction to define a plurality of intersections. Each intersection defines a two-terminal resistive memory 650.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the ordering of layers on the substrate could be reversed, where the top electrode is provided below the bottom electrode depending on implementation. Accordingly the terms “top” and “bottom” should not be used to limit the relative positions of the source electrode that provides the filament-forming ions in the a-Si structure and an electrode provided at its opposing side. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A monolithic integrated circuit and crossbar array comprising: a semiconductor substrate having a first surface region;one or more CMOS integrated circuit devices provided on the surface region of the semiconductor substrate;a dielectric layer overlying the one or more CMOS integrated circuit devices;a first plurality of electrodes overlying the dielectric layer and extending along a first direction;a second plurality of electrodes overlying the first plurality of electrodes and extending along a second direction, wherein the first direction and the second direction are different; andwherein intersections of the first plurality of electrodes and the second plurality of electrodes define a two-terminal resistive memory cell comprising: a resistive switching material having a controllable resistance;an interface material disposed between the resistive switching material and the first plurality of electrodes, wherein the interface material comprises a foundry-compatible p-doped polycrystalline silicon germanium—containing material; andan active metal material disposed between the resistive switching material and the second plurality of electrodes.

2. The monolithic integrated circuit and crossbar array of claim 1, wherein the resistive switching material comprises amorphous silicon.

3. The monolithic integrated circuit and crossbar array of claim 2, wherein the resistive switching material comprises a nano-pillar structure disposed between first plurality of electrodes and the second plurality of electrodes;wherein the active metal material is selected from a group consisting of: silver (Ag), gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co).

4. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium material has a concentration within a range of about 60% Ge to about 80% g Ge.

5. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium-containing material has a concentration within a range of about 70% Ge to about 80% Ge; andwherein the polycrystalline silicon-germanium-containing material is formed by using a deposition temperature within a range of about 380° C. to about 420° C.

6. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium-containing material is deposited at a temperature of about 400° C.

7. The monolithic integrated circuit and crossbar array of claim 1, wherein the polycrystalline silicon-germanium-material is doped with boron with a doping concentration within a range of about 10E17/cm3 to about 10E20/cm3.

8. The monolithic integrated circuit and crossbar array of claim 1, wherein the resistive switching material is configured to have a ratio of an on resistance to off resistance within a range of about 10E3 to about 10E7.

9. The monolithic integrated circuit and crossbar array of claim 1, wherein the one or more CMOS integrated circuit devices provided on the surface region of the semiconductor substrate comprises a MOS transistor.

10. The monolithic integrated circuit and crossbar array of claim 1 further comprising a plurality of electrical contacts between the one or more CMOS integrated circuit devices and the first plurality of electrodes.

11. A method for forming an integrated circuit comprising: receiving a semiconductor substrate having one or more CMOS integrated circuit devices formed on a surface region of the semiconductor substrate;forming a dielectric layer overlying the one or more CMOS integrated circuit devices;forming a first plurality of electrodes overlying the dielectric layer and extending along a first direction;forming a second plurality of electrodes overlying the first plurality of electrodes and extending along a second direction, wherein the first direction and the second direction are different; andforming a two-terminal resistive memory cell at intersections of the first plurality of electrodes and the second plurality of electrodes using foundry-compatible processes, comprising: forming a resistive switching material having a controllable resistance;disposing an interface material between the resistive switching material and the first plurality of electrodes, wherein the interface material comprises p-doped polycrystalline silicon germanium—containing material; anddisposing an active metal material between the resistive switching material and the second plurality of electrodes.

12. The method of claim 11, wherein the forming the resistive switching material comprises depositing amorphous silicon material.

13. The method of claim 12, wherein the forming the resistive switching material further comprises: forming a nano-pillar structure between the first plurality of electrodes and the second plurality of electrodes;wherein the active metal material is selected from a group consisting of: silver (Ag), gold (Au), nickel (Ni), aluminum (AI), chromium (Cr), iron (Fe), manganese (Mn), tungsten (W), vanadium (V) and cobalt (Co).

14. The method of claim 11, wherein the polycrystalline silicon-germanium material has a concentration within a range of about 60% Ge to about 80% g GE.

15. The method of claim 12 wherein forming the polycrystalline silicon-germanium-containing material comprises depositing the polycrystalline silicon germanium-containing material at a deposition temperature within a range of about 380° C. to about 420° C.

16. The method of claim 11 wherein the disposing the interface material comprises doping the polycrystalline silicon germanium-containing material with boron with a doping concentration within a range of about 10E17/cm3 to about 10E20/cm3.

17. The method of claim 11, wherein the resistive switching material comprises an electric field controllable resistance via metal ion migration.

18. The method of claim 11 wherein the receiving the semiconductor substrate comprises: receiving the semiconductor substrate having the surface region; andforming the one or more CMOS integrated circuit devices on the surface region using foundry-compatible processes.

19. The method of claim 18 wherein the forming the one or more CMOS integrated circuit devices comprises forming a MOS transistor on the surface region.

20. The method claim 11 further comprising forming a plurality of electrical contacts between the one or more CMOS integrated circuit devices and the first plurality of electrodes.