The present application generally relates to semiconductor technology, and more particularly, to a semiconductor package and a method for making an electronic package.
System-in-Package (SiP) is a functional electronic system or sub-system that includes two or more heterogeneous semiconductor dice, such as a logic chip, a memory, integrated passive devices (IPD), RF filters, sensors, heat sinks, or antennas. A molded underfill (MUF) process is used in the manufacturing of SiPs that underfill and mold semiconductor devices. However, in the conventional MUF process, when the semiconductor packages are demolded from a mold chase, cracks and breakages frequently occur to the semiconductor packages.
Therefore, a need exists for a process for making an electronic package with an improved yield.
An objective of the present application is to provide a method for making an electronic package with an improved yield.
According to an aspect of the present application, an electronic package is provided. The electronic package comprises a substrate; a plurality of electronic components disposed on the substrate and an encapsulant cap for encapsulating the substrate and the plurality of electronic components, wherein the encapsulant cap comprises a top surface having a first region and a second region; and wherein the first region has a first roughness, the second region has a second roughness greater than the first roughness.
According to another aspect of the present application, an electronic package strip is provided. The electronic package strip includes a plurality of electronic packages. Each electronic package comprises a substrate, a plurality of electronic components disposed on the substrate, and an encapsulant cap for encapsulating the substrate and the plurality of electronic components, wherein the encapsulant cap comprises a top surface having a first region and a second region; and wherein the first region has a first roughness, the second region has a second roughness greater than the first roughness.
According to a further aspect of the present application, a method for making an electronic package is provided. The method comprises: placing a substrate strip with a plurality of electronic packages on a bottom mold chase, wherein each electronic package comprises a substrate and a plurality of electronic components disposed on the substrate; disposing a top mold chase over the electronic packages, wherein the top mold chase has a molding cavity to receive the electronic packages, and the molding cavity has a molding surface facing towards the electronic packages, and wherein the molding surface has a first molding region with a first roughness and a second molding region with a second roughness greater than the first roughness; injecting an encapsulant material into the molding cavity to form an encapsulant cap encapsulating the substrate and the plurality of electronic components of each electronic package, wherein the encapsulant cap comprises a top surface having a first region and a second region which correspond to the first molding region and the second molding region of the molding surface, respectively; detaching the electronic packages each encapsulated with an encapsulant cap from the bottom mold chase and the top mold chase; and separating the plurality of electronic packages from each other by singulation such that each electronic package is encapsulated with the encapsulant cap.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. Further, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The drawings referenced herein form a part of the specification. Features shown in the drawing illustrate only some embodiments of the application, and not of all embodiments of the application, unless the detailed description explicitly indicates otherwise, and readers of the specification should not make implications to the contrary.
The same reference numbers will be used throughout the drawings to refer to the same or like parts.
The following detailed description of exemplary embodiments of the application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the application. Those skilled in the art may further utilize other embodiments of the application, and make logical, mechanical, and other changes without departing from the spirit or scope of the application. Readers of the following detailed description should, therefore, not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiment of the application.
In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of “or” means “and/or” unless stated otherwise. Furthermore, the use of the term “including” as well as other forms such as “includes” and “included” is not limiting. In addition, terms such as “element” or “component” encompass both elements and components including one unit, and elements and components that include more than one subunit, unless specifically stated otherwise. Additionally, the section headings used herein are for organizational purposes only and are not to be construed as limiting the subject matter described.
As used herein, spatially relative terms, such as “beneath”, “below”, “above”, “over”, “on”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “side” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.
As aforementioned, cracks and breakages frequently occur to semiconductor packages when the semiconductor packages are demolded from a mold chase for a molding process. The inventors of the present application have found that the interface roughness between the semiconductor packages and the mold chase is low, so it may take a significant force required for separating the semiconductor packages (especially encapsulant caps of the semiconductor packages) from the mold chase, which may result in cracking and breakage issue of the semiconductor packages. In particular, when the encapsulant cap is demolded from the mold chase, two ends of the encapsulant cap can be detached from the mold chase, but the middle portion of the encapsulant cap may still tightly stick to the mold chase, thereby the electronic package may crack or break at the middle portion or close to the middle portion. However, the low-roughness encapsulant cap surfaces of semiconductor packages are generally required for laser marking because a smooth surface may improve the resolution of laser marking. Typically, a surface where laser marking is implemented requires relatively low roughness, such as less than 0.8 μm.
In order to address the above issue, the inventors of the present application conceived a new electronic package having an encapsulant cap with two types of roughness, and a method for making an electronic package, as elaborated below with more details.
As shown in
A plurality of electronic components 102 can be disposed on the top surface 101a of the substrate 101, with at least a portion of them covered by an encapsulant cap 105. Furthermore, a plurality of bumps 104 can be attached to the substrate 101 to facilitate the integration of the electronic package 100 with an external electronic device or system. In particular, the plurality of electronic components 102 are mounted on the top surface 101a of the substrate 101 and are encapsulated by the encapsulant cap 105. After being encapsulated, the electronic package 100 can be laser-marked with certain information of the electronic package 100. For example, the information may can be marked on a top surface of the encapsulant cap 105 including a specification and/or manufacturing information of the electronic package 100.
In the embodiment, the top surface 101a of the encapsulant cap 105 has a first region 1051 and a second region 1052. The first region 1051 has a first roughness, and the second region 1052 has a second roughness greater than the first roughness. The encapsulant cap 105 with two different roughness can bring many benefits. For example, during the MUF process, since the first roughness is lower than the second roughness, the second region having the second roughness is less likely to adhere to the mold chase than the first region when the encapsulant cap 105 is demolded from the mold chase. As such, it is much easier to remove the encapsulant cap 105 and the electronic package 100 from the mold chase, thereby avoiding cracking of the electronic packages. It should be noted that since the two-roughness top surface of the encapsulant cap 105 is to address the cracking issue during demolding, such top surface should be formed in a single molding and demolding process, rather than formed separately in two or more molding and demolding processes.
In some embodiments, the first region 1051 is higher than the second region 1052 relative to the substrate 101 as shown in
In some embodiments, the first electronic components 102a and/or the second electronic components 102b may include a plurality of semiconductor dices, semiconductor devices and/or discrete devices. For example, the electronic components may include a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, an RF circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, a memory controller, a memory device, an application specific integrated circuit, etc. The electronic components 102 may also be passive devices such as capacitors, inductors, or resistors. In the example shown in
In some embodiments, the encapsulant cap 105 is formed by an injection molding process such as the MUF process, which may reduce or prevent moisture and other contaminants from affecting the functionality and reliability of the electronic package. In some embodiments, an encapsulant material of the encapsulant cap 105 may be made of a general molding compound resin in a liquid form, for example, an epoxy-based resin, but the scope of this application is not limited thereto. In some embodiments, the encapsulant material is non-conductive material and provides structural support.
One or more laser markings can be formed in the first region 1051 of the top surface of the encapsulant cap 105, which may have the first roughness less than 0.8 μm. In some embodiments, the first roughness is in a range of 0.2 μm to 0.4 μm, in a range 0.4 μm to 0.6 μm or in a range of 0.6 μm to 0.8 μm. In some other embodiments, the first roughness is less than 0.4 μm. In some embodiments, the second roughness is greater than 1.8 μm. On the contrary, the second roughness of the second region 1052 is in a range of 1.8 μm to 3.2 μm, in a range of 3.2 μm to 6.3 μm or in a range of 6.3 μm to 12.5 μm. In some other embodiments, the second roughness is greater than 12.5 μm.
In some preferred embodiment, at a border between the first region 1051 and the second region 1051, a transition region 106 may be formed at the top surface of the encapsulant cap 105. The transition region 106 may be for example a rounded step or the like, which provides a smooth transition from the higher first region 1051 to the lower second region 1052. Such smooth transition can reduce or avoid stress concentration at the border between the first region 1051 and the second region 1051, thereby reducing the risk of cracking there.
As shown in
As shown in
It should be noted that although two regions 2051 and 2052 are shown in
In some embodiments, the first region 2051 may occupy a smaller area of the top surface of the encapsulant cap 205 than the second region 2052, as long as the surface area required for laser marking or other similar purposes can be satisfied. For example, the first region 2051 may occupy less than 50% of the top surface of the encapsulant cap 205. In some examples, the first region 2051 may occupy less than 40%, less than 30%, less than 20% or less than 10% of the top surface of the encapsulant cap 205. In some embodiments, the first region 2051 may occupy an area of smaller than 5 cm2 of the top surface of the encapsulant cap 205, or smaller than 1 cm2 of the top surface of the encapsulant cap 205, or even smaller.
Referring to
As shown in
The bottom mold chase 306 may be a part of a mold chase for molding, and mate with a top mold chase 307 which is the other part of the mold chase. In the embodiment, the bottom mold chase 306 is generally flat to support the substrate strip which is flat as well. In some other embodiments, the bottom mold chase may be a carrier with another shape that may fit for supporting and placing the substrate strip.
Afterwards, as shown in
In some embodiments, the mold chase including the top mold chase 307 and the bottom mold chase 306 may be formed of stainless steel, ceramics, copper, aluminum, or other types of materials. In some embodiments, the design of the mold chase including its configuration and layout can be modified according to the size and number of electronic packages to be disposed within the mold chase.
Afterwards, as shown in
As shown in
Then, as shown in
Afterwards, the substrate strip with the electronic packages can be singulated into individual electronic packages as shown in
Referring to
The discussion herein included numerous illustrative figures that showed various portions of an electronic package and a method for making the same. For illustrative clarity, such figures did not show all aspects of each example assembly. Any of the example devices and/or methods provided herein may share any or all characteristics with any or all other devices and/or methods provided herein. It could be understood that embodiments described in the context of one of the devices or methods are analogously valid for the other devices or methods. Similarly, embodiments described in the context of a device are analogously valid for a method, and vice versa. Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.
Various embodiments have been described herein with reference to the accompanying drawings. It will, however, be evident that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the claims that follow. Further, other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of one or more embodiments of the invention disclosed herein. It is intended, therefore, that this application and the examples herein be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following listing of exemplary claims.
Number | Date | Country | Kind |
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202211159326.X | Sep 2022 | CN | national |