Claims
- 1. A manufacturing method of a semiconductor device having a multi-layered wiring structure, comprising the steps of:forming a dielectric layer; forming a compound layer of a composition containing boron, nitrogen, and silicon on said dielectric layer by changing a ratio of flowrates of a gas containing silicon, a gas containing boron, and a gas containing nitrogen, to determine the composition of the compound layer; forming a predetermined pattern on said compound layer using a resist composed of an organic material; and etching said dielectric layer to shape it into a predetermined pattern using an etching gas capable of etching both said dielectric layer and said resist.
- 2. The manufacturing method of semiconductor device according to claim 1, further comprising, after said step of etching, a step of forming a wiring layer in said dielectric layer already etched into said predetermined shape.
- 3. The manufacturing method of semiconductor device according to claim 1, further comprising, after said step of forming a compound layer, a step of forming an adhesive layer containing silicon.
- 4. The manufacturing method of semiconductor device according to claim 1, wherein said step of forming a dielectric layer is executed by reduced-pressured deposition.
- 5. The manufacturing method of semiconductor device according to claim 1, wherein said step of forming a dielectric layer is executed by coating.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-321288 |
Oct 1998 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATION
This application is a Continuation of International Application No. PCT/JP99/05915, filed Oct. 26, 1999.
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Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/JP99/05915 |
Oct 1999 |
US |
Child |
09/658675 |
|
US |