Patent Application
20080169570
This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-003701, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. More particularly, the present invention relates to a semiconductor device having a multilayer interconnection structure and a method for manufacturing such a semiconductor device.
2. Description of the Related Art
There have been increasing demands for semiconductor devices to fabricate small-width, high-density and low-resistance interconnections to obtain a multilayer interconnection structure including aluminum (Al) or Al alloy including Al as a main component thereof. Meeting such demands requires embedding an interconnection material with a higher embedding performance into a small-diameter through-hole or via hole, and increasing the thickness of the Al interconnections to be formed on an insulating film.
For example, as described in Patent Publication JP-1995-263589-A1, the process of forming the multilayered Al interconnections includes a technique of: setting a substrate temperature at 150 degrees C. or higher; using a CVD (Chemical Vapor Deposition) technique and sputtering technique to simultaneously embed Al interconnection material into via holes and deposit an Al interconnection layer onto an insulating film; and then polishing the top portion of the Al interconnection layer by use of a CMP (Chemical Mechanical Polishing) process in order to form a desired thickness. A reflow sputtering technique is also known as the technique for forming the multilayered Al interconnections by setting a substrate temperature at for example, 400 degrees C. and causing the Al interconnection material to reflow. In this reflow sputtering technique, if the via holes have a smaller diameter, it is essential to set the substrate temperature higher than usual to enhance the embedding performance of the Al interconnection material. On the other hand, an excessively higher substrate temperature enhances the grain growth of Al in the Al interconnection material, with a problem that the surface roughness becomes larger in an attempt of forming an equal thickness.
As described above, if the Al interconnection material is deposited by using the reflow sputtering technique at a high temperature, via plugs or via plugs adapted to fill the through-holes and the Al interconnection layer located on the interlayer dielectric film are formed in a single process. In this technique, however, the depositing process is carried out by maintaining a higher substrate temperature of, for example, 390 degrees C. to 500 degrees C. level. Because of such a higher temperature, a large degree of roughness may be caused on the top surface of the Al interconnections. For example, if an AlCu alloy film having a thickness as large as 2 μm is formed by use of the reflow sputtering technique to form the Al interconnection layer, the surface roughness of the Al interconnection layer will be as large as 700 nm, for example. The large surface roughness may incur a halation to thereby cause a defective patterning in the subsequent photolithographic process. In addition, the surface roughness may incur ingress of etching solution into the wafer during a wet etching process subsequent to the photolithographic process. The etching solution may enter the semiconductor device and react with the Al interconnection material to generate a compound, which incurs a short-circuit failure between the interconnections.
In view of the above, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of reducing the surface roughness during the process for forming an interconnection layer having a relatively large thickness and via plugs within the through-holes, and thereby preventing occurrence of the defective patterning and short-circuit failure during the subsequent photolithographic process and wet etching process.
It is another object of the present invention to provide a semiconductor device manufactured by the process as described above.
The present invention provides a method for manufacturing a semiconductor device including: forming an interlayer dielectric film having a through-hole on a first interconnection pattern; depositing a via plug filling said through-hole and an interconnection layer on said interlayer dielectric film in a single step; polishing a top surface of said interconnection layer; forming an antireflection film on said polished surface of said interconnection layer; and patterning the antireflection film and the polished interconnection layer to form a second interconnection pattern.
The present invention also provides a semiconductor device including: a first interconnection pattern overlying a semiconductor substrate; an interlayer dielectric film having a through-hole through which a portion of the first interconnection pattern is exposed; a second interconnection pattern formed on the interlayer dielectric film and including a via plug filling the through-hole, the second interconnection pattern having a polished top surface; and an antireflection film formed on the second interconnection pattern.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
Now, exemplary embodiments of the present invention will be described with reference to accompanying drawings, wherein similar constituent elements are designated by similar reference numerals throughout the drawings.
In the process for forming the second interconnection layer (for example, second-layer interconnection layer), a Ti film configuring a barrier layer 18 is first formed within the via holes 17 and on the interlayer dielectric film 16. Subsequently, a hot-reflow sputtering technique is used to embed AlCu within the via holes 17 and deposit AlCu onto the interlayer dielectric film 16 at the same time, to thereby form an AlCu film 20 including via plugs.
Now detailed description will be given of the above-described process with reference to the steps of
On a surface portion of a semiconductor (Si) substrate (not illustrated), a shallow-trench-isolation (STI) structure, wells and transistors are formed, and a borophosphosilicate glass (BPSG) film is deposited over the resulting structure. The BPSG film is then subjected to a heat treatment in a steam ambient to cause the BPSG film to reflow so as to obtain a flat surface. A non-doped SiO2 film is deposited on the BPSG film by using a plasma-enhanced CVD process, and the resultant insulating layer is then polished by means of a CMP process, to form a first interlayer dielectric film 11 shown in
In the step of forming the first interconnections 15, first, the entire substrate (wafer) is introduced in an Ar-sputtering chamber and subjected to sputter etching of the first interlevel dielectric film by using Ar plasma for removing an equivalent oxide thickness (EOT) of 10 nm. Then, the wafer is transferred to a Ti-sputtering chamber, where the substrate temperature is set at 200 degrees C., to deposit a Ti film up to a thickness of 20 nm. Subsequently, the wafer is transferred to a TiN-sputtering chamber to deposit a TiN film up to a thickness of 30 nm by using a reactive sputtering technique, which introduces therein Ar and nitrogen for reaction. Thus, the TiN/Ti layer 12 is obtained. The resultant wafer is taken out from the chamber and subjected to a wet-cleaning treatment for the purpose of removing a variety of particles caused in the previous steps. Then, the wafer is introduced in a sputtering chamber and heated at a substrate temperature of 100 degrees C. in an Ar ambient at 8 Torr for 60 seconds for degassing. Thereafter, the wafer is subjected to an Al sputtering process at a substrate temperature of 300 degrees C. to form the AlCu film 13 having a thickness of 270 nm. The wafer is then transferred to a TiN-sputtering chamber, wherein heat is not applied to the substrate, to form a TiN film having a thickness of 27 nm. The TiN film configures the TiN antireflection layer 14. Subsequently, by using a plasma-enhanced CVD technique, a 50-nm-thick SiO2 film (not shown) to be used as a hard mask is formed, followed by forming a resist mask (not shown) thereon, which is then used for patterning using a dry etching technique to obtain the first interconnections 15.
By using a high-density plasma-enhanced CVD process, the second interlayer dielectric film 16 configured by SiO2 is deposited on the first interconnections 15 and the gap therebetween. The top surface of the second interlayer dielectric film 16 is polished for planarization using a CMP process. This step is shown in
Subsequently, a degassing treatment is conducted for the resultant wafer at a substrate temperature of, for example, 350 degrees C. in an Ar ambient at 8 Torr for 60 seconds. Then, the wafer is introduced in the Ar-sputtering chamber to subject the substrate to a sputter etching of the same for an EOT of 20 nm. The degassing treatment is conducted to prevent release of gas in the hot-reflow sputtering process performed later. If a significant amount of gas is released therein, the reflow is difficult to achieve.
Thereafter, the wafer is transferred to the Ti-sputtering chamber, where the substrate is not heated, to form the Ti barrier layer 18 having a thickness of 20 nm (
Subsequently, the wafer is transferred to an AlCu-sputtering chamber, where the substrate temperature is maintained at 200 degrees C., and a thin AlCu film 19 having a thickness of 250 nm is formed as a seed layer. The thickness is to be measured at a flat portion of the interlayer dielectric film 16. This step is shown in
Thereafter, AlCu is further deposited by sputtering onto the AlCu seed layer 19 at a substrate temperature of 445 degrees C. for 180 seconds so as to obtain a film thickness of 350 nm for the AlCu film. In the sputtering process, embedding of AlCu within the via holes 17 and deposition of the AlCu film onto the flat top surface of the second interlayer dielectric film 16 are simultaneously carried out to form the AlCu film 20. In this process, the substrate temperature is set at a higher temperature so as to reduce the deposition rate while providing the fluidity for the AlCu being deposited. In this process, the AlCu interconnections configuring an interconnection layer is formed while embedding AlCu within the via holes 17. This step is shown in
A higher temperature increases the fluidity, increases the grain diameter, and increases the surface roughness of the AlCu film. It should be noted to form the uniform profile of the AlCu film especially on the step portion and within the via holes 17 before the reflow processing. This is because a thin portion of the AlCu film at this stage causes agglomeration of AlCu particles in the middle stage of the reflow processing, which may prevent the embedding of AlCu from being perfected. More specifically, in the hot-reflow sputtering process, it is important to maintain an appropriate substrate temperature during the reflow sputtering and to form a uniform film of AlCu having an appropriate thickness before entering the reflow stage. The present embodiment in consideration of these points, uses conditions where the AlCu is embedded within via holes 17 having an aspect ratio as high as 5.6.
In the hot-reflow sputtering process, since the grain growth in Al is enhanced, the degree of the surface roughness of the AlCu film 20 is larger. The surface roughness of the AlCu film 20 depends upon the Ti barrier layer 18 used as an underlying layer, and upon the temperature during the hot-reflow sputtering of the AlCu film. The surface roughness is such that a difference of 15% to 25% is recognized in the height of the top surface on the entire profile in terms of ratio with respect to the thickness at the flat portion. For instance, assuming that the AlCu film 20 at the flat potion is 2 μm thick, a difference of around 0.5 μm or smaller may be observed in the height of the profile of the AlCu film. This surface roughness may significantly scatter the light incident thereto during the exposure process. Further, if the antireflection film is formed on the surface having such a surface roughness, the resultant antireflection film may have an uneven thickness. If the antireflection film has an excessively higher surface roughness, the overlying TiN film formed thereon may have pin holes, thereby incurring ingress of the wet etching solution and a defect in the resultant semiconductor device.
In order to solve the above problems, a CMP process is introduced to remove the surface roughness of the AlCu film 20 to obtain a uniform thickness thereof CMP of the AlCu film 20 has achieved satisfactory results in a technical field of manufacturing aluminum ROM discs or the like. For example, as described in Patent Publication JP-2000-219874-A1, it is possible to use as a polishing agent a composition of water and abrasive (alumina or SiO2) using basic aluminum sulfamate as a promotor. Under the conditions where micro pits do not exist and a mean surface roughness is equal to or below 1 to 2 nm, setting of a polishing rate of 40 to 250 nm/minute may be adopted.
The surface roughness of the AlCu film 20 formed using the hot-reflow sputtering technique may be removed using a CMP process for planarization by an amount of about 30% with respect to the thickness of the film deposited. The amount of polishing by the CMP process can be determined depending on the degree of the surface roughness.
On the surface of the AlCu film 20 polished by the CMP process, an undesirable thin Al oxide film is formed. To remove the undesirable thin Al oxide film, a degassing process is first carried out by heating the Al oxide film at 100 degrees C. in an Ar ambient, followed by Ar-sputter etching to remove the Al oxide layer by a thickness of around 10 nm. In this process, a setting of matching is employed in order to generate plasma, taking into account reflective waves. Plasma etching may be carried out while changing a setting therein depending on the case where an SiO2 film is formed on the surface of the AlCu film and the case where the AlCu film is formed on the entire surface in the sample at this stage.
Thereafter, the TiN film is deposited to a thickness of 27 nm by using a typical sputtering process without heating the substrate. A sectional view at this stage is shown in
The TiN antireflection layer 21 in the present embodiment has a uniform surface by virtue of the uniform underlying layer. The TiN antireflection layer 21 has a function of reducing the reflectance of the surface of the AlCu film 20 from some 90% to about 10% with respect to ultraviolet ray. Further, in the photolithographic process, the TiN antireflection layer 21 can suppress ingress of the wet processing solution into the AlCu film 20. If the underlying layer has a large degree of surface roughness, the reflectance will be higher.
A method for manufacturing a semiconductor device according to a second embodiment of the present invention will now be described with reference to
Next as shown in
In the second embodiment, since the TiN antireflection layer 14 of the first interconnections 15, which configures the underlying interconnection layer, is also etched during the pattern etching for the via holes 17, an Al—Ti alloy is generated in the AlCu film 20. This alloy has rough-hewn texture, and continuous parts and discontinuous parts coexist. For this reason, in the present embodiment, the contact resistance can be reduced as compared with the first embodiment, wherein the TiN antireflection layer 14 exists at an interface with the via plugs.
Next, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to
As described above, in the present invention, since the surface roughness of aluminum is removed by a CMP process to form a uniform surface thereof. Thus, it is possible to form thereon an antireflection film having a uniform top surface. Accordingly, an abnormal reflection such as halation on the surface of the interconnection layer can be suppressed, which allows forming of a fine pattern in the pattering process. In addition, the antireflection film having a flat surface has a function to act as a resistance film to the wet processing. Therefore, the antireflection film has also an effect to avoid a short-circuit failure caused by the compound produced as a result of the ingress of a wet processing solution. In the above circumstances, it is possible to eliminate drawbacks that exist when the formation of the interconnections and embedding of the via holes are executed in a single process step. Further, by adopting the process of the embodiments, the manufacturing cost of the semiconductor device may be reduced.
According to the semiconductor device of the above embodiments and the semiconductor devices manufactured by the method of the above embodiments, the via plugs embedded within via holes and an interconnection layer formed on an interlayer dielectric film are simultaneously deposited by use of a hot-reflow sputtering technique. Therefore, the deposition of the interconnection material may be performed using a smaller number of process steps. In addition, since the surface of the interconnection layer is polished before an antireflection film is formed, the photolithographic process carried out after the hot-reflow sputtering process prevents a halation defect, with the result that a failure of patterning process hardly occurs. Further, since an etchant or wet processing solution is hardly to cause ingress to the interconnection layer, a pattering failure or a short-circuit failure in the interconnections does not occur. This provides an advantageous effect that a highly reliable semiconductor device can be obtained while reducing the number of steps in the fabrication process.
While the invention has been particularly shown and described with reference to exemplary embodiment and modifications thereof, the invention is not limited to these embodiment and modifications. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined in the claims.
For example, in the above embodiment, the first interconnections correspond to the first-layer interconnections and the second interconnections correspond to the second layer interconnections. However, the first interconnection may correspond to the second-layer interconnections and the second interconnections may correspond to the third-layer interconnections, for example. Alternatively, the first interconnection pattern may be formed within the semiconductor substrate, such as a diffused region of the semiconductor device.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-003701 | Jan 2007 | JP | national |
