Patent Application
20100163168
This application claims priority from Japanese Patent Application No. 2008-332596 filed on Dec. 26, 2008 and Japanese Patent Application No. 2009-291744 filed on Dec. 24, 2009, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method for manufacturing a wiring board with a built-in component in which components, such as capacitors, are accommodated.
2. Description of Related Art
A semiconductor integrated circuit element (an IC chip) employed as a microprocessor, and the like, of a computer recently attains higher speed and greater functionality. In association with this, a number of terminals increases and a pitch between terminals is also narrower. In general, a plurality of terminals are densely arrayed on a bottom surface of an IC chip, and such a group of terminals is connected to a group of terminals on a mother board in the form of a flip-chip package. Since a pitch between the terminals of the IC chip greatly differs from a pitch between the terminals of the mother board, it is difficult to connect the IC chip directly onto the mother board. For this reason, there is in ordinary cases adopted a technique of fabricating a package in which an IC chip is mounted on a wiring board for implementation of the IC chip and of mounting the package on a mother board. In order to diminish switching noise of the IC chip and stabilize a source voltage, the wiring board used for implementation of the IC chip of the package of this type has hitherto been proposed to be provided with a capacitor. An example of a wiring board includes a capacitor embedded in a core substrate made of a polymeric material and build-up layers made respectively on a front face and a rear face of the core substrate (see; for instance, JP-A-2007-103789).
An example of a related-art method for manufacturing a wiring board is described hereunder. First, there is prepared a core substrate 204 that has an accommodation hole 203 opening toward both a first major surface 201 and a second major surface 202 and that is made of a polymeric material (see
Incidentally, in the resin layer 210, a first surface 211 adjoining the resin insulation layer which makes up the first build-up layer and a second surface 212 adjoining a resin insulation layer which makes up the second build-up layer sometimes become inactive as a result of adhesion of extraneous matters to the surfaces. In particular, the second surface 212 has remained in contact with an adhesive face of the adhesive tape 209 that easily attracts extraneous matters and has a high probability of becoming inactive. As a consequence, a problem may arise in adhesion between the resin layer 210 and the resin insulation layer adjoining the first surface 211 and the second surface 212 of the resin layer 210. Therefore, there is a risk of a wiring board manufactured becoming defective as a result of an occurrence of delamination between the resin layer 210 and the resin insulation layer, to thus deteriorate reliability of the wiring board.
The present invention has been conceived in light of the problem, and an object thereof is to provide a method for manufacturing a wiring board with a built-in component that enables manufacture of a wiring board with a highly reliable built-in component by enhancing adhesion between a resin layer and a resin insulation layer.
According to an aspect of the invention, there is provided a method for manufacturing a wiring board with a built-in component comprising: a core substrate preparation step for preparing a core substrate having a first major surface, a second major surface, and an accommodation hole opened at least in the first major surface; a component preparation step for preparing a component having a first component major surface, a second component major surface, and a side surface; an accommodation step for holding the component in the accommodation hole after the core substrate preparation step and the component preparation step, while the second major surface and the second component major surface are oriented toward a same side; a resin layer formation step for filling a gap between an inner wall surface of the accommodation hole and the side surface of the component with a resin layer after the accommodation step; a fixing step for hardening the resin layer after the resin layer formation step, to thus fix the component; an insulation layer formation step for forming a resin insulation layer on the second major surface and the second component major surface after the fixing step; and a surface modification step for modifying a surface of the resin layer, after the fixing step but before the insulation layer formation step.
Therefore, according to the method for manufacturing the wiring board with a built-in component, the surface of the resin layer is modified in the surface modification step, whereby the resin insulation layer can reliably be brought into close contact with the surface of the resin layer when the resin insulation layer is formed in the insulation layer formation step. For this reason, the occurrence of delamination, or the like, can be prevented. Consequently, a highly-reliable wiring board with a built-in component can be produced.
The method for manufacturing a wiring board with a built-in component is hereunder described.
In the core substrate preparation step, a core substrate of the wiring board with a built-in component is manufactured by the related-art well-known technique and prepared in advance. The core substrate is formed into the shape of a plate having, for instance, a first major surface, a second major surface situated at an opposite position, and an accommodation hole for housing a component. The accommodation hole may also be a closed-end hole opened in only the first major surface or a through hole opened in both the first major surface and the second major surface.
Although particular limitations are not imposed on a material for forming a core material, a preferred core substrate is mainly made of a polymeric material. A specific example of polymeric materials used for forming a core substrate may by EP resins (epoxy resins), PI resins (Polyimide resins), BT (bismaleimide triazine) resins, PPE (polyphenylene ether) resins, or the like. In addition, a composite material containing any of the resins and an organic fiber, such as a glass fiber (a glass woven fabric or a glass nonwoven fabric) and a polyamide fabric, may also be used.
In the component preparation step, components for forming the wiring board with a built-in component are manufactured and prepared in advance by means of a hitherto well-known technique. A component has a first component primary surface, a second component primary surface, and a side surface. Although the shape of a component can arbitrarily be set, the first component primary surface is preferably a plate that is larger than the component side surface in terms of an area. By means of this shape, when the component is held in the accommodation hole, a distance between an inner wall surface of the accommodation hole and the side surface of the component becomes shorter, so that the volume of a resin layer arranged in the accommodation hole does not need to be much increased. A polygonal shape with a plurality of sides when viewed in a plane direction is preferable as the shape of the component achieved when viewed in a plane direction. The polygonal shape achieved when viewed in a plane direction includes; for instance, a substantially-rectangular shape achieved when viewed in a plane direction, a substantially-triangle shape achieved when viewed in a plane direction, a hexagonal shape achieved when viewed in a plane direction, and the like. In particular, a substantially-rectangular shape achieved when viewed in a plane direction, which is a common shape, is desirable. The word “substantially-rectangular shape achieved when viewed in a plane direction” is assumed to imply a shape with chamfered corners and a shape with partially-curved sides as well as a perfect rectangular shape achieved when viewed in a plane direction.
A capacitor, a semiconductor integrated circuit element (an IC chip), a MEMS (Micro Electro Mechanical Systems) element manufactured through semiconductor manufacturing processes, and the like, can be mentioned as the preferred components. DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and the like, can be mentioned as an IC chip. The word “semiconductor integrated circuit element” principally refers to an element used as a microprocessor of a computer, and the like.
A preferred example of the capacitor may be a chip capacitor. Another example of the capacitor may be a capacitor including: a plurality of internal electrode layers stacked with dielectric layers sandwiched therebetween; a plurality of intra-capacitor via conductors connected to the plurality of internal electrode layers; and a plurality of surface electrodes connected to at least ends of the second component major surface in the plurality of intra-capacitor via conductors. A preferred capacitor is of a via array type in which the plurality of intra-capacitor via conductors are arranged on the whole in the form of an array. Such a structure enables a reduction in inductance of a capacitor and a high-speed power supply for absorbing noise and smoothing power fluctuations. Further, it becomes easy to make the entirety of the capacitor compact and, by extension, make the entire wiring board with a built-in component compact. Moreover, the capacitor is easy to achieve high electrostatic capacitance for its compactness and can supply more stable power.
A dielectric layer including a ceramic dielectric layer, a resin dielectric layer, and a ceramic-resin composite material, and others, is mentioned as the dielectric layer in a capacitor. A sintered body of high-temperature calcined ceramic, such as alumina, aluminum nitride, boron nitride, silicon carbide, and silicon nitride, is preferably used as the ceramic dielectric layer. In addition, a sintered body of low-temperature calcined ceramic, such as glass ceramic produced by adding borosilicate-based glass or lead-borosilicate-based glass to an inorganic filler, such as alumina, is preferably used. In this case, it is also preferable to use a sintered body of dielectric ceramic, such as barium titanate, lead titanate, and strontium titanate, according to an application. When a sintered body of the dielectric ceramic is used, it becomes easy to materialize a capacitor having great electrostatic capacity. A resin, such as an epoxy resin and a polytetrafluoroethylene (PTFE) resin containing an adhesive, is preferably used as the resin dielectric layer. In relation to the dielectric layer containing the ceramic-resin composite material, barium titanate, lead titanate, strontium titanate, and the like, is preferably used as ceramic. Thermosetting resins, such as an epoxy resin, a phenolic resin, an urethane resin, a silicone resin, a polyimide resin, and an unsaturated polyester resin; thermoplastic resins, such as a polycarbonate resin, an acrylic resin, a polyacetal resin, and a polypropylene resin; and lattices, such as nitrile-butadiene rubber, styrene-butadiene rubber, and fluororubber; are preferably used as a resin material.
No limitations are imposed on the internal electrode layer, the intra-capacitor via conductors, and the surface electrode. However, when the dielectric layer is a ceramic dielectric layer, a metallized conductor, for instance, is preferable as the dielectric layer. The metallized conductor is made by applying a conductor paste including metal powder by means of a related-art known technique; for instance, a metalize-printing technique and sintering the paste. When a metallized conductor and a ceramic dielectric layer are produced by means of a co-firing metallization technique, metallic powder contained in a metallized conductor must exhibit a melting point that is higher than a calcination temperature of the ceramic dielectric layer. For instance, when the ceramic dielectric layer is made of so-called high-temperature sintered ceramic (e.g., alumina, and the like), nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), or an alloy thereof, can be selected as metallic powder in the metallized conductor. When the ceramic dielectric layer is made of so-called low-temperature sintered ceramic (e.g., glass ceramic, and the like), copper (Cu), silver (Ag), or an alloy thereof can be selected as metallic powder in the metallized conductor.
In a subsequent accommodation step, the component is held in the accommodation hole while the second major surface and the second component major surface are oriented toward a same side. The component may also be held in the accommodation hole while fully embedded or while a portion of the component projects out of the opening of the accommodation hole. However, holding the component in the accommodation hole while fully embedded is preferable. If the component is held in such a manner, projection of the component from the opening of the accommodation hole, which would otherwise arise when processing pertaining to the accommodation step is completed, can be prevented. Further, when the resin insulation layer is formed over the second major surface and the second component major surface in the subsequent insulation layer formation step, the surface of the resin insulation layer contacting the second major surface and the second component major surface can be made smooth, so that dimensional accuracy of a wiring board with a built-in component is enhanced.
In a subsequent resin layer formation step, a gap between the inner wall surface of the accommodation hole and the side walls of the component is filled with a resin layer. The resin layer used for filling the gap between the inner wall surface of the accommodation hole and the side surface of the component in the resin layer formation step can appropriately be selected in consideration of an insulation property, heat resistance, humidity resistance, and the like. A preferred example of polymeric materials used for forming the resin layer may be an epoxy resin, a phenol resin, an urethane resin, a silicone resin, a polyimide resin, or the like. Further, a material made by adding the resin to a glass filler, and the like, may also be used as a polymeric material for making a resin layer.
The resin layer is further formed over the first major surface and the first component major surface in the resin layer formation step, and preferably comprises a resin sheet. In the resin layer formation step, the gap between the inner wall surface of the accommodation hole and the side surface of the component may also be filled with a portion of the resin sheet by heating the resin sheet and pressing the resin sheet against the core substrate and the component. By means of adoption of the structure, handling of the resin layer performed when the gap between the inner wall surface of the accommodation hole and the side surface of the component is filled with a resin layer becomes easier when compared with a case where the resin layer is liquid. Conversely, so long as the resin layer is liquid, a follow-up of a resin layer to a component will be improved.
It is also preferable that the resin layer be formed from a resin material having substantially the same composition as that of the resin insulation layer. By means of such a composition, a necessity for preparing a material differing from the resin insulation layer at the time of formation of a resin layer is obviated. Therefore, since the amount of material required to manufacture a wiring board with a built-in component is reduced, the cost of the wiring board with a built-in component can be curtailed.
In a subsequent fixing step, the resin layer is cured, to thus fix the component. When the resin layer is a thermosetting resin, heating an unhardened resin layer is mentioned as a step for hardening the resin layer. When the resin layer is a thermoplastic resin, cooling the resin layer heated in the resin layer formation step, and the like, is mentioned as a step for curing a resin layer.
If the second component major surface of the component and the surface of the resin layer are not level with the second major surface at a point in time when processing pertaining to the fixing step has completed, a surface of a resin insulation layer which will contact the second major surface, the second component major surface, and the surface of the resin layer cannot be made plane when the resin insulation layer is formed in a subsequent resin insulation layer formation step. As a result, dimensional accuracy of the wiring board with a built-in component is deteriorated. Even when the second component major surface and the surface of the resin layer are level with the second major surface, a problem will occur in adhesion between the resin layer and the resin insulation layer if the surface of the resin layer is inactive, which will in turn induce delamination between the resin layer and the resin insulation layer. Accordingly, processing pertaining to the accommodation step, the resin layer formation step, and the fixing step is performed while the opening of the accommodation hole in the second major surface, in which the accommodation hole has the openings in both the first major surface and the second major surface, is closed with an adhesive tape having a adhesive face. It is preferable to perform a surface modification step for modifying the surface of the resin layer after removal of the adhesive tape, after the fixing step and before the insulation layer formation step. In such a case, the second component major surface side of the component is bonded to the adhesive face of the adhesive tape in the accommodation step, to thus become temporarily fastened. Further, the second component major surface becomes level with the second major surface. Further, the surface of the resin layer becomes level with the second major surface and the second component major surface in the resin layer formation step. Therefore, the surface of the resin insulation layer contacting the second major surface, the second component major surface, and the surface of the resin layer can be made planar, so that the dimensional accuracy of the wiring board with a built-in component is enhanced. Further, since the surface of the resin layer is modified, the resin layer and the resin insulation layer can reliably be brought into close contact with each other, so that the occurrence of delamination can be prevented. Therefore, processing pertaining to a layered wiring area formation step for forming a layered wiring area including a resin insulation layer and a conductor layer stacked one on top of the other is performed. After the layered wiring area formation step, there is performed processing pertaining to a solder bump formation step for forming solder bumps used for implementing a semiconductor integrated circuit element on a conductor layer formed on the outermost resin insulation layer. In such a case, coplanarity of the surface of the layered wiring area is enhanced, so that heights of respective solder bumps become less likely to vary. Therefore, reliability of a connection between the solder bumps and the semiconductor integrated circuit element is enhanced.
The word “coplanarity” referred to in the present specification is an index exhibiting uniformity of the lowest surface of terminals defined in “Standards of Electronic Industries Association of Japan EIAJ ED-7304 Method for measuring specified BGA dimensions”; namely, uniformity of a surface of a layered wiring area.
In a subsequent insulation layer formation step, the resin insulation layer is formed over the second major surface and the second component major surface. It is preferable that the wiring board with a built-in component should have a layered wiring area including the resin insulation layer and the conductor layer stacked on the second major surface and the second component major surface. Such a structure makes it possible to configure electric circuitry in the layered wiring area, and hence the function of the wiring board with a built-in component can further be enhanced. Moreover, the layered wiring area is formed only over the second major surface and the second component major surface. A layered area having the same structure as that of the layered wiring area may also be formed over the first major surface and the first component major surface. If such a structure is adopted, electric circuitry can also be made in the layered area formed over the first major surface and the first component major surface as well as in the layered wiring area formed over the second major surface and the second component major surface. Hence, the function of the wiring board with a built-in component can further be enhanced.
The resin insulation layer can appropriately be selected in consideration of an insulation property, heat resistance, humidity resistance, and the like. A preferred example of polymeric materials used for forming the resin insulation layer may be: a thermosetting resin such as an epoxy resin, a phenol resin, an urethane resin, a silicone resin, or a polyimide resin; or a thermoplastic resin such as a polycarbonate resin, an acrylic resin, a polyacetal resin, and a polypropylene resin. In addition, there may also be used a composite material containing any of the resins and an organic fiber, such as a glass fiber (a glass woven fabric or a glass nonwoven fabric) and a polyamide fabric; or a resin-resin composite material made by impregnating a three-dimensional network-like fluorine-based resin base material, such as a continual porous PTFE, with a thermosetting resin such as an epoxy resin.
Meanwhile, the conductor layer can be formed from a conductive metallic material. For instance, copper, silver, iron, cobalt, nickel, and the like, are mentioned as a metallic material for forming a conductor layer. In particular, it is preferable that the conductor layer be made of copper which is inexpensive and exhibits high electrical conductivity. Further, it is desirable that the conductor layer be made by plating. When the conductor layer is made in such a way, the conductor layer can be made simply at low cost. Alternatively, the conductor layer may also be made by printing a metallic paste.
A surface modification step for modifying the surface of the resin layer is performed after the fixing step and before the insulation layer formation step. The term “surface modification” referred to herein means modification of a surface of a resin layer by elimination of the cause for making the surface of the resin layer inactive, through use of a physical technique and a chemical technique.
A method for modifying the surface of the resin layer by grinding the surface of the resin layer, and the like, can be mentioned as a method for modifying the surface of the resin layer by use of a physical method in the surface modification step. A method for modifying the surface of the resin layer by grinding the surface of the resin layer includes a method for grinding the surface of the resin layer by use of a belt sander machine equipped with sand paper, to thus modify the surface of the resin layer, a method for modifying the surface of the resin layer through buffing that involves coating an outer periphery of a disc-shaped nonwoven fabric with an abrasive material and pressing the nonwoven fabric against the surface of the resin layer while rotating the fabric, and others.
A method for modifying the surface of the resin layer by use of a chemical method in the surface modification step includes a method for modifying the surface of the resin layer by means of desmearing, a method for modifying the surface of the resin layer by performing coupling treatment using a silane coupling agent, and the like. Desmearing treatment includes wet desmearing, dry desmearing, and the like. The word “wet desmearing treatment” used herein refers to treatment for roughening the surface of the resin layer by causing a chemical, such as permanganate, to adhere to the surface of the resin layer.
After the fixing step and before the surface modification step, it is preferable to perform processing pertaining to a height adjustment step for making the surface of the resin layer level with a first-major surface-side surface of the conductor layer made on the first major surface by means of rendering the resin layer thin. In the surface modification step, it is preferable to modify both the surface of the resin layer and the first-major-surface-side surface of the conductor layer. In this case, the surface of the resin layer is made level with the first-major-surface-side surface of the conductor layer by performing processing pertaining to the height adjustment step. Therefore, when a resin insulation layer is formed over the first major surface and the first component major surface as well as on the second major surface and the second component major surface in an insulation layer formation step subsequent to the height adjustment step, the resin insulation layer can reliably be brought into close contact with the surface of the resin layer. As a consequence, the occurrence of delamination, and the like, can be prevented more thoroughly; hence, a wiring board with a built-in component exhibiting much superior reliability can be produced.
A technique for mechanically eliminating a portion of the resin layer, a technique for chemically eliminating a portion of the resin layer, and the like, can be mentioned as the technique for making the surface of the resin layer level with the first-major-surface-side surface of the conductor layer by means of rendering the resin layer thin in the height adjustment step. However, it is desirable to mechanically eliminate a portion of the resin layer in the height adjustment step. In such a case, processing pertaining to the height adjustment step can be performed in a more simple manner and at a lower cost when compared with a case where a portion of the resin layer is chemically eliminated.
A method for mechanically eliminating a portion of the resin layer includes a method for cutting a portion of the resin layer, a method for grinding the surface of the resin layer, and the like. The method for grinding the surface of the resin layer includes abrasion performed by means of a belt sander equipped with sand paper; buffing that involves coating an outer periphery of a disc-shaped nonwoven fabric with a grinding agent and pressing the fabric against the surface of the resin layer while rotating the fabric; and the like. In the meantime, the method for chemically eliminating a portion of the resin layer includes a method for eliminating a portion of the resin layer by means of an etchant.
Other features and advantages of the invention will be set forth in, or apparent from, the detailed description of the exemplary embodiments of the invention found below.
A wiring board with a built-in component according to an embodiment of the present invention is hereinbelow described in detail with reference to the drawings.
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The core substrate 11 of the embodiment assumes the shape of a substantially-rectangular plate measuring 25 mm high×25 mm wide×1.0 mm thick when viewed in a plane direction. The core substrate 11 exhibits a thermal expansion coefficient of 10 to 30 ppm/° C. or thereabouts (specifically 18 ppm/° C.) in the direction of a plane (an XY direction). A thermal expansion coefficient of the core substrate 11 refers to an average of measured values ranging from 0° C. to a glass transition temperature (Tg). The core substrate 11 is comprised of a base material 161 made of glass epoxy; a sub-base material 164 that is made on the upper and lower surfaces of the base material 161 and that is made of an epoxy resin doped with an inorganic filler, such as a silica filler; and a conductor layer 163 made of copper on upper and lower surfaces of the base material 161.
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For instance, when a voltage is applied between the internal power electrode layers 141 and the internal ground electrode layers 142 by application of power by way of the electrodes 111 and 112, positive electric charges, for instance, are accumulated in the internal power electrode layers 141, and negative electric charges, for instance, are accumulated in the internal ground electrode layers 142. As a consequence, the ceramic capacitor 101 functions as a capacitor. In the sintered ceramic element 104, the intra-capacitor power via conductors 131 and the intra-capacitor ground via conductors 132 are arranged adjacently to each other and set in such a way that electric currents flow in opposite directions in the intra-capacitor power via conductors 131 and the intra-capacitor ground via conductors 132. As a result, inductance components are reduced.
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A method for manufacturing the wiring board 10 of the embodiment is now described by reference to
In a core substrate preparation step S1, a semi-manufactured product of the core substrate 11 is manufactured in advance by means of the related-art known technique.
A semi-manufactured product of the core substrate 11 is manufactured as follows. There is first prepared a copper clad laminate (omitted from the drawings) including a base material 161 measuring 400 mm high×400 mm wide×0.8 mm thick with copper, foil affixed to both surfaces. Next, the copper foil on both surfaces of the copper clad laminate is etched, to thus pattern a conductor layer 163 by means of; for instance, a subtractive technique. Specifically, after subjected to electroless copper plating, the copper clad laminate is subjected to electrolytic copper plating while the electroless copper plated layer is taken as a common electrode. Moreover, the plate layer is laminated with a dry film, and the dry film is exposed and developed, whereby a predetermined pattern is made in the dry film. In this state, the unwanted electrolytic copper plated layer, the unwanted electroless copper plated layer, and the unwanted copper foil are etched away. Subsequently, the dry film is removed. After the upper and lower surfaces of the base material 161 and the conductor layer 163 have been roughened, an epoxy resin film doped with an inorganic filler (having a thickness of 80 μm) is affixed to both the upper and lower surfaces of the base material 161 by means of thermal compression, to thus produce a sub-base material 164.
A first-major-surface-side conductor layer 14 (e.g., 50 μm) is made in the form of a pattern on an upper surface of the upper sub-base material 164, and a second-major-surface-side conductor layer 15 (e.g., 50 μm) is made in the form of a pattern on a lower surface of the lower sub-base material 164. Specifically, after an upper surface of the upper sub-base material 164 and a lower surface of the lower sub-base material 164 are subjected to electroless copper plating, an etching resist is produced, and the sub-base materials are subjected to electrolytic copper plating. Further, the etching resist is removed, and the sub-base materials are subjected to soft etching. A layered product including the base material 161 and the sub-base materials 164 is bored by use of a rooter, to thus create a through hole, which is to form the accommodation hole 90, at a predetermined location. Thus, a semi-manufactured product of the core substrate 11 is produced (see
In a capacitor preparation step S2 (a component preparation step), the ceramic capacitor 101 is manufactured by the related-art known technique and prepared in advance.
The ceramic capacitor 101 is manufactured as follows. Specifically, a ceramic green sheet is made, and a nickel paste for an internal electrode layer is printed on the green sheet by means of screen printing. The green paste is then dried. An internal power electrode which will later become the internal power electrode layer 141 and an internal ground electrode which will later become the internal ground electrode layer 142 are thereby be produced. The green sheet on which the internal power electrode is produced and the green sheet on which the internal ground electrode is made are stacked one on top of the other. Pressing force is imparted to the green sheets in the direction in which the green sheets are piled, so as to integrate the respective green sheets. A layered green sheet product is thus produced.
Further, a plurality of via holes 130 are made in the layered green sheet product by use of a laser beam machine. The respective via holes 130 are filled with nickel paste for a via conductor by use of an unillustrated paste press filler machine. Next, paste is printed on lower surfaces of the layered green sheet products, thereby generating the power electrodes 111 and 121 and the ground electrodes 112 and 122 on the respective lower surface sides of the layered green sheet products so as to cover lower end faces of the respective conductors.
Subsequently, the layered green sheet products are dried, thereby hardening the respective electrodes 111, 112, 121, and 122 to a certain extent. The layered green sheet products are then subjected to dewaxing and are further sintered at a predetermined temperature for a predetermined period of time. As a consequence, barium titanate and nickel in the paste are sintered at the same time, to thus become a sintered ceramic element 104.
The respective electrodes 111, 112, 121, and 122 of the thus-produced sintered ceramic element 104 are subjected to electroless copper plating (having a thickness of about 10 μm). A copper plating layer is made over the respective electrodes 111, 112, 121, and 122, whereupon the ceramic capacitor 101 is completed.
In a subsequent accommodation step S3, an opening of the accommodation hole 90 adjoining the second major surface 13 is sealed with a removable adhesive tape 171. The adhesive tape 171 is supported by a support bed (omitted from the drawings). Next, the ceramic capacitor 101 is placed in the accommodation hole 90 while the first major surface 12 and the first capacitor major surface 102 are oriented in the same direction and while the second major surface 13 and the second capacitor major surface 103 are also oriented in another direction by use of a mounter (manufactured by Yamaha Motor Co., Ltd.) (see
In a subsequent resin layer formation step S4, the resin layer 92 is formed over the first major surface 12 and the first capacitor major surface 102, and the gap between the inner wall surface 91 of the accommodation hole 90 and the capacitor side surface 106 of the ceramic capacitor 101 is filled with a portion of the resin layer 92 (see
In a subsequent fixing step S5, the resin layer 92 is cured, to thus fix the ceramic capacitor 101 in the accommodation hole 90. Specifically, heat processing (curing, and the like) is carried out, to thus harden the resin layer 92, whereupon the ceramic capacitor 101 is fixed to the core substrate 11. After the fixing step S5, the adhesive tape 171 is removed. In short, processing pertaining to the accommodation step S3, the resin layer formation step S4, and the fixing step S5 is performed while the opening of the accommodation hole 90 adjoining the second major surface 13 is closed with the adhesive tape 171.
In a subsequent height adjustment step S6, the resin layer 92 is made thin, to thus make the first surface 93 (the surface) of the resin layer 92 level with the surface 18 of the first-major-surface-side conductor layer 14 (see
In a subsequent surface modification step S7 and roughening step S8, the cause for making the surface of the resin layer inactive is eliminated, thereby the surface of the resin layer is modified. Herein, the surface modification step S7 and the roughening step S8 may also referred to as a surface modification step. In a subsequent surface modification step S7, desmear treatment is performed, whereupon the surfaces (the first surface 93 and the second surface 94) of the resin layer 92 and the surfaces 18 and 19 of the conductor layers 14 and 15 are modified. Processing pertaining to the surface modification step S7 is performed after the fixing step S5 and before an insulation layer formation step S9-1; more specifically, immediately after the height adjustment step S6.
In a subsequent roughening step S8, the surface 18 of the conductor layer 14 made on the first major surface 12 and the surface 19 of the conductor layer 15 made on the second major surface 13 are roughened (subjected to CZ treatment). The surfaces of the electrodes 121 and 122 exposed through the second surface 94 of the resin layer 92 are also roughened. After completion of processing pertaining to the roughening step S8, the layered product is subjected to a cleansing step, whereby the surfaces (the first surface 93 and the second surface 94) of the resin layers 92, the surfaces 18 and 19 of the conductor layers 14 and 15, and the surfaces of the electrodes 121 and 122 are cleansed. When necessary, the first major surface 12 and the second major surface 13 may also be subjected to coupling treatment by use of a silane coupling agent (manufactured by Shin-Etsu Chemical Co., Ltd.).
In a subsequent layered wiring area formation step S9, by means of the related-art known technique, the first buildup layer 31 is made on the first major surface 12, and the second buildup layer 32 is made on the second major surface 13. To be more specific, processing pertaining to an insulation layer formation step S9-1 is first implemented. Namely, a thermosetting epoxy resin is caused to adhere (affixed) to the second major surface 13 and the second capacitor major surface 103; specifically, the second surface 94 of the resin layer 92 and the surface 19 of the second-major-surface-side conductor layer 15, thereby generating an innermost resin insulation layer 34 on the second major surface 13 (see
Laser boring is performed by use of a YAG laser or a carbon dioxide gas laser, thereby making via holes 180 and 181 at locations where the via conductors 43 and 47 are to be made (see
In a conductor formation step S9-2, the surfaces of the resin insulation layers 33 and 34, the inner surface of the via hole 181, and the inner surface of the through hole 191 are subjected to electroless copper plating and subsequently to electrolytic copper plating. The through hole conductor 16 is thereby made in the through hole 191; the via conductor 43 is formed in the via hole 181; and the via conductor 47 is formed in the via hole 180. Processing pertaining to a hole plugging step S9-3 is subsequently carried out. Specifically, a cavity of the through hole conductor 16 is filled with an insulation resin material (an epoxy resin), to thus create the filled resin 17 (see
The resin insulation layers 33 and 34 are then covered with a thermosetting epoxy resin, thereby producing the outermost resin insulation layers 35 and 36 having via holes 182 and 183 at positions where the via conductors 43 and 47 are to be Bawled (see
A photosensitive epoxy resin is applied over the resin insulation layers 35 and 36 and is then hardened, thereby generating the solder resists 37 and 38. The substrates are subjected to exposure and development while a predetermined mask is arranged thereon, thereby patterning the openings 40 and 46 in the solder resists 37 and 38.
In a subsequent solder bump formation step S10, a solder paste is printed on the terminal pads 44 formed on the outermost resin insulation layer 36. Next, the wiring board 10 with a printed solder paste is placed in a reflow furnace and heated to a temperature that is higher than the melting point of solder by 10 to 40° C. The solder paste is melted at this point in time, whereupon the semi-spherically bulging solder bumps 45 used for implementing the IC chip 21 are formed. The substrates in this state can be ascertained to be a multi-product wiring board in which product areas which should become the wiring boards 10 are arranged lengthwise and breadthwise along the direction of the plane. Moreover, a plurality of wiring boards 10, which each are products, can be simultaneously acquired by dividing the multi-product wiring board.
Subsequently, the IC chip 21 is mounted in the IC chip implementation area 23 of the second buildup layer 32 of the wiring board 10. At this time, the surface connection terminals 22 of the IC chip 21 and the respective solder bumps 45 are positioned in correspondence with each other. The solder bumps 45 are heated to a temperature of 220° C. to 240° C., to thus become reflowed, whereupon the respective solder bumps 45 and the surface connection terminals 22 are joined together, and the wiring boards 10 and the IC 21 are electrically connected. Thus, the IC chip 21 is mounted in the IC chip implementation area 23 (see
Accordingly, the present embodiment yields the following advantages.
(1) Under the method for manufacturing the wiring board 10 of the present embodiment, the first surface 93 and the second surface 94 of the resin layer 92 are modified in the surface modification step. When the resin insulation layers 33 and 34 are made in the insulation layer formation step S9-1, the resin insulation layers 34 and 36 can be reliably brought into close contact with the surfaces (the first surface 93 and the second surface 94) of the resin layer 92; hence, the occurrence of delamination, and the like, can be prevented. Therefore, the wiring boards 10 exhibiting superior reliability can be produced.
(2) In the embodiment, since the IC chip implementation area 23 is situated within the area located immediately above the ceramic capacitor 101. Therefore, the IC chip 21 implemented on the IC chip implementation area 23 is supported by the ceramic capacitor 101 exhibiting high rigidity and a small thermal expansion coefficient. Therefore, since the second buildup layer 32 becomes less prone to deformation in the IC chip implementation area 23, the IC chip 21 implemented in the IC chip implementation area 23 can be supported more stably. Therefore, the occurrence of cracking or connection failures in the IC chip 21, which would otherwise be attributable to great thermal stress, can be prevented. For this reason, a large-size IC chip measuring 10 mm or more per side that induces an increase in stress (distortion) due to a thermal expansion difference and hence undergoes great thermal stress and that generates a large quantity of heat and undergoes harsh thermal shock during operation or an Low-k (exhibiting a low dielectric constant) IC chip claimed to be brittle can be used as the IC chip 21.
(3) In the embodiment, since the ceramic capacitor 101 is placed at a position immediately below the IC chip 21 implemented in the IC chip implementation area 23. Hence, wiring for connecting the ceramic capacitor 101 to the IC chip 21 becomes shorter, whereby an increase in inductance components of the wiring is prevented. Accordingly, switching noise of the IC chip 21 induced by the ceramic capacitor 101 can reliably be reduced, so that a source voltage can reliably be made stable. Further, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be minimized, high reliability can be accomplished without involvement of failures, such as faulty operation.
The embodiment may also be changed as follows.
The first surface 93 and the second surface 94 may also be modified by grinding the first surface 93 and the second surface 94. For instance, the wiring board 10 is placed on a vacuum suction plate having a plurality of suction holes, and air pressure of the lower surface side of the vacuum suction plate is reduced, to thus fix the wiring board 10 through vacuum suction. Next, a surface of the resin layer 92 (the first surface 93 or the second surface 94) is ground by use of the belt sander equipped with sand paper. Specifically, the surface of the resin layer 92 is ground by means of 600-grit sandpaper, whereby the surface of the resin layer 92 is modified. Simultaneously, the surfaces 18 and 19 of the conductor layers 14 and 15 and the surfaces of the electrodes 121 and 122 are also ground.
In the embodiment, processing pertaining to the surface modification step is carried out immediately after the height adjustment step S6. However, timing at which processing pertaining to the surface modification step is performed may also be changed. For instance, processing pertaining to the surface modification step may also be carried out after the fixing step S5 and before the height adjustment step S6.
In the conductor formation step S9-2 of the embodiment, electroless plating can also be performed again after abrasion of the filled resin 17. As a result of performance of electroless plating, a plated cap layer is made on both the through hole conductor 16 and the end face of the filled resin 17 adjoining the second major surface 13 as well as on both the through hole conductor 16 and the end face of the filled resin 17 adjoining the first major surface 12, and a plated layer is also made over the via conductors 43 and 47. Subsequently, the substrates are subjected to patterning by means of etching in conformance with the related-art known technique (e.g., a subtractive technique), whereby the plated layer makes up portions of the conductor layers 41 and 42.
In the surface modification step of the embodiment, both the first surface 93 of the resin layer 92 situated on the same side where the first major surface 12 of the core substrate 11 is located and the second surface 94 of the resin layer 92 situated on the same side where the second major surface 13 of the core substrate 11 is located are modified. However, only one of the first surface 93 and the second surface 94 may also be modified in the surface modification step. When only any one of the surfaces is modified, it is especially preferable to modify only the second surface 94. The reason for this is that the second surface 94 is a surface remained in contact with an adhesive face of the adhesive tape 171 susceptible to adhesion of extraneous matters and hence may probably become unmodified.
In the resin layer formation step S4 of the embodiment, a gap between the inner surface 91 of the accommodation hole 90 and the capacitor side surfaces 106 of the ceramic capacitor 101 is filled with a portion of the resin layer 92 (the resin sheet). However, the gap between the inner wall surface 91 and the capacitor side surfaces 106 may also be filled by charging liquid resin, which is to make the resin layer 92, by use of a dispenser (manufactured by Asymtek K.K.).
In the embodiment, the height adjustment step S6 may be omitted. Further, processing pertaining to a step for making the resin layer 92 on the first major surface 12 and the first capacitor major surface 102 may also be omitted from the resin layer formation step S4.
In the embodiment, the ceramic capacitor 101 is used as a component held in the accommodation hole 90. However, another component, such as DRAM, SRAM, a chip capacitor, and a register, may also be used.
In the solder bump formation step S10 of the embodiment, only the solder bumps 45 used for implementing the IC chip 21 are formed. In addition, solder bumps used for implementing a motherboard may also be made on the pads 49 formed on the resin insulation layer 35.
Technical ideas ascertained by the embodiment are provided below.
(1) A method for manufacturing a wiring board with a built-in component comprising: a core substrate preparation step for preparing a core substrate having a first major surface, a second major surface, and an accommodation hole opened in both the first major surface and the second major surface; a component preparation step for preparing a component having a first component major surface, a second component major surface, and side surfaces; an accommodation step for holding the component in the accommodation hole after the core substrate preparation step and the component preparation step while the second major surface and the second component major surface are oriented toward the same side; a resin layer formation step for filling a gap between an inner wall surface of the accommodation hole and the side surfaces of the component with a resin layer after the accommodation step; a fixing step for hardening the resin layer after the resin layer formation step, to thus fix the component; and a layered wiring area formation step for forming a layered wiring area, which includes a resin insulation layer and a conductor layer stacked one on top of the other, on the second major surface and the second component major surface after the fixing step, wherein processing pertaining to the accommodation step, the resin layer formation step, and the fixing step is carried out while the second-major-surface-side opening of the accommodation hole is closed with an adhesive tape with a adhesive face; when the adhesive tape is removed after the fixing step, a second-major-surface-side surface of the conductor layer formed on the second major surface, is level with a surface of the resin layer adjoining the innermost resin insulation layer after the layered wiring area formation step; and processing pertaining to the surface modification step for modifying the surface of the resin layer is performed after the fixing step and before the layered wiring area formation step.
(2) In relation to the technical idea (1), the method for manufacturing a wiring board with a built-in component is characterized in that processing pertaining to a solder bump formation step for forming solder bumps used for implementing a semiconductor integrated circuit element on the conductor layer formed on the outermost resin insulation layer is performed after the layered wiring area formation step.
(3) In relation to the technical idea (1) or (2), the method for manufacturing a wiring board with a built-in component is characterized in that the resin layer formed over the first major surface and the first component major surface in the resin layer formation step comprises a resin sheet; and a portion of the resin sheet is caused to enter the first-major-surface-side opening of the accommodation hole in the resin layer formation step, thereby filling a gap between the inner wall surface of the accommodation hole and the side surfaces of the component.
(4) A method for manufacturing a wiring board with a built-in component comprising: a core substrate preparation step for preparing a core substrate having a first major surface, a second major surface, and an accommodation hole opened at least in the first major surface; a component preparation step for preparing a component having a first component major surface, a second component major surface, and side surfaces; an accommodation step for holding the component in the accommodation hole after the core substrate preparation step and the component preparation step while the second major surface and the second component major surface are oriented toward the same side; a resin layer formation step for filling a gap between an inner wall surface of the accommodation hole and the side surfaces of the component with a resin layer after the accommodation step; a fixing step for hardening the resin layer after resin layer formation step, to thus fix the component; and an insulation layer formation step for forming a resin insulation layer on the second major surface and the second component major surface after the fixing step, wherein there is performed processing pertaining to a surface modification step for modifying surfaces of the resin layer after the fixing step and before the insulation layer formation step; processing pertaining to a cleansing step for cleansing the surface of the resin layer and the first-major-surface-side surface of the conductor layer is performed after the surface modification step and before the insulation layer formation step; and the first major surface and the second major surface are subjected to coupling treatment using a silane coupling agent after the cleaning step and before the insulation layer formation step.
(5) A method for manufacturing a wiring board with a built-in component comprising: a core substrate preparation step for preparing a core substrate having a first major surface, a second major surface, and an accommodation hole opened at least in the first major surface; a component preparation step for preparing as a component a capacitor of via array type having a first capacitor major surface, a second capacitor major surface, capacitor side surfaces, a plurality of internal electrode layers stacked by way of dielectric layers, a plurality of intra-capacitor via conductors connected to the plurality of internal electrode layers, and a plurality of surface electrodes connected to at least ends on the second capacitor major surface side of the plurality of intra-capacitor via conductors, the plurality of intra-capacitor via conductors being wholly arranged in an array pattern; an accommodation step for holding the capacitor in the accommodation hole after the core substrate preparation step and the component preparation step while the second major surface and the second capacitor major surface are oriented toward the same side; a resin layer formation step for filling a gap between an inner wall surface of the accommodation hole and the capacitor side surfaces with a resin layer after the accommodation step; a fixing step for hardening the resin layer after resin layer formation step, to thus fix the capacitor; and an insulation layer formation step for fowling a resin insulation layer on the second major surface and the second capacitor major surface after the fixing step, wherein processing pertaining to a surface modification step for modifying surfaces of the resin layer by means of plasma treatment is performed after the fixing step and before the insulation layer formation step.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2008-332596 | Dec 2008 | JP | national |
| P2009-291744 | Dec 2009 | JP | national |
