Method of manufacturing integrated circuit

FIELD OF ART

[0001] The present invention relates to a technique for manufacturing a semiconductor integrated circuit device and more particularly to a technique which is applicable effectively to the lithography in a semiconductor integrated circuit device manufacturing process.

BACKGROUND ART

[0002] In manufacturing a semiconductor integrated circuit device there is used a lithography technique as a method for transferring a fine pattern onto a semiconductor wafer. In the lithography technique there mainly is used a projection exposure system and a pattern of a photomask (hereinafter referred to simply as “mask”) attached to the projection exposure system is transferred onto a semiconductor wafer (simply “wafer” hereinafter) to form a device pattern.

[0003] A mask pattern of an ordinary mask which the present inventors have studied is formed by patterning a light shielding film of chromium (Cr), for example, formed on a transparent quartz substrate. For example, this patterning work for the light shielding film is performed in the following manner. First, an electron beam-sensitive resist is applied onto the light shielding film, then a desired pattern is plotted to the electron beam-sensitive resist by means of an electron beam plotter, followed by development to form a resist pattern of a desired shape. Subsequently, with the resist pattern as an etching mask, the light shielding film is subjected to patterning by dry or wet etching, followed by removal of the resist pattern and subsequent washing, to form a light shielding pattern of a desired shape on the transparent quartz substrate.

[0004] Various mask structures have been proposed along the recent tendency to the improvement of resolution in lithography. For example, in Japanese Published Unexamined Patent Application No. Hei 4(1992)-136854 there is disclosed a technique using a halftone type phase shift mask as means for improving the resolution of a single transparent pattern. According to the technique disclosed therein, a surrounding portion relative to a single transparent pattern is made translucent, that is, a light shielding portion of the mask is made translucent, then in this state the phase of a very small amount of light passing through the translucent portion and having a sensitivity not higher than that of a photoresist and the phase of light passing through the transparent pattern are inverted. Since the light having passed through the translucent film is inverted in phase with respect to the light having passed through the transparent pattern which is a main pattern, there occurs a phase inversion at the boundary portion and the light intensity at the pattern boundary approaches zero. As a result, the ratio between the intensity of the light having passed through the transparent pattern and that at the pattern boundary becomes relatively large and there is obtained a light intensity distribution which is higher in contrast in comparison with the technique not using the translucent film. This halftone type phase shift mask corresponds to a mask in which the light shielding mask of the foregoing ordinary mask has been replaced with a halftone phase shift film, and is fabricated by almost the same process as the ordinary mask manufacturing process referred to above.

[0005] In Japanese Published Unexamined Patent Application No. Hei 5(1993)-289307 there is disclosed a technique of forming a light shielding film by a resist film with a view to attaining simplification and high accuracy of the mask manufacturing process. The method disclosed therein utilizes the property that an ordinary electron beam-sensitive resist or a photosensitive resist shields a vacuum ultraviolet light having a wavelength of approximately 200 nm or less. According to this method it becomes unnecessary to use an etching step for a light shielding film and a resist removing step, thus permitting the reduction of cost, improvement of dimensional accuracy, and the decrease of defects.

[0006] In Japanese Published Unexamined Patent Application No. Sho 55(1980)-22864 there is disclosed a masking technique for lithography using a pattern formed by a laminate of a metallic film and an organic material layer. According to the technique disclosed therein, a photoresist pattern for patterning a chromium layer on a main surface of a glass substrate is irradiated with argon ions and is thereby fixed to the chromium layer pattern, thereby improving the shielding effect against the exposure light.

[0007] In Japanese Published Unexamined Patent Application No. Sho 60(1985)-85525 there is disclosed a technique in which a photoresist is applied onto a mask having a defect to be remedied and then a focused, charged particle beam is radiated to a tiny area of the photoresist which area is to remedy the defect of the mask, to form an opaque carbon film in that area.

[0008] Further, in Japanese Published Unexamined Patent Application No. Sho 54(1979)-83377 there is disclosed a technique in which an opaque emulsion is buried into a local defective portion of a photomask to effect the correction of pattern.

DISCLOSURE OF THE INVENTION

[0009] However, the present inventors have found out that the foregoing masking techniques involve the following problems.

[0010] The change or modification of a mask pattern on mask cannot be done quickly. In the semiconductor integrated circuit device manufacturing process, there sometimes is a case where a circuit pattern is changed or modified for realizing a semiconductor chip construction conforming to a specification requested by a customer, for meeting a customer's request in product development or in manufacture, for rewriting memory information, for the adjustment of characteristics, or for the relief of a defective circuit. For example, in Japanese Published Unexamined Patent Application No. Sho 63(1988)-274156 it is described that wiring should be changed frequently for writing information to a ROM (Read Only Memory) in the manufacture of a semiconductor integrated circuit device which incorporates the ROM. In an ordinary mask, however, the provision of a mask substrate and the deposition and patterning of chromium film are required at every change or modification of the design of the mask, thus resulting in that the fabrication of the mask requires much time. Consequently, much time and labor are required for developing or manufacturing a semiconductor integrated circuit device.

[0011] Moreover, in the foregoing publications disclosing the technique of forming the light shielding pattern of mask by a resist film, there is found no disclosure about problems involved in actually using the mask in the semiconductor integrated circuit device manufacturing process and about problems involved in manufacturing the mask as well as measures to solve the problems. For example, there are the following problems.

[0012] Firstly, it is difficult to detect predetermined patterns used in detecting various information such as mask alignment mark, pattern measurement mark, and product judgment mark. For example, in the mask defect inspecting system and exposure system presently in use there mainly is used a halogen lamp for the alignment of mask. Therefore, in case of attaching a mask to the defect inspecting system or exposure system, if a detection mark on the mask is formed of a resist film pattern, it is difficult to detect the pattern because the resist film is high in light transmittance and a high contrast cannot be obtained. As a result, it becomes difficult to effect alignment between the mask and the defect inspecting system or exposure system, making it impossible to effect the inspection and exposure in a satisfactory manner.

[0013] Secondly, there arise dust particle at the time of loading the mask to the defect inspecting system or exposure system. In the foregoing conventional techniques, at the time of loading the mask to the defect inspecting system or exposure system, the resist film of the mask comes into direct contact with a mask fixing member (e.g., vacuum fixing member) in the defect inspecting system or exposure system, with consequent breakage or chipping of the resist film leading to the generation of dust particles. The dust particles thus generated may adhere to the surface of a lens used in the defect inspecting system or exposure system, or contaminate the interior of a chamber, or adhere to the surface of a semiconductor wafer, which would cause deterioration of the pattern inspection accuracy or transfer accuracy or such a defect as short-circuit or open-circuit defect of pattern, resulting in the semiconductor integrated circuit being deteriorated in its reliability and yield.

[0014] Thirdly, in case of affixing a pellicle onto the mask, if a resist film is present at the portion where the pellicle is to be affixed, it is impossible to affix the pellicle in a satisfactory manner, the pellicle becomes easy to peel off, and dust particles occur at the time of peeling the pellicle.

[0015] It is an object of the present invention to provide a technique capable of shortening the time required for changing or modifying a mask pattern of a mask.

[0016] It is another object of the present invention to provide a technique capable of shortening the period for the development or the manufacture of a semiconductor integrated circuit device.

[0017] It is a further object of the present invention to provide a technique capable of improving an information detecting capability in a mask wherein a resist film is allowed to function as a light shielding film.

[0018] It is a still further object of the present invention to provide a technique capable of suppressing or preventing the generation of dust particles in an exposure processing using a mask wherein a resist film is allowed to function as a light shielding film.

[0019] The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.

[0020] Typical inventions disclosed herein will be outlined below.

[0021] In one aspect of the present invention there is used a step of transferring a predetermined pattern to a resist film formed on a main surfaced of a semiconductor wafer by an exposure processing using a photomask formed on a main surface of a mask substrate, the photomask having a light shielding portion formed of a resist film and a light shielding formed of metal.

[0022] In another aspect of the present invention, the light shielding portion formed of the resist film is removed and instead a new light shielding portion comprised of a resist film is formed to modify or change the light shielding portion, and thereafter the aforesaid exposure processing is performed.

[0023] In a further aspect of the present invention, a light shielding portion is formed of metal along a peripheral portion of the main surface of the mask substrate and a pellicle is contacted and fixed onto the light shielding portion.

[0024] In a still further aspect of the present invention, a light shielding portion is formed of metal along the peripheral portion of the main surface of the mask substrate and an opening is formed in the light shielding portion, thereby forming an information detecting pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]
FIG. 1(a) is a plan view of a photomask according to an embodiment of the present invention and FIG. 1(b) is a sectional view taken on line A-A in FIG. 1(a);

[0026]
FIG. 2 is an explanatory diagram showing schematically a photomask holding means at the time of plotting a predetermined pattern onto the photomask;

[0027] FIGS. 3(a) to 3(c) are sectional views of the photomask of FIG. 1 in a manufacturing process for the photomask;

[0028]
FIG. 4 is a graph showing spectral transmittances of typical electron beam resist films;

[0029] FIGS. 5(a) to 5(c) are sectional views showing a modified example of a manufacturing process for the photomask of FIG. 1;

[0030] FIGS. 6(a) to 6(c) are sectional views showing another modified example of a manufacturing process for the photomask of FIG. 1;

[0031] FIGS. 7(a) and 7(b) illustrate a semiconductor integrated circuit device manufacturing process using the photomask of FIG. 1, in which FIG. 7(a) is a plan view of a principal portion of a semiconductor wafer and FIG. 7(b) is a sectional view taken on line A-A in FIG. 7(a);

[0032] FIGS. 8(a) and 8(b) illustrate a step following FIG. 7, in which FIG. 8(a) is a plan view of the principal portion of the semiconductor wafer and FIG. 8(b) is a sectional view taken on line A-A in FIG. 8(a);

[0033] FIGS. 9(a) and 9(b) illustrate a step following FIG. 8, in which FIG. 9(a) is a plan view of the principal portion of the semiconductor wafer and FIG. 9(b) is a sectional view taken on line A-A in FIG. 9(a);

[0034]
FIG. 10 is an explanatory diagram showing an example of a reducing projection exposure system used in this embodiment;

[0035]
FIG. 11 is a sectional view of a principal portion of the semiconductor wafer in a concrete manufacturing step for the semiconductor integrated circuit device using the photomask of FIG. 1;

[0036]
FIG. 12 is a sectional view of the principal portion of the wafer in a concrete manufacturing step using the photomask which step follows the step of FIG. 11;

[0037]
FIG. 13 is a sectional view of the principal portion of the wafer in a concrete manufacturing step using the photomask which step follows the step of FIG. 12;

[0038]
FIG. 14 is a sectional view of the principal portion of the wafer in a concrete manufacturing step using the photomask which step follows the step of FIG. 13;

[0039]
FIG. 15(a) is a plan view of the photomask of FIG. 1 in a modifying/changing step for a light shielding pattern formed of resist film and FIG. 15(b) is a sectional view taken on line A-A in FIG. 15(a);

[0040] FIGS. 16(a) and 16(b) illustrate a step following FIG. 15, in which FIG. 16(a) is a plan view of the photomask of FIG. 1 in the modifying/changing step for the light shielding pattern formed of resist film and FIG. 16(b) is a sectional view taken on line A-A in FIG. 16(a);

[0041]
FIG. 17(a) is a plan view of a semiconductor wafer, showing patterns transferred through the photomask of FIG. 16 and FIG. 17(b) is a sectional view taken on line A-A in FIG. 16(a);

[0042]
FIG. 18 is a plan view showing an example of a semiconductor chip which is effectively employable during development or manufacture of the photomask of this embodiment;

[0043]
FIG. 19 is a plan view showing another example of a semiconductor chip which is effectively employable during development or manufacture of the photomask of this embodiment;

[0044]
FIG. 20 is a plan view showing a further example of a semiconductor chip which is effectively employable during development or manufacture of the photomask of this embodiment;

[0045]
FIG. 21(a) is a plan view of a photomask according to another embodiment of the present invention and FIG. 21(b) is a sectional view taken on line A-A in FIG. 21(a);

[0046]
FIG. 22(a) is a plan view of the photomask of FIG. 21 in a modifying/changing step for a light shielding pattern formed of resist film and FIG. 22(b) is a sectional view taken on line A-A in FIG. 22(a);

[0047]
FIG. 23(a) is a plan view of the photomask of FIG. 21 in the modifying/changing step for the light shielding pattern formed of resist film;

[0048]
FIG. 24(a) is a plan view of a photomask according to a further embodiment of the present invention and FIG. 24(b) is a sectional view taken on line A-A in FIG. 24(a);

[0049]
FIG. 25(a) is a plan view of the photomask of FIG. 24 in a modifying/changing step for a light shielding pattern formed of resist film and FIG. 25(b) is a sectional view taken on line A-A in FIG. 25(a);

[0050]
FIG. 26(a) is a plan view of the photomask of FIG. 24 in the modifying/changing step for the light shielding pattern formed of resist film and FIG. 26(b) is a sectional view taken on line A-A in FIG. 26(a);

[0051]
FIG. 27(a) is a plan view of a first photomask according to a still further embodiment of the present invention and FIG. 27(b) is a sectional view taken on line A-A in FIG. 27(a);

[0052]
FIG. 28(a) is a plan view of a second photomask used in the embodiment illustrated in FIG. 27 and FIG. 28(b) is a sectional view taken on line A-A in FIG. 28(a);

[0053]
FIG. 29(a) is a plan view of the photomask of FIG. 28 in a modifying/changing step for a light shielding pattern formed of resist film and FIG. 29(b) is a sectional view taken on line A-A in FIG. 29(a);

[0054]
FIG. 30(a) is a plan view of the photomask of FIG. 28 in the modifying/changing step for the light shielding pattern formed of resist film and FIG. 30(b) is a sectional view taken on line A-A in FIG. 30(a);

[0055]
FIG. 31(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 31(b) is a sectional view of the photomask of FIG. 31(a), showing a state of phase inversion of exposure light having passed through various portions of the photomask;

[0056]
FIG. 32(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 32(b) is a sectional view of the photomask of FIG. 32(a), showing a manufacturing step for the photomask;

[0057]
FIG. 33(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 33(b) is a sectional view of the photomask of FIG. 33(a), showing a manufacturing step for the photomask;

[0058] FIGS. 34(a) to 34(d) are sectional views of a photomask according to a still further embodiment of the present invention, showing manufacturing steps for the photomask;

[0059]
FIG. 35(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 35(b) is a sectional view of the photomask of FIG. 35(a), showing a state of phase inversion of exposure light having passed through various portions of the photomask;

[0060] FIGS. 36(a) to 36(e) are sectional views of the photomask of FIG. 35, showing manufacturing steps for the photomask;

[0061]
FIG. 37(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 37(b) is a sectional view of the photomask of FIG. 37(a), showing a state of phase inversion of exposure light having passed through various portions of the photomask;

[0062]
FIG. 38 is a sectional view of a photomask according to a still further embodiment of the present invention;

[0063]
FIG. 39 is a sectional view of a photomask according to a still further embodiment of the present invention;

[0064]
FIG. 40(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 40(b) is a sectional view of the photomask of FIG. 40(a) which is being subjected to pattern modification or change;

[0065]
FIG. 41(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 41(b) is a sectional view of the photomask of FIG. 41(a) which is being subjected to pattern modification or change;

[0066]
FIG. 42(a) is a sectional view of a photomask according to a still further embodiment of the present invention and FIG. 42(b) is an explanatory diagram of the photomask of FIG. 42(a) as loaded onto an exposure system;

[0067]
FIG. 43(a) is a plan view of a connection between a light shielding pattern formed of metal and a light shielding pattern formed of resist film in a photomask according to a still further embodiment of the present invention and FIG. 43(b) is a sectional view taken on line A-A in FIG. 43(a);

[0068]
FIG. 44(a) is an explanatory diagram showing the occurrence of a positional deviation between a light shielding pattern formed of metal and a light shielding pattern formed of resist film in a photomask according to a still further embodiment of the present invention;

[0069]
FIG. 45(a) is a plan view of a connection between a light shielding pattern formed of metal and a light shielding pattern formed of resist film in a photomask according to a still further embodiment of the present invention and FIG. 45(b) is a sectional view taken on line A-A in FIG. 45(a);

[0070]
FIG. 46(a) is an explanatory diagram showing a positional deviation between the light shielding patterns formed of metal and resist film respectively in the photomask of FIG. 45, FIG. 46(b) is a plan view of patterns which have been transferred onto a semiconductor wafer using the photomask of FIG. 46(a), and FIG. 46(c) is a sectional view taken on line A-A in FIG. 46(b);

[0071] FIGS. 47(a) and 47(b) are plan views of a principal portion of the semiconductor wafer, also showing pattern layers which overlie the patterns illustrated in FIG. 46(b), and FIG. 47(c) is a sectional view taken on line A-A in FIGS. 47(a) and 47(b);

[0072]
FIG. 48(a) is a plan view of a connection between a light shielding pattern formed of metal and a light shielding pattern formed of resist film in a photomask according to a still further embodiment of the present invention and FIG. 48(b) is a sectional view taken on line A-A in FIG. 48(a);

[0073]
FIG. 49(a) is a plan view of patterns which have been transferred onto a semiconductor wafer using the photomask of FIG. 48 and FIG. 49(b) is a sectional view taken on line A-A in FIG. 49(a);

[0074]
FIG. 50(a) is a plan view of a connection between a light shielding pattern formed of metal and a light shielding pattern formed of resist film in a photomask according to a still further embodiment of the present invention and FIG. 50(b) is a sectional view of a principal portion, showing a positional deviation between the light shielding patterns formed of metal and resist film respectively in the photomask of FIG. 50(a);

[0075]
FIG. 51 is a plan view of a semiconductor chip according to a still further embodiment of the present invention;

[0076]
FIG. 52(a) is a plan view of a basic cell in the semiconductor chip of FIG. 51, FIG. 52(b) is a sectional view of a principal portion of FIG. 51(a), and FIG. 52(c) is a sectional view of a principal portion of the semiconductor chip of FIG. 52(b) with wiring layers formed thereon;

[0077]
FIG. 53(a) is a symbol diagram of a NAND circuit formed on the semiconductor chip of FIG. 51, FIG. 53(b) is a circuit diagram of FIG. 53(a), and FIG. 53(c) is a plan view of a principal portion, showing a pattern layout in FIG. 53(b);

[0078] FIGS. 54(a) and 54(b) are plan views of principal portions of photomasks according to still further embodiments of the present invention which photomasks are used at the time of transfer of circuit patterns shown in FIG. 53;

[0079]
FIG. 55(a) is a symbol diagram of a NOR circuit formed on the semiconductor chip of FIG. 51, FIG. 55(b) is a circuit diagram of FIG. 55(a), and FIG. 55(c) is a plan view of a principal portion, showing a pattern layout of FIG. 55(b);

[0080] FIGS. 56(a) and 56(b) are plan views of principal portions of photomasks according to still further embodiments of the present invention which photomasks are used at the time of transfer of circuit patterns shown in FIG. 55;

[0081]
FIG. 57(a) is a plan view of a principal portion of a mask ROM, FIG. 57(b) is a circuit diagram of FIG. 57(a), and FIG. 57(c) is a sectional view taken on line A-A in FIG. 57(a);

[0082]
FIG. 58(a) is a plan view of a principal portion of a photomask according to a still further embodiment of the present invention which photomask is used at the time of transferring a pattern onto a semiconductor wafer for the write of data by ion implantation to the mask ROM of FIG. 57, FIG. 58(b) is a plan view of a principal portion of the semiconductor wafer, showing a position of the pattern which is transferred using the photomask of FIG. 58(a), and FIG. 58(c) is a sectional view of the semiconductor wafer, showing in what state data are written in FIG. 58(a);

[0083]
FIG. 59(a) is a plan view of a principal portion of a photomask according to a still further embodiment of the present invention which photomask is used at the time of transferring patterns onto a semiconductor wafer for the write of data by ion implantation to the mask ROM of FIG. 57, FIG. 59(b) is a plan view of a principal portion of the semiconductor wafer, showing positions of the patterns which are transferred using the photomask of FIG. 59(a), and FIG. 59(c) is a sectional view of the semiconductor wafer, showing in what state data are written in FIG. 59(a);

[0084]
FIG. 60(a) is a plan view of a principal portion of a photomask according to a still further embodiment of the present invention which photomask is used at the time of transferring a pattern onto a semiconductor wafer for the write of data by ion implantation to the mask ROM of FIG. 57, FIG. 60(b) is a plan view of a principal portion of the semiconductor wafer, showing a position of the pattern which is transferred using the photomask, and FIG. 60(c) is a sectional view of the semiconductor wafer, showing in what state data are written in FIG. 60(a);

[0085]
FIG. 61(a) is a plan view of a principal portion of another ROM, FIG. 61(b) is a circuit diagram of FIG. 61(a), and FIG. 61(c) is a sectional view taken on line A-A in FIG. 61(a);

[0086]
FIG. 62(a) is a plan view of a principal portion of a photomask according to a still further embodiment of the present invention which photomask is used at the time of transferring contact hole patterns onto a semiconductor wafer for the write of data to the mask ROM of FIG. 61, FIG. 62(b) is a plan view of a principal portion of the semiconductor wafer, showing positions of the patterns which are transferred using the photomask of FIG. 62(a), and FIG. 62(c) is a circuit diagram of FIG. 62(b), and FIG. 62(d) is a sectional view taken on line A-A in FIG. 62(b);

[0087] FIGS. 63(a) and (b) are sectional views of a principal portion of the semiconductor wafer for explaining how to form the contact holes shown in FIG. 62;

[0088]
FIG. 64(a) is a plan view of a principal portion of a photomask according to a still further embodiment of the present invention which photomask is used at the time of transferring contact hole patterns onto the semiconductor wafer for the write of data to the mask ROM of FIG. 61, FIG. 64(b) is a plan view of a principal portion of the semiconductor wafer, showing positions of the patterns which are transferred using the photomask of FIG. 64(a), FIG. 64(c) is a circuit diagram of FIG. 64(b), and FIG. 64(d) is a sectional view taken on line A-A in FIG. 64(b);

[0089]
FIG. 65(a) is a plan view of a principal portion of a photomask according to a still further embodiment of the present invention which photomask is used at the time of transferring contact hole patterns onto a semiconductor wafer for the write of data to the mask ROM of FIG. 61, FIG. 65(b) is a plan view of a principal portion of the semiconductor wafer, showing positions of the patterns which are transferred using the photomask of FIG. 65(a), FIG. 65(c) is a circuit diagram of FIG. 65(b), and FIG. 65(d) is a sectional view taken on line A-A in FIG. 65(b);

[0090]
FIG. 66(a) is a plan view of a principal portion of a mask ROM according to a still further embodiment of the present invention, FIG. 66(b) is a circuit diagram of FIG. 66(a), and FIG. 66(c) is a sectional view taken on line A-A in FIG. 66(a);

[0091]
FIG. 67 is a diagram explaining how to adjust a characteristic of a semiconductor integrated circuit device according to a still further embodiment of the present invention;

[0092]
FIG. 67 is a diagram explaining how to adjust a characteristic of a semiconductor integrated circuit device according to a still further embodiment of the present invention;

[0093]
FIG. 69(a) is an explanatory diagram showing schematically patterns of terminals on a semiconductor wafer which terminals are illustrated in FIG. 67 or FIG. 68 and FIG. 69(b) is a plan view of a principal portion of a photomask which is used for transfer of the patterns shown in FIG. 69(a);

[0094]
FIG. 70(a) is an explanatory diagram showing patterns of terminals on a semiconductor wafer which terminals are illustrated in FIGS. 67 or FIG. 68 and FIG. 70(b) is a plan view of a principal portion of a photomask which is used for transfer of the patterns shown in FIG. 70(a);

[0095]
FIG. 71 illustrates a redundant structure of a semiconductor integrated circuit device according to a still further embodiment of the present invention;

[0096]
FIG. 72(a) is an explanatory diagram showing schematically patterns of terminals on a semiconductor wafer which terminals are illustrated in FIG. 71 and FIG. 72(b) is a plan view of a principal portion of a photomask used for transfer of the patterns shown in FIG. 72(a);

[0097]
FIG. 73(a) is an explanatory diagram of patterns of terminals on a semiconductor wafer which terminals are illustrated in FIG. 71 and FIG. 73(b) is a plan view of a principal portion of a photomask used for transfer of the patterns shown in FIG. 73(a);

[0098] FIGS. 74(a) to 74(c) are explanatory diagrams showing an example of a series of flows in connection with a photomask which is used in a manufacturing process for a semiconductor integrated circuit device according to a still further embodiment of the present invention;

[0099]
FIG. 75 is an explanatory diagram showing a manufacturing process for a semiconductor integrated device circuit according to a still further embodiment of the present invention;

[0100]
FIG. 76 is an explanatory diagram showing a manufacturing process for a semiconductor integrated circuit device according to a still further embodiment of the present invention;

[0101]
FIG. 77 is an explanatory diagram showing a manufacturing process for a semiconductor integrated circuit device according to a still further embodiment of the present invention;

[0102]
FIG. 78(a) is a plan view of a principal portion of a semiconductor wafer in a manufacturing process for a semiconductor integrated circuit device according to a still further embodiment of the present invention, FIGS. 78(b) and 78(c) are plan views of principal portions of the semiconductor wafer, showing description examples of information transferred onto the semiconductor wafer, and FIG. 78(d) is a sectional view taken on line A-A in FIG. 78(b); and

[0103] FIGS. 79(a) and 79(b) are plan views of principal portions of photomasks according to still further embodiments of the present invention which photomasks were used for transfer of the information shown in FIG. 78(b).

BEST MODE FOR CARRYING OUT THE INVENTION

[0104] Meanings of terms as used herein will be described below before describing the present invention in detail.

[0105] 1. Mask (Optical Mask)

[0106] A substrate with a light shielding pattern and a light phase changing pattern formed thereon. A reticle formed with a pattern several times as large as the actual size is also included. By the expression “on the substrate” is meant to include an upper surface of the substrate, as well as an interior or overlying region close to the substrate upper surface, (including an arrangement on another substrate close to the substrate upper surface). By “a first main surface of the mask” is meant a surface where the aforesaid light shielding pattern and light phase changing pattern are formed and by “a second main surface of the mask” is meant a surface located on the side opposite to the first main surface. By “an ordinary mask (binary mask)” is meat a conventional mask with a mask pattern formed on a substrate, the mask pattern comprising a light shielding pattern and a light transmitting pattern.

[0107] 2. A pattern surface of the mask is classified into the following regions: “integrated circuit pattern region” in which integrated circuit patterns to be transferred are arranged, “pellicle cover region” as a region covered with pellicle, “integrated circuit pattern peripheral region” as a pellicle cover region other than the integrated circuit pattern region, “peripheral region” as an outside region not covered with pellicle, “peripheral inside region” as an inside region in the peripheral region where an optical pattern is formed, and “peripheral outside region” as the other peripheral portion used for vacuum chuck for example.

[0108] 3. In connection with the mask shield material, by the term “metal” is meant chromium, chromium oxide, another metal, or a compound thereof, more widely, a simple substance, including a metal element, a compound, and a composite, having a light shielding action.

[0109] 4. By the terms “light shielding region,” “light shielding film,” and “light shielding pattern” is meant one having an optical characteristic which permits less than 40%, usually several % to less than 30%, of exposure light radiated to the region concerned to pass therethrough. On the other hand, by the terms “transparent,” “transparent film,” “light transmitting region,” and “light transmitting pattern,” is meant one having an optical characteristic which permits not less than 60%, usually not less than 90%, of exposure light radiated to the region concerned to pass therethrough. The term “light shielding portion” is used as a generic concept of light shielding region, light shielding film, and light shielding pattern, which are formed of metal or resist film.

[0110] 5. Halftone Mask

[0111] A kind of a phase shift mask, having a halftone shifter wherein the transmittance of a halftone film serving as both shifter and light shielding film is not less than 1% and less than 40% and wherein a phase shift quantity compared with a halftone film-free portion inverts the phase of light.

[0112] 6. Levenson Type Phase Shift Mask (an alternating phase shift mask)

[0113] A kind of a phase shift mask which causes the phases of adjacent openings spaced by a light shielding region to be mutually inverted with the intention of obtaining a clear image by the resulting interfering action.

[0114] 7. Regular Illumination Indicates a non-modified illumination having a relatively uniform light intensity distribution.

[0115] 8. Modified Illumination Indicates an illumination wherein the illuminance of a central portion is lowered, including oblique illumination, zone illumination, multi-pole illumination such as quadrupole illumination and pentapole illumination, as well as an equivalent super-resolution technique using a pupil filter.

[0116] 9. Resolution

[0117] Pattern size can be expressed by standardization using NA (Numerical Aperture) of a projection lens and the wavelength λ of exposure light. In case of using a different wavelength and a different NA, a conversion may be made because the resolution R is represented by the equation R=K1·λ/NA, provided a focal depth D is different because it is also expressed by D=K2·λ/(NA)2.

[0118] 10. In the field of semiconductor, ultraviolet rays are classified as follows. Rays shorter than about 400 nm and not shorter than about 50 nm in wavelength are ultraviolet rays, rays not shorter than 300 nm are near ultraviolet rays, rays not shorter than 200 nm are far ultraviolet rays, and rays shorter than 200 nm are vacuum ultraviolet rays. Main embodiments of the present invention will refer mainly to the vacuum ultraviolet region shorter than 200 nm in wavelength, but it goes without saying that the present invention is also applicable to the far ultraviolet region using a KrF excimer laser and shorter than 250 nm and not shorter than 200 nm if there are made such modifications as will be described in connection with the following embodiments. Further, the principle of the present invention is applicable even to a short wavelength region of ultraviolet rays shorter than 100 nm and not shorter than 50 nm in wavelength.

[0119] 11. Scanning Exposure

[0120] An exposure method wherein a fine slit-like exposure band is moved (scanned) continuously and relatively in a direction perpendicular to the longitudinal direction of the slit (an oblique movement will do) with respect to both semiconductor wafer and photomask (or reticle, by the term “photomask” as referred to herein is meant a wide concept including reticle), thereby transferring the circuit pattern on the photomask onto a desired portion on the semiconductor wafer.

[0121] 12. Step-and-Scan Exposure

[0122] A combined method of the above scanning exposure and stepping exposure to expose the whole of the to-be-exposed portion on the wafer to light, corresponding to a more specific concept of the scanning exposure.

[0123] 13. By the term “semiconductor integrated circuit wafer (semiconductor integrated circuit substrate)” or “wafer (semiconductor substrate)” is meant a silicon single crystal substrate (generally flat and circular), sapphire substrate, glass substrate, another insulating or semi-insulating substrate, a semiconductor substrate, or a composite substrate thereof.

[0124] 14. By the term “device surface” is meant a main surface of a wafer on which are formed device patterns corresponding to plural chip regions by photolithography.

[0125] 15. Masking Layer

[0126] Generally indicates a resist film, but an inorganic mask and a non-photosensitive organic mask are also included.

[0127] 16. Transfer Pattern

[0128] A pattern transferred onto a wafer through the mask, indicating, more concretely, the foregoing photoresist pattern and a pattern on wafer formed actually using the photoresist pattern as mask.

[0129] 17. Resist Pattern

[0130] Indicates a film pattern obtained by patterning a photosensitive organic film by the photolithography technique. In this pattern is included a mere resist film free from any opening in the portion concerned.

[0131] 18. Hole Pattern

[0132] A fine pattern such as a contact hole or through hole pattern having a two-dimensional size equal to or smaller than the wavelength of exposure light on wafer. On the mask, the hole pattern generally assumes a square shape or a rectangular or octagonal shape close to the square shape, but on wafer the hole pattern assumes a circular shape in many cases.

[0133] 19. Line Pattern

[0134] A band-like pattern extending in a predetermined direction.

[0135] 20. Custom Circuit Pattern

[0136] A pattern which constitutes a circuit whose design is changed in accordance with a customer's request such as, for example, a custom I/O circuit or a custom logic circuit.

[0137] 21. Redundant Circuit Pattern

[0138] A pattern which constitutes a circuit for replacing a spare circuit formed on an integrated circuit with a defective pattern.

[0139] In the following embodiments, if necessary for convenience' sake, a division will be made into plural sections or embodiments, but unless otherwise specified, they are not unrelated to one another, but are in such a relation that one is a modification or a detailed or supplemental explanation of part or the whole of the others.

[0140] In the following embodiments, when reference is made to the number of elements (including the number of pieces, numerical values, amount, and range), no limitation is made to such a specific number and both a number larger than and a number smaller than the specific number will do unless otherwise specified and except the case where limitation is made to the specific number basically obviously.

[0141] Moreover, it goes without saying that in the following embodiments their components (including component steps) are not always essential unless otherwise specified and except the case where they are considered essential basically obviously.

[0142] Likewise, in the following embodiments, when reference is made to the shape and positional relation of components, those substantially similar or closely similar to such shape and positional relation are also included unless otherwise specified and except the case where they are considered different basically obviously. This is also the case with the foregoing numerical value and range.

[0143] By the term “semiconductor integrated circuit device” as referred to herein is meant to include not only one fabricated on such a semiconductor or insulator substrate as silicon or sapphire wafer but also one fabricated on another insulating substrate such as TFT (Thin-Film-Transistor) and STN (Super-Twisted-Nematic) liquid crystal.

[0144] In all of the drawings for illustrating the following embodiments, portions having the same functions are identified by like reference numerals and repeated explanations thereof will be omitted.

[0145] In the drawings used in the following embodiments, even in a plan view, a light shielding pattern or a phase shift pattern may be hatched for making the drawing easier to see.

[0146] Further, in the following embodiments, MIS·FET (Metal Insulator Semiconductor Field Effect Transistor), p-channel type MIS-FET, and n-channel type MIS-FET, will be abbreviated as MIS, pMIS, and nMIS, respectively.

[0147] Embodiments of the present invention will be described in detail hereinunder with reference to the accompanying drawings.

[0148] (First Embodiment)

[0149]
FIG. 1(a) is a plan view of a photomask according to an embodiment of the present invention and FIG. 1(b) is a sectional view taken on line A-A in FIG. 1(a) with the photomask attached to a predetermined apparatus.

[0150] The mask of this embodiment, indicated at PM1, is a reticle for focusing and transferring an original of integrated circuit patterns sizing one to ten times the actual size for example onto a wafer through a reducing projection optical system. The illustrated mask is used in the case where a peripheral portion of a semiconductor chip serves as a light shielding portion and where line patterns are formed using a positive type resist film on a wafer.

[0151] A mask substrate 1 of the mask PM1 is formed, for example, by a transparent, synthetic quartz glass plate having a square shape in plan and having a thickness of about 6 mm. Centrally of a main surface of the mask substrate 1 is formed a light transmitting opening region having a rectangular shape in plan, to which is exposed the main surface of the mask substrate 1. This light transmitting opening region forms the foregoing integrated circuit pattern region. On the main surface of the mask substrate 1 in this light transmitting opening region there are arranged light shielding patterns 2a and 3a for transferring the integrated circuit patterns onto a wafer. In the illustrated example, the light shielding patterns 2a and 3a are transferred as line patters on the wafer.

[0152] In this embodiment, the light shielding patterns 2a are formed of metal like ordinary mask, while the light shielding patterns 3a lying in a limited region RE (the region indicated with a broken line) within the integrated circuit pattern region are formed of resist film. Therefore, as will be described later, the light shielding patterns 3a present in the region RE (the region indicated with a broken line) can be removed in a relatively simple manner. Then, new light shielding patterns 3a can be formed easily and in a short time. The resist film which forms the light shielding patterns 3a possesses the property of absorbing exposure light such as, for example, KrF excimer laser beam (wavelength: 248 nm), ArF exciter laser beam (wavelength: 193 nm), or F2 laser beam (wavelength: 157 nm), and has a light shielding function almost equal to that of the light shielding patterns 2a formed of metal. As to the structure of the resist film, including the material thereof, it will be described later. As to the technique of forming light shielding patterns by a resist film, a description thereof is found in Japanese Patent Application No. Hei 11(1999)-185221 (filed Jun. 30, 1999) relating to an invention made by the present inventors.

[0153] On the main surface of the mask substrate 1, an outer periphery of the integrated circuit pattern region is covered with a light shielding pattern 2b. The light shielding pattern 2b is formed in a frame shape in plan so as to span the region between the outer periphery of the integrated circuit pattern region and that of the mask substrate 1. For example, the light shielding pattern 2b is formed of the same metal as that of the light shielding patterns 2a and in the same pattern forming step as that of the patterns 2a. The light shielding patterns 2a and 2b are formed, for example, by chromium or chromium oxide deposited on chromium, provided the material of the light shielding patterns 2a and 2b is not limited thereto and various other materials may be employed. For example, there may be used a refractory metal such as tungsten, molybdenum, tantalum, or titanium, or a nitride such as tungsten nitride, or a refractory metal silicide (compound) such as tungsten silicide (WSix) or molybdenum silicide (MoSix), or a laminate film thereof. In the case of the mask PM1 according to this embodiment, there sometimes is a case where after removal of the light shielding patterns 3a formed of resist film, the mask substrate 1 is washed and is used again. Therefore, it is preferable that the light shielding patterns 2a and 2b be formed using a material superior in peeling resistance and abrasion resistance. Such a refractory metal as tungsten is superior in all of oxidation resistance, abrasion resistance and peeling resistance and is therefore preferable as the material of the light shielding patterns 2a and 2b.

[0154] A generally octagonal framed region formed on the light shielding pattern 2b represents the foregoing pellicle cover region. That is, in the figure being considered there is illustrated a case where a pellicle PE is bonded to the main surface side of the mask substrate 1 of the mask PM1 through a pellicle affixing frame PEf. The pellicle PE is a constituent having a transparent protective film and is spaced a predetermined distance from the main surface or both main surface and back side of the mask substrate 1 for avoiding the adhesion of dust particles to the mask PM1. The predetermined distance is designed taking dust particles deposited on the surface of the protective film and the transferability thereof onto the wafer into account.

[0155] A base portion of the pellicle affixing frame PEf is bonded and fixed in direct contact with the light shielding pattern 2b of the mask PM1, whereby the pellicle affixing frame PEf can be prevented from peeling off. If resist film is formed at the mounted position of the pellicle affixing frame PEf, the resist film will peel off at the time of mounting or removing the pellicle PE and cause the generation of dust particles. The generation of dust particles can be prevented by bonding the pellicle affixing frame PEf in direct contact with the light shielding pattern 2b.

[0156] In the pellicle cover region, the region exclusive of the integrated circuit pattern region represents the integrated circuit pattern peripheral region, in which are formed mark patterns 4a for detecting information on the mask PM1. The mark patterns 4a are for detecting position information on the mask PM1 directly from the same mask at the time of plotting a predetermined pattern on the mask with use of an electron beam plotter. More specifically, at the time of plotting a predetermined integrated circuit pattern in the integrated circuit pattern region of the mask PM1 with use of an electron beam plotter, the mark patterns 4a of the mask PM1 are read at a rate of once per several seconds and the plotting of pattern is carried out while correcting (adjusting) the position to which a pattern plotting electron beam is to be radiated. As a result, it becomes possible to improve the accuracy of the pattern plotting position by the electron beam plotter. The provision of such mark patterns 4a is for the following reason for example.

[0157] In the conventional electron beam plotter, the plotting process for the mask is carried out in vacuum. The mask is held in vacuum in the following manner. As schematically shown in FIG. 2, the mask PM1 or a cassette 201 with the mask PM1 loaded thereon is pushed against three-point pins 200a provided in a mask holder 200, the mask holder 200 being mounted on a moving stage of the electron beam plotter, and is fixed mechanically with a push pin 200b. In the conventional electron beam plotter, position detecting mark patterns 200m are detected plural times during plotting to correct a positional deviation, the mark patterns 200m being attached to the mask holder 200 for the purpose of preventing a deviation of the pattern plotting position caused by a positional drift of the electron beam during plotting. Since the PM1 on the mask holder 200 (stage) is fixed mechanically as mentioned above, a relative positional relation between the mark patterns 200m in the mask holder 200 and the mask PM1 ought to be constant. Actually, however, there may occur a slight positional deviation between the mark patterns 200m and the mask PM1 due to a shock of the stage which is moving at high speed. Consequently, there occurs a positional deviation of the plotted pattern despite the position of the mask PM1 being read from the mark patterns 200m in the electron beam plotting step. To avoid such an inconvenience, position correcting mark patterns 4a are arranged on the mask PM1 itself to detect the position of the mask PM1 directly from the mask itself. By so doing, not only the positional deviation of the plotted pattern but also a deviation in the retention of the mask PM1 can be corrected, so that it is possible to diminish a pattern arrangement error. The mark patterns 4a are each constituted on the basis of whether the pattern position concerned lies in the light transmitting region or in the light shielding region, and information is detected from the state of reflection of a position detecting beam or light radiated there. As position detecting means there may be used one which uses an electron beam from the electron beam plotter, one which uses a laser beam from a laser writer, or any other suitable means. Particularly, the use of position detecting means superior in position accuracy is desirable. The mark patterns 4a may be formed at the time of forming a common light shielding pattern in the mask production or at the time of fabricating mask blanks.

[0158] The outside of the pellicle cover region in FIG. 1 represents a peripheral region, in which are formed mark patterns 4b for detecting information on the mask PM1. The mark patterns 4b are used, for example, as alignment marks or as calibration marks used in mask production. The alignment marks are used for detecting the position of the photomask PM1 when the mask is attached to a predetermined position in an inspection system or an exposure system, thereby making alignment between the mask PM1 and the inspection system or exposure system. The calibration marks are used for detecting a non-registration of pattern and also for detecting the shape of pattern and pattern transfer accuracy.

[0159] The mark patterns 4b are formed of light transmitting patterns. More specifically, the mark patterns 4b are formed by removing portions of the light shielding pattern 2b, allowing portions of the underlying transparent mask substrate 1 to be exposed. Therefore, even in case of using a conventional exposure system which uses a halogen lamp or the like for detecting the position of the mask PM1, it is possible to obtain a sufficient contrast of light having passed through each mark pattern 4b, whereby the recognition ability of the mark patterns 4b can be improved. Consequently, a relative alignment between the mask PM1 and the exposure system can be done easily and that with high accuracy. According to the results of studies made by the present inventors it has become possible to effect an alignment equal to that in the use of a conventional mask. The mark patterns 4a and 4b are not transferred onto the wafer.

[0160] In this embodiment, a resist film for pattern formation is not formed in the peripheral region. If such a resist film is formed in the peripheral region, the resist film may be peeled off or chipped, generating dust particles, due to a mechanical shock induced when the mask PM1 is loaded onto an inspection system or an exposure system. According to this embodiment, however, since no resist film is present in the peripheral region, it is possible to prevent peeling and chipping of the resist film. Actually it was possible to prevent the occurrence of such an inconvenience as the generation of dust particles caused by peeling of the resist film.

[0161] The mask PM1 is installed in the inspection system or exposure system in a directly contacted state of loading portions 5 of the system with the light shielding pattern 2b of the mask. Regions 5A indicated with thick frames in FIG. 1(a) represent regions with which the loading portions 5 come into contact. Thus, even when the mask PM1 is loaded onto the inspection system or exposure system, the generation of dust particles caused by peeling or chipping of resist film is prevented because no resist film is formed on the light shielding pattern 2b. Also prevented is the generation of dust particles caused by peeling or chipping of metal because the metal which constitutes the light shielding pattern 2b is hard. The illustrated loading portions 5 are each provided with a vacuum chuck mechanism.

[0162] Next, an example of a method for manufacturing the mask PM1 shown in FIG. 1 will be described with reference to FIGS. 3 and 4.

[0163] First, as shown in FIG. 3(a), there is provided a mask substrate 1 formed, for example, by a transparent quartz substrate having a thickness of about 6 mm. In this stage, light shielding patterns 2a and 2b have already been formed on a main surface of the mask substrate 1 by the same method as in the conventional mask. That is, the light shielding patterns 2a and 2b are formed by depositing a metal film superior in light shieldability on the main surface of the mask substrate 1 by sputtering for example and subsequently patterning the metal film by photolithography technique and etching technique. As a resist film used as an etching mask in forming the light shielding patterns 2a and 2b there is used a positive type resist film. This is because the area of plotting with an electron beam for example can be reduced and the plotting time can be shortened. After the patterning for the formation of light shielding patterns 2a and 2b, the positive type resist film is removed.

[0164] Subsequently, as shown in FIG. 3(b), a resist film 3 which possesses the property of absorbing exposure light such as KrF excimer laser beam, ArF excimer laser beam, or F2 laser beam is applied to the whole of the main surface of the mask substrate 1 by a spin coating method for example. The resist film 3 is sensitive to electron beam. In this embodiment, a novolak resist film was formed at a thickness of 150 nm, for example.

[0165] Next, after alignment using alignment marks, light shielding patterns 3a were formed of the resist film 3 with use of the same electron beam plotting method as the desired pattern forming method in the conventional mask fabricating process, as shown in FIG. 3(c). In this case there was adopted a measure against electric charging of electron beam. Moreover, since the peripheral portion of the mask PM1 serves as a portion of contact with a projection exposure system, consideration was given so that the resist film 3 was removed, thereby preventing the generation of dust particles caused by a mechanical shock and resultant peeling or chipping of the resist film 3.

[0166] The resist film 3 used contains as a principal component, for example, a copolymer of α-methylstyrene and α-chloroacrylic acid, novolak resin and quinone diazide, novolak resin and polymethylpentene-1-sulfone, or chloromethylated polystyrene. For example, there may be used a chemically amplified resist comprising such a phenolic resin as polyvinyl phenol resin or a novolak resin and an inhibitor and an acid generator both incorporated in the resin. It is necessary that the material of the resist film 3 possess a light shielding characteristic against light emitted from a light source in the projection exposure system and be sensitive to light emitted from a light source in the pattern plotter, e.g., electron beam or light having a wavelength of 230 nm or more. No limitation is made to the materials referred to above, but various other materials may be used. Also as to the film thickness, no limitation is made to 150 nm, but various other film thicknesses may be adopted insofar as the conditions described above are satisfied.

[0167] Spectral transmittances of typical electron beam resist films are shown in FIG. 4. In the case where a polyphenol or novolak resin is formed into a film of about 100 nm in thickness, the transmittance is almost zero at wavelengths of 150 to 230 nm for example. Such a film exhibits a satisfactory masking effect against, for example, ArF excimer laser beam having a wavelength of 193 nm and F2 laser beam having a wavelength of 157 nm. Although description has here been directed to vacuum ultraviolet rays not longer than 200 nm in wavelength, no limitation is made thereto. For such a laser beam as KrF excimer laser beam having a wavelength of 248 nm it is necessary to use another mask material or add a light absorbing or shielding material to the resist film. After the light shielding patterns 3a have been formed of the resist film, it is also effective to apply a hardening process to the resist film which process involves, for example, a heat treatment or a pre-radiation of a powerful ultraviolet light for the purpose of improving the resistance to the exposure light radiated.

[0168] As an example, a negative type resist film was used as the resist film 3. This is because the mask PM1 can be fabricated in Q-TAT (Quick Turn Around Time). More particularly, if the resist film is allowed to remain outside the integrated circuit pattern region, the resist film will cause the generation of dust particles as noted previously, so it is necessary to remove the outside resist film. Therefore, if a positive type resist film is used, the electron beam plotting must also cover most of the outer periphery portion of the integrated circuit pattern region, which is time-consuming. In contrast therewith, if a negative type resist film is used, it suffices for the plotting to cover a region of a relatively small area in the main surface of the mask substrate 1, whereby it is possible to reduce the plotting area and shorten the plotting time.

[0169] Another example of a method for fabricating the mask PM1 of FIG. 1 will now be described with reference to FIGS. 5 and 6. In case of fabricating the above conventional mask, if the metal film for forming light shielding patterns is connected to ground at the time of plotting the resist patterns for forming the light shielding patterns with use of an electron beam plotter or the like, electrons generated during electron beam plotting can be prevented from being charged electrically, so it is not necessary to perform any processing for the prevention of such electric charging. However, in fabricating the mask PM1 according to this embodiment and at the time of forming light shielding patters on the resist film 3 with use of an electron beam plotter, since both mask substrate 1 and resist film 3 are insulators, radiated electrons have their escape cut off and are charged electrically, which may exert a bad influence on the formation of resist patterns (i.e., light shielding patterns 3a). For example, therefore, the mask PM1 is fabricated in the following manner.

[0170] First, as shown in FIG. 5(a), a transparent conductive film 7a is deposited on the main surface of the mask substrate 1. As the transparent conductive film 7a there may be used ITO (indium-tin-oxide) film for example. No processing is needed for the transparent conductive film 7a. Subsequently, light shielding patterns 2a and 2b are formed on the transparent conductive film 7a in the same way as in the fabrication of the conventional mask described above. Next, as shown in FIG. 5(b), the resist film 3 is applied onto the transparent conductive film 7a in the same manner as in the first embodiment. The conductive film 7a is electrically connected to an earth EA. Thereafter, predetermined patterns (light shielding patterns 3a) are plotted on the resist film 3 by means of the electron beam plotter as in the above example. In this case, electrons radiated to the mask substrate 1 can be allowed to escape to the earth EA through the transparent conductive film 7a and therefore it becomes possible to suppress or prevent inconveniences caused by electric charging of electrons such as deterioration in shape and positional deviations of the resist patterns. Thereafter, the mask substrate is subjected to development and washing to fabricate the mask PM1 shown in FIG. 5(c).

[0171] The following modification may be made for the same purpose as above. First, as shown in FIG. 6(a), there is provided a mask substrate 1 already formed with light shielding patterns 2a and 2b, followed by application of the resist film 3 onto the main surface of the mask substrate, as shown in FIG. 6(b). Subsequently, a water-soluble conductive organic film 7b is applied onto the resist film 3. As the water-soluble conductive organic film 7b there was used espacer (a product of Showa Denko K.K.) or aquasave (a product of Mitsubishi Rayon Co., Ltd.) as an example. Thereafter, with the water-soluble conductive organic film 7b and the earth EA connected together electrically, there was conducted an electron beam plotting process for the pattern plotting described above. Then, the water-soluble conductive organic film 7b was also removed during development of the resist film 3. In this way it was possible to prevent the electron beam from being electrically charged and prevent the occurrence of such inconveniences as an abnormal pattern shape and a positional deviation of pattern. The mask PM1 shown in FIG. 6(c) is thus fabricated.

[0172] In the mask PM1 thus fabricated, it is also effective to hold the pattern surface in an inert gas atmosphere such as a nitrogen gas (N2) atmosphere for the purpose of preventing the oxidation of light shielding patterns 3a formed of resist film. The pattern plotting method for the resist film, which method is adopted for forming the light shielding patterns 3a, is not limited to the above electron beam plotting method, but the plotting of patterns may be done using, for example, an ultraviolet ray having a wavelength of 230 nm or more (e.g., i-ray (wavelength: 365 nm)). The main point of the present invention resides in using the resist film directly as mask (light shielding patterns) to provide a practical mask structure. Accordingly, there may be used other wavelengths to be shielded and other resist materials and mask substrate materials.

[0173] Patterns were transferred onto a wafer 8 shown in FIG. 7 by means of a reducing projection exposure system using the mask PM1. FIG. 7(a) is a plan view of a principal portion of the wafer 8 and FIG. 7(b) is a sectional view taken on line A-A in FIG. 7(a). The wafer 8, which serves as a substrate to be projected, is formed of a silicon single crystal for example and with an insulating film 9a deposited on a main surface of the wafer. A conductor film 10a is deposited on the whole upper surface of the insulating film 9a. Further, an ordinary positive type resist film 11a sensitive to ArF is deposited at a thickness of 300 nm or so on the conductor film 10a.

[0174] As an example, in the reducing projection exposure system, there were used ArF excimer laser beam having a wavelength of 193 nm as projection light, a projection lens NA of 0.68, and a light source coherency a of 0.7. Alignment between the reducing projection exposure system and the mask PM1 was performed by detecting mark patterns 4b of the mask PM1. For the alignment there was used helium-neon (He—Ne) laser beam having a wavelength of 633 nm as an example. In this case, since it is possible to take a sufficient contrast of light having passed through the mark patterns 4b, a relative alignment between the mask PM1 and the exposure system could be done easily and with high accuracy.

[0175] Thereafter, the integrated circuit pattern on the mask PM1 was projected onto the main surface of the wafer 8 by the conventional exposure method, followed by conventional heat treatment and development to form resist patterns 11a1 shown in FIG. 8. FIG. 8(a) is a plan view of a principal portion of the wafer 8 and FIG. 8(b) is a sectional view taken on line A-A in FIG. 8(a). RE stands for a region onto which light shielding patterns 3a formed of resist film have been transferred. Thereafter, with the resist patterns 11a1 as an etching mask, the conductor film 10a was subjected to etching to form such conductor film patterns 10a1 as shown in FIG. 9. FIG. 9(a) is a plan view of a principal portion of the wafer 8 and FIG. 9(b) is a sectional view taken on line A-A in FIG. 9(a). As a result, there was obtained about the same pattern transfer characteristic as in the exposure using the conventional mask described above. For example, 0.19 μm line and space could be formed at a focal depth of 0.4 μm.

[0176] An example of the reducing projection exposure system used in this exposure processing is shown in FIG. 10. Exposure light emitted from a light source 12a of a reducing projection exposure system 12 passes through a fly-eye lens 12b, an illumination shape adjusting aperture 12c, condenser lenses 12d1, 12d2, and a mirror 12e, and is radiated to the mask PM1. As the source of exposure light there is used, for example, KrF excimer laser, ArF excimer laser, or F2 laser. The mask PM1 is rested on the reducing projection exposure system 12 with its main surface facing downward (to the wafer 8 side), on which main surface are formed light shielding patterns 2a and 2b. Therefore, the exposure light is radiated to from the back side of the mask PM1, whereby the mask pattern plotted on the mask PM1 is projected through a projection lens 12f onto the wafer 8 which is a sample substrate. As the case may be, the pellicle PE is provided on the main surface of the mask PM1. The mask PM1 is vacuum-chucked to the loading portions 5 of a mask stage 12h which is controlled by a mask position control means 12g, and is then aligned by a position detecting means 12i, whereby the alignment between the center thereof and an optical axis of the projection lens 12f is effected accurately.

[0177] The wafer 8 is vacuum-chucked onto a sample rest 12j. The sample rest 12j is placed on a Z stage 12k, which in turn is placed on an XY stage 12m, the Z stage 12k being movable in the optical axis direction of the projection lens 12f, i.e., in Z axis direction. The Z stage 12k and the XY stage 12m are driven by drive means 12p1 and 12p2, respectively, in accordance with control instructions provided from a main control system 12n and are therefore movable to a desired exposure position. With a laser range finder 12r, that position is monitored accurately as the position of a mirror 12q which is fixed to the Z stage 12k. As the position detecting means 12i there is used an ordinary halogen lamp for example. That is, it is not necessary to use any special light source as the position detecting means 12i (it is not necessary to introduce a new technique or a difficult technique), but there may be used a conventional reducing projection exposure system. Therefore, even with use of such a novel mask PM1 as in this embodiment, there is no fear of increase of the product cost. The main control system 12n is electrically connected to a network system, making it possible to remotely monitor the state of the reducing projection system 12. It is optional whether the exposure method is to be, for example, a step and repeat exposure method or a step and scanning exposure method.

[0178] Next, with reference to FIGS. 11 to 14, the following description is provided about the case where the technical idea of the present invention is applied to the manufacturing process for a semiconductor integrated circuit device having a twin well type CMIS (Complimentary MIS) circuit.

[0179]
FIG. 11 is a sectional view of a principal portion of a wafer 8 in the manufacturing process. The wafer 8 is formed of a thin plate which is generally circular in plan for example. A semiconductor substrate 8s which constitutes the wafer 8 is formed of an n− type Si single crystal for example and above the substrate 8s are formed an n well NWL and a p well PWL. For example, phosphorus (P) or arsenic (As) is introduced into the n well NWL, while boron is introduced into the p well PWL.

[0180] On a main surface of the semiconductor substrate 8s is formed a field insulating film 9b for isolation, for example by a silicon oxide film, in accordance with a LOCOS (Local Oxidization of Silicon) method. The isolating portion may be formed as a trench. More specifically, the isolating portion may be formed by embedding an insulating film in a trench which is dug in the thickness direction of the semiconductor substrate 8s. Both nMIS Qn and pMIS Qp are formed in an active region surrounded by the field insulating film 9b.

[0181] Gate insulating films 9c of nMIS Qn and pMIS Qp are constituted by silicon oxide films for example, which are formed by a thermal oxidation method for example. Gate electrodes 10b of nMIIS Qn and pMIS Qp are formed on the main surface of the wafer 8 by depositing a gate forming conductor film in accordance with CVD method, the conductor film being constituted by a low-resistance polysilicon for example, and then subjecting the conductor film to patterning by the photography technique using the reducing projection exposure system 12 and the photomask PM1 and the conventional etching technique. The gate length is, for example, 0.18 μm or so though this value does not constitute any limitation.

[0182] A semiconductor region 13 which constitutes the source or drain of nMIS Qn is formed self-alignmentwise with respect to the associated gate electrode 10b by introducing, for example, phosphorus or arsenic into the semiconductor substrate 8s in accordance with the ion implantation method for example, with the gate electrode 10b as mask. Likewise, a semiconductor region 14 which constitutes the source or drain of pMIS Qp is formed self-alignmentwise with respect to the associated gate electrode 10b by introducing, for example, boron into the semiconductor substrate 8s in accordance with the ion implantation method, with the gate electrode 10b as mask.

[0183] However, it is not limited for the gate electrodes 10b to be each formed of a simplex film of a low-resistance polysilicon for example. Various changes may be made. For example, there may be adopted a so-called polycide structure wherein a silicide layer such as a layer of tungsten silicide or cobalt silicide is formed on a low-resistance polysilicon film, or there may be adopted a so-called polymetal structure wherein a metal film such as tungsten film is formed on a low-resistance polysilicon film through a barrier conductor film such as titanium nitride or tungsten nitride film.

[0184] First, as shown in FIG. 12, an interlayer insulating film 9d, e.g., silicon oxide film, is deposited on the semiconductor substrate 8s by CVD for example and then a polysilicon film is deposited thereon by CVD. Subsequently, the polysilicon film is subjected to patterning in accordance with the photolithography technique using the reducing projection exposure system 12 and the mask PM1 and the conventional etching technique, and thereafter an impurity is introduced into predetermined regions of the thus-patterned polysilicon film to form wiring lines 10c and a resistor 10d.

[0185] Thereafter, as shown in FIG. 13, an SOG (Spin On Glass) film 9e constituted by a silicon oxide film for example is deposited on the semiconductor substrate 8s by coating for example and then contact holes 15 are formed in the interlayer insulating film 9d and SOG film 9e so that semiconductor regions 13, 14 and the wiring lines 10c are partially exposed in accordance with the photolithography technique using the reducing projection exposure system 12 and mask PM1 and the conventional etching technique. Further, a metal film formed of aluminum (Al) or Al alloy, for example, is deposited on the semiconductor substrate 8s by sputtering for example and is then subjected to patterning by the photolithography technique using the reducing projection exposure system 12 and mask PM1 and the conventional etching technique to form first-layer wiring lines 10e. Subsequently, like the first-layer wiring lines 10e, second and further layer wiring lines are formed to fabricate a semiconductor integrated circuit device. Here, in each of the above photolithography steps, there are formed mask patterns (light shielding patterns and light transmitting patterns) corresponding to the patterns to be formed.

[0186] Next, a description will be given about an application example of the semiconductor integrated circuit device manufacturing method using the mask PM1 according to this embodiment. Reference will here made to a method for partially correcting or changing the pattern of the semiconductor integrated circuit device.

[0187] In the development or manufacturing stage of the semiconductor integrated circuit device there may occur the necessity of partially correcting or changing the integrated circuit patterns. In such a case, with use of a conventional mask, a new mask substrate is provided, a metal film is deposited thereon and is subjected to patterning. Thus, the correcting and changing works are troublesome, labor- and time-consuming works. Besides, if a defect is found in a pattern of the mask thus fabricated, the mask is generally not employable though depending on the degree of the defect, so there is no choice but to discard the mask and it is necessary to provide a new mask substrate and fabricate the mask again from the beginning. For this reason, the works may become wasteful and uneconomical.

[0188] On the other hand, in case of using the mask pM1 according to this embodiment, it is possible to take following measure. First, the light shielding patterns 3a formed of resist film on the mask PM1 in FIG. 1 are removed as in FIG. 15. FIG. 15(a) is a plan view of the mask pM1 after removal of light shielding patterns 3a and FIG. 15(b) is a sectional view taken on line A-A in FIG. 15(a). On the mask PM1 there remain light shielding patterns 2a and 2b formed of metal, but the light shielding patterns 3a in the region RE have been removed, allowing the region RE to serve as a light transmitting region.

[0189] The light shielding patterns 3a formed of resist film were peeled off with an organic solvent, n-methyl-2-pyrrolidone, which may be substituted by a heated amine-based organic solvent or acetone. There also may be used an aqueous tetramethyl ammonium hydroxide (TMAH) solution, ozone sulfuric acid, or a mixed solution of an aquous hydrogen peroxide and a concentrated sulfuric acid. When an aqueous TMAH solution was used at a concentration of about 5%, the resist film (light shielding patterns 3a) could be peeled off without soaking the metal (light shielding patterns 2a and 2b), and thus the use of the aqueous TMAH solution at such a concentration was found preferable.

[0190] As another method for removing the resist film (light shielding patterns 3a) there also may be adopted an oxygen plasma ashing method. This method is effective particularly in the case where the resist film (light shielding patterns 3a) on the mask PM1 has been subjected to a hardening treatment. This is because the resist film (light shielding patterns 3a) having been subjected to a hardening treatment is in a hardened state and may not be removed to a satisfactory extent by the above chemical removing method.

[0191] The light shielding patterns 3a may be subjected to peeling for mechanical removal thereof. More specifically, an adhesive tape is affixed to the surface of the mask PM1 on which surface are formed the light shielding patterns 3a, and is then removed to peel off the light shielding patterns 3a. In this case, there scarcely is used any organic solvent and it is not necessary to create a vacuum state, so the light shielding patterns 3a can be peeled off relatively easily and in a short time.

[0192] The step of removing the resist film (light shielding patterns 3a) is followed by washing to remove dust particles present on the surface of the mask PM1. For the washing there was used, as an example, a combination of ozone sulfuric acid washing and brush washing, but any other method may be adopted insofar as the method adopted has a high dust particle removing ability and does not affect the metal (light shielding patterns 2a and 2b).

[0193] Thereafter, as shown in FIG. 16, a group of desired light shielding patterns 3a different in shape from the group of light shielding patterns 3a shown in the region RE in FIG. 1 is formed in the region RE. How to form the light shielding patterns 3a is the same as that described in the manufacturing method for the mask PM1 and therefore an explanation thereof will here be omitted. FIG. 17 shows these patterns of mask PM1 having been transferred onto the wafer with use of the foregoing reducing projection exposure system 12 (see FIG. 10). FIG. 17(a) is a plan view of a principal portion of the wafer 8 and FIG. 17(b) is a sectional view taken on line A-A in FIG. 17(a). In this way a group of conductor film patterns 10a1 different in shape from that shown in FIG. 9 can be formed in the region RE.

[0194] Thus, in the case of the mask PM1 being considered, the light shielding patterns 3a as part of the mask PM1 are formed of resist film, so in the event there occurs a correction or change with respect to patterns present in part (region RE) of the mask PM1, all that is required is removing the light shielding patterns 3a and re-forming like patterns in the same manner as in the lithography commonly adopted in the semiconductor integrated circuit device manufacturing process. Therefore, the correction or change can be done in a simple manner and that in an extremely short time. That is, it becomes possible to greatly shorten the period of manufacturing the mask PM1. Consequently, by using the mask PM1 in the development or manufacture of a semiconductor integrated circuit device it is made possible to greatly shorten the time required for the development or manufacture of a semiconductor integrated circuit device.

[0195] In correcting or changing patterns of the mask PM1 it is not necessary to newly provide or re-fabricate a mask substrate 1. Besides, even in the event the light shielding patterns 3a on the mask fabricated are found to involve a defect, it suffices to remove the light shielding patterns 3a and again perform patterning for the mask. Accordingly, not only the number of manufacturing steps for the mask PM1 can be reduced to a great extent but also the quantity of materials required in the manufacture of the mask PM1 can be greatly decreased and hence it becomes possible to greatly reduce the manufacturing cost of the mask PM1. It follows that the use of the mask PM1 in the development or manufacture of a semiconductor integrated circuit device permits a great reduction in cost of the circuit device.

[0196] FIGS. 18 to 20 show examples of semiconductor chips 8c1 to 8c3 of semiconductor integrated circuit devices to which the technical idea of the present invention is applicable effectively. The semiconductor chips are small semiconductor pieces square in plan cut out from the wafer 8. On the wafer, the hatched area indicates an area where light shielding patters are formed of resist film.

[0197] In the semiconductor chip 8c1 shown in FIG. 18 there are arranged such circuit regions as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), DSP (Digital Signal Processor), a microprocessor, MPEG (Moving Picture Experts Group), and Logic. Since Logic is apt to be changed on customer's request, light shielding patterns on the mask for forming patterns in the Logic circuit region are formed of resist film. More specifically, mask patterns for forming patterns in the Logic circuit region are formed of resist film (light shielding patterns 3a). Light shielding patterns on the mask PM1 for forming patterns in the other circuit region are formed of metal.

[0198] In the semiconductor chip 8c2 shown in FIG. 19 there are arranged such circuit regions as PCI control circuit, I/F control circuit, MCU, program ROM, data RAM (e.g., SRAM), and custom logic circuit. Light shielding patterns on the mask for forming I/F control circuit, program ROM, and custom logic circuit are formed of resist film. To be more specific, three regions RE are provided on the mask PM1 and mask patterns for forming patterns of I/F control circuit, program ROM, and custom logic circuit are formed of resist film (light shielding patterns 3a) in the three regions RE, respectively. Light shielding patterns on the mask PM1 for forming patterns in the other circuit region are formed of metal. This is because in the I/F control circuit there occur different pattern shapes in case of different interface standards like, for example, IEEE (I triple E) 1394, USB (Universal Serial Bus), SCSI (Small Computer System Interface), AGP (Accelerated Graphics Port), Ether, and Fiber-channel. Moreover, in the program ROM there arises the necessity of rewriting program. Here it is possible to give an example in which light shielding patterns on the mask are formed of resist film for divisions (memory cells) of ROM. Further, in the custom logic circuit, there arises the case where a circuit pattern is changed in compliance with a customer's request as typified, for example, by a gate array or a standard cell.

[0199] In the semiconductor chip 8c3 shown in FIG. 20 there are arranged CPU (Central Processing Unit), memory, application logic circuit, custom I/O (Input/Output) circuit, analog circuit, and custom logic circuit. Light shielding patterns on the mask for forming patterns of the custom I/O circuit and custom logic circuit are formed of resist film. More specifically, there are provided two regions RE of the mask PM1 and mask patterns for forming patterns of the custom I/O circuit and custom logic circuit are formed of resist film (light shielding patterns 3a) in the two regions RE, respectively. Light shielding patterns on the mask PM1 for forming patterns in the other circuit region are formed of metal. This is because for the custom I/O circuit there is applied the same reason as with I/F control circuit set forth above.

[0200] (Second Embodiment)

[0201] In this second embodiment a modified example of mask will be described. Other points are the same as in the first embodiment.

[0202] In a mask PM2 shown in FIG. 21, a peripheral contour of a semiconductor chip serves as a light shielding portion, and line patterns are formed on wafer with use of a positive type resist film. FIG. 21(a) is a plan view of the mask PM2 and FIG. 21(b) is a sectional view taken on line A-A in FIG. 21(a).

[0203] Light shielding patterns 2a and 3a in an integrated circuit pattern region on the mask PM2 are the same as in the first embodiment. Patterns which are transferred onto the wafer with use of the mask PM2 are also the same as those shown in FIGS. 8 and 9. In this second embodiment, a band-like light shielding pattern 2c is formed of metal along an outer periphery of the integrated circuit pattern region and in a surrounding relation to the same region. The greater part of the portion located outside the light shielding pattern 2c serves as a light transmitting region, with the light shielding film removed. Mark patterns 4a and 4b located in the peripheral region of the mask PM2 are formed of metallic light shielding patterns. Consequently, it is possible to obtain a sufficient contrast of detection light and hence possible to improve the sensitivity and accuracy in mark detection.

[0204] The light shielding patterns 2a, 2c and mark patterns 4a, 4b are formed in the same patterning step, using the same metal material. In forming the light shielding patterns 2a, 2c and mark patterns 4a, 4b on this mask substrate 1 there is used a negative type resist film as an etching mask. This is because the mark PM2 can be fabricated in Q-TAT. More particularly, if resist film is allowed to remain outside the integrated circuit pattern region, it will cause the generation of dust particles as noted earlier, so it is necessary to remove the outside resist film. In this connection, if a positive type resist film is used, the greater part of the interior and outer periphery of the integrated circuit pattern region must be subjected to electron beam plotting, which takes time. However, if a negative type resist film is used, it suffices to effect plotting for the regions of light shielding patterns 2a, 2c and mark patterns 4a, 4b which are relatively small in area within the main surface of the mask substrate 1, whereby the plotting area and plotting time can be made small and short, respectively.

[0205] A base portion of a pellicle affixing frame PEf of pellicle PE is bonded in direct contact with the mask substrate 1. As in the first embodiment, therefore, it is possible to prevent peel-off of the pellicle affixing frame PEf. Loading portions 5 of the exposure system also assumes a state of direct contact with the mask substrate 1. Consequently, the generation of dust particles caused by peel-off of resist can be suppressed or prevented as in the first embodiment.

[0206] How to change the light shielding patterns 3 of mask PM2 is also the same as in the first embodiment. A brief description on this point will be given below with reference to FIGS. 22 and 23. In each of FIGS. 22 and 23, (a) is a plan view of the mask PM2 and (b) is a sectional view taken on line A-A in (a).

[0207] First, the light shielding patterns 3a in region RE of the mask PM2 are removed in the same way as in the first embodiment, as shown in FIG. 22. Light shielding patterns 2a and 2c present in elements transfer regions D1 to D3 are allowed to remain because they are formed of metal. Subsequently, as shown in FIG. 23, light shielding patterns 3a different in shape from those in FIG. 21 are formed of resist film in the region RE of the mask PM2 in the same manner as in the first embodiment. As the resist film which forms the light shielding patterns 3a in the above manner there was used a negative type resist.

[0208] Also in this second embodiment constructed as above there are obtained the same effects as in the first embodiment.

[0209] (Third Embodiment)

[0210] In this third embodiment a description will be given below about a modified example of mask. Other points are the same as in the first embodiment.

[0211] A mask PM3 according to this third embodiment is used in forming line patterns on wafer with use of a negative type resist film. FIG. 24(a) is a plan view of the mask PM3 and FIG. 24(b) is a sectional view taken on line A-A in FIG. 24(a).

[0212] A main surface of a mask substrate 1 of the mask PM3 is covered substantially throughout the whole thereof with a light shielding film 2d formed of metal. The material of the light shielding film 2d is the same as that of the light shielding patterns 2a to 2c described previously. In elements forming regions D1 to D3 located within an integrated circuit pattern region of the mask PM3, part of the light shielding film 2d is removed to form light transmitting patterns 16a. In a region RE located within the integrated circuit pattern region, the light shielding film 2d is partially removed in a square shape in plan to form a light transmitting opening region, which instead is covered with a light shielding film 3b formed of resist film. The light shielding film 3b is partially removed to form light transmitting patterns 16b. An outer periphery of the light shielding film 3b formed of resist film is partially stacked on part of the light shielding film 2d. The resist material of the light shielding film 3b is the same as that of the light shielding patterns 3a described in the first embodiment. In the illustrated example, the light transmitting patterns 16a and 16b are transferred as line patterns on wafer. That is, patterns of the light transmitting patterns 16a and 16 are transferred onto the wafer. Further, mark patterns 4a and 4b of the mask PM3 are formed as light transmitting patterns as in the first embodiment. That is, they are formed by removing part of the light shielding film 2d. Therefore, it is possible to obtain a sufficient contrast of detection light and hence possible to improve the sensitivity and accuracy in mark detection.

[0213] In processing the light shielding film 2d on the mask substrate 1 (i.e., in forming the light transmitting patterns 16a, the light transmitting opening region in region RE and mark patterns 4a, 4b) there is used a positive type resist film. This is because the mask PM3 can be formed in Q-TAT. In more particularly terms, if a negative type resist film is used in the aforesaid processing, the greater part of both inside and outside of the integrated circuit pattern region must be subjected to electron beam plotting, which requires much time.

[0214] A base portion of a pellicle affixing frame PEf of pellicle PE is bonded in direct contact with the light shielding film 2d which is formed of metal on the mask substrate 1. Therefore, as in the first and second embodiments, it is possible to prevent peel-off of the pellicle affixing frame PEf. Loading portions 5 in the exposure system also assumes a state of direct contact with the light shielding film 2d formed of metal. Consequently, the generation of dust particles caused by peeling of resist can be suppressed or prevented as in the first and second embodiments.

[0215] Also as to the method of changing the light transmitting patterns 16b of the mask PM3, it is the same as in the first and second embodiments. This point will be described below briefly with reference to FIGS. 25 and 26. In both figures, (a) is a plan view of the mask PM3 and (b) is a sectional view taken on line A-A in (a).

[0216] First, the light shielding film 3b formed of resist film in region RE of the mask PM3, which is shown in FIG. 24, is removed in the same way as in the first and second embodiments, as shown in FIG. 25, allowing the light transmitting opening region 16c in region RE to be exposed. At this time, the light shielding film 2d formed of metal is allowed to remain, so the light transmitting patterns 16a in the elements transfer regions D1 to D3 are maintained in their state shown in FIG. 24. A light transmitting opening region 16c is opened in a square shape in plan for example, from which a main surface of the mask substrate 1 is exposed.

[0217] Subsequently, a resist film for forming light shielding patterns is applied onto a main surface (the surface formed with the light shielding film 2d) of the mask PM3. As the resist film there was used a negative type resist film. This is because the mask Q-TAT can be fabricated in Q-TAT. More particularly, if a positive type resist film is used, it is required to perform electron beam plotting both inside and outside the integrated circuit pattern, and thus it takes time. However, with a negative type resist film, the plotting area can be reduced and the plotting time can be shortened. Then, the light shielding region-forming portion of the resist film is irradiated with electron beam for example to plot patterns, followed by development, whereby the light shielding film 3b and light transmitting patterns 16b, which result from partial removal of the film 3a, are formed in the region RE as shown in FIG. 26.

[0218] Also in this third embodiment constructed as above there are obtained the same effects as in the first and second embodiments.

[0219] (Fourth Embodiment)

[0220] In this fourth embodiment a description will be given below about the application of the present invention to a so-called superimposed exposure technique wherein one pattern or a group of patterns on a wafer are formed by exposure through plural stacked masks. Other points are the same as in the first to third embodiments.

[0221]
FIG. 27 shows an example of a first mask PM41 used in this fourth embodiment. In an integrated circuit pattern region of the mask PM41 is formed a light transmitting opening region 16d which is inverted L-shaped in plan for example. In the light transmitting opening region 16d are formed light shielding patterns 2a of metal for transferring an integrated circuit pattern onto a wafer. The illustrated mask PM41 is used to transfer line patterns onto the wafer. The surrounding portion of the light transmitting opening region 16d is mostly covered with a light shielding film 2e of metal which extends up to an outer periphery of the mask substrate 1. Region RE is also covered with the light shielding film 2e. As to mark patterns 4b and pellicle used in the first mask PM41, they are the same as in the third embodiment.

[0222] The mask PM41 is used to transfer patterns of a circuit (see FIGS. 18 to 20) constituted by a group of constant-shape patterns which are basically not corrected or changed in a semiconductor integrated circuit device. The light shielding patterns 2a and the light shielding film 2e are made of the same material, but as their material there may be used a material other than chromium and chromium oxide. This is because the mask PM41 is used in the same manner as an ordinary type of mask. More particularly, since the change of pattern is not made, it suffices for the light shielding patterns 2a and light shielding film 2e to have such a resistance as is required of an ordinary type of mask. Of course, the light shielding portions (light shielding patterns and light shielding film) of the mask PM41 may be formed of resist film.

[0223]
FIG. 28 shows an example of a second mask PM42 used in this fourth embodiment. In region RE in an integrated circuit pattern region of the mask PM42 is formed a light transmitting opening region 16e which is square in plan for example. In the light transmitting opening region 16e are formed light shielding patterns 3a by resist film to transfer an integrated circuit pattern onto a wafer. The mask PM42 is used to transfer line patterns onto the wafer. The surrounding portion of the light transmitting opening region 16e is mostly covered with a light shielding film 2f of metal which extends to an outer periphery of a mask substrate 1. The light shielding film 2f is formed of the same material as that of the light shielding patterns 2a described in the first embodiment, etc. Mark patterns 4b and pellicle used in the second mask PM42 are also the same as in the third embodiment.

[0224] The second mask PM42 is used to transfer patterns of a circuit (see FIGS. 18 to 20) constituted by a group of patterns which are subjected to correction or change in a semiconductor integrated circuit device. How to correct or change the light shielding patterns 3a in the second mask PM2 is also the same as in the first to third embodiments. This point will now be described briefly with reference to FIGS. 29 and 30, in which (a) is a plan view of the mask PM42 and (b) is a sectional view taken on line A-A in (a).

[0225] First, the light shielding patterns 3a formed of resist film in the region RE of the mask PM2 shown in FIG. 28 are removed in the same manner as in the first to third embodiments, as shown in FIG. 29. At this time the light shielding film 2f of metal is allowed to remain. Subsequently, a resist film for forming light shielding patterns is applied onto a main surface (the surface formed with the light shielding film 2f) of the mask PM42. As the resist film there was used a negative type resist film. This is because the mask PM42 can be formed in Q-TAT. More particularly, if the resist film is allowed to remain outside the integrated circuit pattern region, it causes the generation of dust particles as noted earlier, so it is necessary to remove the outside resist film. Therefore, if a positive type resist film is here used, the greater part of an outer periphery of the integrated circuit pattern region must also be subjected to electron beam plotting, which takes time. In contrast therewith, if a negative type resist film is used, it suffices to plot only the region of light shielding patterns 3a which are relative small in area within the main surface of the mask substrate 1, whereby the plotting area can be reduced and the plotting time can be shortened. Subsequently, electron beam for example is radiated to the light shielding region-forming portion of the resist film to plot patterns, followed by development, to form light shielding patterns 3a in region RE which patterns are different in shape from the light shielding patterns 3a shown in FIG. 28. Of course, even if all the light shielding portions (light shielding patterns and light shielding film) of the masks PM41 and PM42 are formed of such metal as chromium, all that is required is only a change of the mask PM42, so it becomes possible to attain Q-TAT in mask production.

[0226] An example of the method for transferring patterns onto wafer with use of such first and second masks PM41 and PM42 will be described below with reference to FIG. 7 and other figures.

[0227] First, as shown in FIG. 7, a positive type resist film 11a is formed by coating onto a conductor film 10a formed on wafer 8 and then the mask patterns of the first mask PM41 shown in FIG. 27 are transferred onto the resist film 11a by means of the reducing projection exposure system 12 shown in FIG. 10. At this time, exposure light passes through the light transmitting opening region 16d of the first mask PM1, so that the region corresponding to the light transmitting opening region 16d in the resist film 11a is exposed to the light. However, since the region RE of the first mask PM41 is covered with the light shielding film 2e, the region corresponding to the region RE in the resist film 11a is not exposed to the light.

[0228] Subsequently, without removing the resist film 11a, the mask patterns of the second mask PM42 shown in FIG. 28 are transferred onto the resist film 11a by means of the reducing projection exposure system 12 shown in FIG. 10. In this case, reverse to the case of the first mask PM41, only the region corresponding to the region RE of the second mask PM42 is exposed to light in the resist film 11a.

[0229] Thereafter, the resist film 11a is subjected to development, whereby resist patterns which reflect the first and second masks PM41, PM42 are formed on the conductor film 10a. Then, with the resist patterns as an etching mask, etching is performed for the conductor film 10a to form conductor film patterns. If there arises the necessity of correction or change for the region RE of the second mask PM42 during development or manufacture of the semiconductor integrated circuit device, the light shielding patterns 3a on the second mask PM42 may be reformed in the manner described above.

[0230] Thus, according to this fourth embodiment there can be obtained the following effects in addition to the effects obtained in the first to third embodiments.

[0231] In the case where both light shielding patterns 2a which seldom require correction or change and light shielding patterns 3a which require correction or change are formed in one and same mask, then at the time of pattern correction or change, peeling and washing of the resist film (light shielding patterns 3a) are applied also to the light shielding patterns 2a which are fine patterns free of correction or change, so that the light shielding patterns 2a may be deteriorated or peel off. On the other hand, in this fourth embodiment, a division is made into the first mask PM41 for the transfer of patterns which are seldom subjected to correction or change and the second mask PM41 for the transfer of patterns which are subjected to correction or change, so at the time of pattern correction or change, peeling and washing of the resist film are not applied to the fine light shielding patterns 2a that are seldom subjected to correction or change. Besides, since the fine light shielding patterns 2a are not present in the second mask PM2, peeling or washing of the light shielding patterns 3a can be carried out without the need of paying attention to deterioration or peel-off of the light shielding patterns 2a. Consequently, it is possible to improve the mask life and reliability.

[0232] (Fifth Embodiment)

[0233] This fifth embodiment describes a modified example of a mask, in which the present invention is applied to a translucent phase shift mask (the foregoing halftone mask).

[0234]
FIG. 31 shows a mask PM5 of this fifth embodiment. Halftone patterns 3c for the transfer of an integrated circuit pattern are formed in a light transmitting region which is a part of an integrated circuit pattern region of the mask PM5. The halftone patterns 3c are formed of resist film 3 which forms the light shielding patterns 3a described in the first embodiment, etc., but are translucent to exposure light and the thickness thereof is adjusted to a thickness for inversion of the phase of exposure light. In the mask substrate 1, the halftone patterns 3c are formed flush with light shielding patterns 2a and 2b.

[0235]
FIG. 31(b) shows a state of phase inversion of exposure light radiated from the back side of the mask PM5 of this fifth embodiment. The exposure light having passed through the halftone patterns 3c is 180° inverted in phase relative to the exposure light having passed through a transparent portion (the light transmitting region). That is, both exposure lights are opposite in phase. The transmittance of the halftone patterns 3c is about 2 to 10% in terms of light intensity relative to the exposure light before passing through the halftone patterns 3c. Therefore, the halftone patterns 3c substantially act as light shielding portions, but are effective in making a boundary portion of transferred patterns clear. Processing and changing methods for the halftone patterns 3c are the same as those for the light shielding patterns 3a in the first to fourth embodiments.

[0236] In case of using an ArF excimer laser as an exposure light source, the absorption in the resist film serving as a mask is large, so for realizing both the foregoing transmittance of about 2 to 10% and phase inversion simultaneously, it is necessary to make an appropriate adjustment for the resist film for the formation of halftone patterns 3c. On the other hand, the use of an F2 laser beam with a wavelength of 157 nm as an exposure light source is advantageous to the simultaneous realization of both the foregoing transmittance of about 2 to 10% and phase inversion.

[0237] Also in this fifth embodiment there are obtained the same effects as in the first to fourth embodiments.

[0238] (Sixth Embodiment)

[0239] This sixth embodiment describes a modification of the mask of the fifth embodiment.

[0240] In the previous fifth embodiment the phase difference set by adjusting the thickness of the halftone patterns, so it is necessary that the thickness be adjusted to within a predetermined range. Consequently, there sometimes occurs a case where it is difficult to set the intensity of light passing through the halftone patterns of the resist film.

[0241] In view of this point, in this sixth embodiment, the phase difference of light is set not by adjusting only the film thickness of the halftone patterns of the resist film but by adjusting both the film thickness and the depth of each trench formed in the mask substrate (i.e., the thickness of the mask substrate in the trenched portion). As a result, there can be obtained the following effects in addition to the effects obtained in the fifth embodiment. Firstly, it is possible to facilitate the setting of the intensity of light passing through the halftone patterns. Secondly, it is possible to widen the selection range of the material which forms the halftone patterns.

[0242]
FIG. 32(a) shows a concrete example of the mask PM6 of this sixth embodiment. In the mask PM6, halftone patterns 3d of resist film are made of the same material as that of the halftone patterns 3c used in the previous fifth embodiment, but their translucent film is thinner than the halftone patterns 3c, and a phase inversion of transmitted light was realized by both the thickness of the halftone patterns 3d and that of the mask substrate 1 in the portion of each trench 18 formed in the mask substrate.

[0243] As an example, the halftone patterns 3d were formed using a novolak resin having a thickness of about 50 nm. As a result, the transmittance of the halftone patterns 3d became 5%. However, the transmittance is not limited to 50%, but various changes may be made. For example, in the range of 2% to 20% it is possible to make selection according to a purpose. In the example being considered, the phase inversion was about 90°. More specifically, trenches 18 each having a depth of about 90 nm was formed in the mask substrate 1 so as to create a phase inversion of about 180° in total for the exposure light having passed through the mask PM6. The thickness of the halftone patterns 3d is not limited to the one referred to above, but various changes may be made if only adjustment is made so as to cause the inversion of phase according to the refractive index of material, the wavelength of exposure light, etc.

[0244] The mask PM6 thus constructed can be formed, for example, in the following manner. First, as in the fifth embodiment, light shielding patterns 2a, 2b and halftone patterns 3d are formed on the mask substrate 1, as shown in FIG. 32(b), then with the patterns 2a, 2b and 3d as an etching mask, the mask substrate 1 exposed therefrom is etched off selectively by only the foregoing depth, whereby the grooves 18 shown in FIG. 32(a) are formed self-alignmentwise with respect to the halftone patterns 3d. In this sixth embodiment the mask PM6 having halftone patterns 3d with a transmittance of 5% could be fabricated in this way. In the example shown in FIG. 32(a), for simplification of the mask fabricating process, the mask substrate 1 in the region of mark patterns 4b is also etched off and is dug thereby at the time of formation of the trenches 18, but the mask substrate portion in this region may be left as it is without being etched off. In the mask PM6, correction or change, if necessary, of the halftone patterns 3d is made before forming the trenches 18.

[0245] Also in this sixth embodiment there are obtained the same effects as in the first to fifth embodiments.

[0246] (Seventh Embodiment)

[0247] This seventh embodiment describes a modification of the masks of the fifth and sixth embodiments.

[0248] In this seventh embodiment, for solving the problem referred to in the previous sixth embodiment, the phase of exposure light is adjusted not by only halftone patterns but by the provision of another film which overlaps the halftone patterns planarly. By so doing, as in the sixth embodiment, it is possible to set easily the intensity of light passing through the halftone patterns. It is also possible to widen the selection range of the material which forms the halftone patterns.

[0249]
FIG. 33(a) shows a concrete example of a mask PM7 according to this seventh embodiment. In the mask PM7, a transparent phase adjusting film 19 formed of a silicon oxide film for example is provided between the same halftone patterns 3d of resist film as in the sixth embodiment and the mask substrate 1, and the foregoing phase inversion is realized by adjusting the thickness of each halftone pattern 3d and phase adjusting film 19.

[0250] The mask PM7 thus constructed is formed, for example, in the following manner. First, as shown in FIG. 33(b), a phase adjusting film 19 constituted by a silicon oxide film for example is formed on the main surface of the substrate 1 by sputtering, CVD (Chemical Vapor Deposition), or coating. Subsequently, light shielding patterns 2a, 2b and halftone patterns 3d are formed thereon in the same way as in the fifth and sixth embodiments. Thereafter, as noted above, with the halftone patterns 3d alone, the phase inversion was about 90°, so with the halftone patterns 3d and light shielding patterns 2a, 2b as an etching mask, the underlying phase adjusting film 19 was dug about 90 nm so as to afford a phase inversion of about 180° in total. In this case, the mask substrate 1 may be used as an etching stopper. The mask PM7 shown in FIG. 33(a) is fabricated in this way. Also in this seventh embodiment there could be fabricated a halftone type mask PM7 having a transmittance of 5% for example. As in the sixth embodiment the thickness of the halftone patterns 3d is not limited thereto. Also in this seventh embodiment, for simplifying the mask fabricating process, the phase adjusting film 19 in the region of mark patterns 4b is also etched off during patterning thereof, but the phase adjusting film portion in this region may be left as it is without being etched off. In this case, it is preferable that correction or change, if necessary, of the halftone patterns 3d of the mask PM7 be made before etching the phase adjusting film 19.

[0251] Also in this seventh embodiment there are obtained the same effects as in the first to sixth embodiments.

[0252] (Eighth Embodiment)

[0253] This eighth embodiment describes modifications of the masks and fabrication methods described in the fifth to seventh embodiments.

[0254] An example of a method for fabricating a mask according to this eighth embodiment will be described below with reference to FIG. 34.

[0255] As shown in FIG. 34(a), light shielding patterns 2a, 2b and mask patterns 4b are formed on the main surface of the mask substrate 1 in the same way as in the first and seventh embodiment. Subsequently, as shown in FIG. 34(b), a resist film 20 which is apparent to exposure light is formed by coating on the main surface of the mask substrate 1 so as to cover the light shielding patterns 2a, 2b and the substrate main surface. Further, a resist film 3 having a light shielding property such as that used in the fifth embodiment was formed thereon as a thin translucent film. As the transparent resist film 20 there was used, as an example, PGMA24 (polyglycidyl methacrylate) exhibiting a negative type. The light shielding resist film 3 was formed of a novolak resin of about 50 nm in thickness exhibiting a negative type as an example. Thereafter, a desired integrated circuit pattern was plotted on the resist film 3 with electron beam. Also at this time there was performed the foregoing antistatic treatment. Then, the resist film 3 was subjected to development in the conventional manner to form halftone patterns 3e by resist film, as shown in FIG. 34(c).

[0256] Subsequently, the main surface of the mask substrate 1 was subjected to exposure in the conventional manner so that the portion of the resist film 20 exposed from the light shielding halftone patterns 3e was exposed to light, followed by development to form a phase adjusting film constituted by the resist film 20 in a self-alignment manner relative to the halftone patterns 3e, as shown in FIG. 34(d). In this way there was fabricated a mask PM8.

[0257] In the mask PM8, the resist film 20 (phase adjusting film) is present only under each halftone pattern 3e. The phase of exposure light passing through the mask PM8 is adjusted by adjusting the thickness of each halftone pattern 3e and resist film 20 (phase adjusting film). In this way there could be attained a phase inversion of 180° between the light having passed through the laminated pattern region of the halftone patterns 3e and resist film 20 (phase adjusting film) and the light having passed through only the mask substrate 1. The transmittance of the laminated pattern region was about 5%. That is, as in the sixth and seventh embodiments there could be produced a mask PM8 having halftone patterns 3e of 5% in transmittance. In this case, correction or change of the halftone patterns 3e may be made after patterning of the resist film 20. In case of making the pattern change, both halftone patterns 34 and resist film 20 are removed and the fabrication process is again started, beginning with coating of the resist film 20.

[0258] Also in this eighth embodiment there are obtained the same effects as in the first to seventh embodiments.

[0259] (Ninth Embodiment)

[0260] This ninth embodiment describes a modified example of a mask, which is a combination of an ordinary halftone mask and such a halftone mask using a resist film as in the fifth to eighth embodiments.

[0261]
FIG. 35 shows a concrete example of a mask PM9 according to this ninth embodiment. In the mask PM9, line patterns such as wiring lines are transferred onto a wafer through halftone patterns. More specifically, ordinary halftone patterns 21a of MoSiOx of MoSiON and halftone patterns 3c of resist film described in the fifth to eighth embodiments are formed in the integrated circuit pattern region on the main surface of the mask substrate 1. The film thickness of the halftone patterns 3c was set at a thickness required for phase inversion and satisfying a desired light shielding performance as in the fifth to eighth embodiments. Therefore, the phase difference of transmitted lights is not limited to 180°, but can be selected from among various values, including 540° and 900°.

[0262]
FIG. 35(b) shows a state of phase inversion of exposure light radiated from the back side of the mask PM9. Exposure light having passed through the halftone patterns 3c and 21a is 180° inverted in phase with respect to exposure light having passed through a transparent portion (light transmitting region). That is, the phases of the exposure lights are reverse to each other.

[0263] An example of a method for fabricating the mask PM9 will be described below with reference to FIG. 36.

[0264] First, as shown in FIG. 36(a), a halftone film 21 of, for example, MoSiOx or MoSiON is formed on the main surface of the mask substrate 1 by sputtering or CVD for example. Thereafter, using the foregoing metal for light shielding film, a light shielding film 2 is deposited on the halftone tone film 21 by sputtering. Subsequently, the light shielding film 2 and the halftone film 21 are subjected to patterning in accordance with the conventional photolithography technique and etching technique to form halftone patterns 21a, light shielding patterns 2b, and mark patterns 4b, as shown in FIG. 36(b). Then, as shown in FIG. 36(c), a resist film 22 is formed so as to cover the light shielding patterns 2b in the other region than the region where the halftone patterns 21 are formed. Thereafter, with the resist film 22 as an etching mask, the light shielding film 2 exposed therefrom is removed, allowing the halftone patterns 21a to be exposed, as shown in FIG. 36(d). Then, as shown in FIG. 36(e), a resist film 3 for a light shielding mask is formed by coating and electron beam is radiated to predetermined positions to form halftone patterns 3c of resist film 3 shown in FIG. 35. How to correct or change the halftone patterns 3c is the same as in the first embodiment.

[0265] Also in this ninth embodiment there are obtained he same effects as in the first to seventh embodiment.

[0266] (Tenth Embodiment)

[0267]
FIG. 10 describes a modified example of a mask, which is a combination of an alternating phase shift mask, i.e., a Levenson type phase shift mask, and a such a light shielding pattern mask using a resist film as in the first to fourth embodiments.

[0268]
FIG. 37 shows a concrete example of a mask PM10 according to this tenth embodiment, which mask is for the transfer of such line patterns as wiring lines onto a wafer. In an integrated circuit pattern region on a main surface of the mask PM10 are arranged a Levenson type phase shift pattern region (left-hand side in FIG. 37(a) and a light shielding patterns 3a region (right-hand side in FIG. 37(a)) of resist film as described in the first to fourth embodiments.

[0269] In the Levenson type phase shift pattern region are arranged plural light shielding patterns 2a of metal, light transmitting patterns 16f adjacent to each other on both sides of each light shielding pattern 2a, and phase shifters 22a positioned on one side of the adjacent light transmitting patterns 16f. For example, the phase shifters 22a are trench shifters. As the structure of the trench shifters there may be adopted a structure wherein a portion in the transverse direction of each trench is allowed to overhang lower portions of the light shielding patterns 2a. According to this structure it is possible to improve the pattern transfer accuracy. FIG. 37(b) shows a state of phase inversion of exposure light radiated from the back side of the mask PM10. Exposure light having passed through the phase shifters 22a is 180° inverted in phase with respect to exposure light having passed through the light transmitting patterns 16f free from phase shifters 22a. That is, the phases of both exposure lights are opposite to each other. On the other hand, the light shielding patterns 3a are the same as in the first embodiment, etc. Therefore, correction and change of the light shielding patterns 3a can be done easily.

[0270] It is preferable that the mask PM10 be applied to a semiconductor integrated circuit device having such a memory as DRAM. In the semiconductor integrated circuit device having such a memory as DRAM, elements and wiring lines in memory cell region are becoming more and more fine. Therefore, in forming word lines, data lines, or hole patterns, there sometimes occurs a case where the transfer of pattern is infeasible unless there is used a Levenson type phase shift mask. In other peripheral circuit region and logic circuit region than the memory cell region it is not necessary to use a Levenson type phase shift mask, but there sometimes is a case where a customer or product specification requires various changes of peripheral circuit and logic circuit patterns. The mask PM10 can cope with both such requests. More particularly, on the memory cell region side it is possible to transfer patterns of fine elements and wiring lines, while in the other circuit region than the memory cell region it is possible to cope with various changes in pattern shape flexibly in a short time. Since correction and change of the patterns can be done after formation of trenches for phase shifters, it is possible to shorten the time required for mask fabrication. Additionally, also in this tenth embodiment there can be obtained the same effects as in the first to ninth embodiments.

[0271] (Eleventh Embodiment)

[0272] This eleventh embodiment described a modified example of a mask, which is a combination of a conventional Levenson type phase shift mask and a Levenson type phase shift mask fabricated using such light shielding patterns of resist film as described in the first to fourth embodiments.

[0273]
FIG. 38 shows a concrete example of a mask PM1 according to this eleventh embodiment, which mask is for transferring line patterns such as wiring lines onto a wafer. In an integrated circuit pattern region on a main surface of the mask PM11 are arranged a Levenson type phase shift pattern region (left-hand side in FIG. 38) and a Levenson type phase shift pattern (right-hand side in FIG. 28) constituted by such light shielding patterns 3a of resist film as described in the first to fourth embodiments.

[0274] The left-hand Levenson type phase shift pattern region is the same as in the tenth embodiment, so an explanation thereof will here be omitted. On the right-hand side of FIG. 38 is formed a phase shifter 22b by patterning a photosensitive transparent film such as a photosensitive SOG film, and light shielding patterns 3a of resist film are formed by patterning so as to cover side faces and the vicinity thereof of the phase shifter 22b. With the light shielding patterns 3a there are defined light transmitting patterns 16g to which a part of the main surface of the mask substrate 1 is exposed and a light transmitting pattern 16h to which a part of an upper surface of the phase shifter 22b is exposed. The phases of lights having passed through mutually adjacent light transmitting patterns 16g and 16h are 180° inverted with respect to each other.

[0275] The mask PM11 thus constructed is fabricated in the following manner. First, light shielding patterns 2a and 2b of metal are formed on the main surface of the mask substrate 1 in the same way as in the fabrication of the ordinary mask, then trenches are formed by digging predetermined portions of the main surface of the mask substrate 1 to form phase shifters 22a. Subsequently, a photosensitive SOG film for example is formed on the main surface of the mask substrate 1 by coating, followed by patterning in accordance with the photolithography technique to form a phase shifter 22b. Then, the foregoing resist film for the formation of a light shielding film is formed on the main surface of the mask substrate 1 by coating and is subjected to patterning by photolithography to form light shielding patterns 3a.

[0276] Also in this eleventh embodiment there can be obtained the same effects as in the first to ninth embodiments.

[0277] (Twelfth Embodiment)

[0278] This twelfth embodiment describes a modified example of a mask, which is a combination of an ordinary mask and a Levenson type phase shift mask constituted by such light shielding patterns of resist film as in the eleventh embodiment.

[0279]
FIG. 39 shows a concrete example of a mask PM12 according to this twelfth embodiment, which mask is used to transfer line patterns such as wiring lines onto a wafer. In an integrated circuit pattern region on a main surface of the mask PM12 are arranged a pattern region of an ordinary mask (left-hand side in FIG. 39) and a Levenson type phase shift pattern region (right-hand side in FIG. 39) constituted by such light light shielding patterns 3a of resist film as described in the eleventh embodiment. The method of fabricating the mask PM12 is almost the same as in the eleventh embodiment and is different in that the step of forming the trenched phase shifters 22a is not included.

[0280] Also in this twelfth embodiment there can be obtained the same effects as in the first to ninth embodiments.

[0281] (Thirteenth Embodiment)

[0282] This thirteenth embodiment describes a modified example of a mask.

[0283] In the mask of this embodiment, as noted previously, since patterns on the mask are removed, the light shielding patterns formed of metal are required to have a certain degree of resistance. In this thirteenth embodiment, therefore, a protective film is formed on the surfaces of light shielding patterns formed of metal.

[0284]
FIG. 40(a) shows a concrete example of a mask PM13 according to this thirteenth embodiment. A thin protective film 23 of silicon oxide, for example, is formed on surfaces of light shielding patterns 2a and 2b (more specifically, on upper surfaces and side faces of the light shielding patterns 2a and 2b) which are formed of metal on the mask substrate 1. Consequently, the light shielding patterns 2a and 2b can be protected at the time of peeling and washing of resist film (light shielding patterns 3a) of the mask PM13, whereby the resistance of the light shielding patterns 2a and 2b can be improved. Particularly, when there are formed light shielding patterns 2a for the transfer of fine integrated circuit patterns, the structure of this embodiment wherein the protective film 23 covers the whole surfaces of the light shielding patterns 2a is preferable in point of improving the resistance to peeling of the light shielding patterns 2a. The protective film 23 is formed by CVD or sputtering for example after patterning of the light shielding patterns 2a and 2b. Light shielding patterns 3a of resist film are formed on the protective film 23 by patterning. FIG. 40(b) shows a removed state of the light shielding patterns 3a. For forming new light shielding patterns, a resist film for forming light shielding patterns is applied and patterns are plotted thereon using electron beam for example in the same manner as in the first embodiment. This structure is applicable to all of the first to twelfth embodiments.

[0285] In this thirteenth embodiment there can be obtained the effect that the service life of the mask PM13 can be improved, in addition to the effects obtained in the first to twelfth embodiments.

[0286] (Fourteenth Embodiment)

[0287] This fourteenth embodiment describes a modification of the previous thirteenth embodiment.

[0288]
FIG. 41(a) shows a concrete example of a section of a mask PM14 according to this fourteenth embodiment. In this fourteenth embodiment, a protective film 23 is applied to only the upper surfaces of the light shielding patterns 2a and 2b. In this case, the protective film 23 is formed simultaneously with formation of the light shielding patterns 2a and 2b by first depositing a light shielding film on the mask substrate 1 by sputtering, then depositing the protective film 23 by CVD or sputtering, and thereafter patterning the light shielding film. Other points are the same as in the thirteenth embodiment. FIG. 41(b) shows a removed state of the light shielding patterns 3a. Also in this case, the resistance of the light shielding patterns 2a and 2b can be improved and hence it becomes possible to improve the service life of the mask PM14.

[0289] (Fifteenth Embodiment)

[0290] This fifteenth embodiment describes a modified example of a mask.

[0291] According to studies made by the present inventors it has turned out that it is also effective to first form light shielding patterns of resist film on a main surface of a mask substrate which patterns are for forming the foregoing integrated circuit patterns and mark patterns and thereafter form a transparent protective film on the mask substrate main surface so as to cover the light shielding patterns. As a result, it is possible to improve the mechanical strength of the light shielding patterns formed of resist film. Besides, since oxygen is shut out by the protective film, it is possible to prevent a change in film quality of the light shielding patterns formed of resist film.

[0292]
FIG. 42 shows a concrete example of such a mask PM15 according to this fifteenth embodiment. On the whole of a main surface of a mask substrate which constitutes the mask PM15 is formed a protective film 24 using, for example, a silicon oxide film or an applied silicon compound. In case of forming the protective film 24 by a silicon oxide film, the film formation may be done by sputtering or CVD, while in case of forming the protective film 24 by an applied silicon compound, it is preferable to conduct a heat treatment at 100° to 200° C. for example after the application.

[0293] In the mask 15 of this fifteenth embodiment, the protective film 24 is deposited on the entire main surface of the mask substrate 1 so as to cover light shielding patterns 2a, 2b, and 3a. That is, in case of attaching the mask PM15 to an inspection system or an exposure system, the protective film 24 of the mask PM15 comes into contact with loading portions of the inspection system or exposure system. Thus, as in the first to fourteenth embodiments, the loading portions of the inspection system or exposure system do not come into direct contact with resist film patterns (light shielding patterns 3a, etc.), so it is possible to prevent peel-off and chipping of the resist film caused by mounting of the mask and hence possible to prevent the resultant generation of dust particles.

[0294] (Sixteenth Embodiment)

[0295] In this sixteenth embodiment, a description will be given below about problems induced when both light shielding patterns of metal and light shielding patterns of resist film are formed on a mask, and also about means for solving the problems.

[0296]
FIG. 43(a) is a plan view of a principal portion of a mask which is used to transfer a plurality of adjacent line patterns onto a wafer. In the same figure there are shown connections between light shielding patterns 2a of metal and light shielding patterns 3a of resist film, which are for the transfer of line patterns. FIG. 43(b) is a sectional view taken on line A-A in FIG. 43(a).

[0297] In the illustrated example, the light shielding patterns 2a and 3a overlap each other without positional deviation. However, since the light shielding patterns 2a and 3a are subjected to patterning separately from each other, it is not always possible to arrange the two in such a satisfactory state of alignment. There may occur such a displacement in the pattern width direction as shown in FIG. 44(a). Upon occurrence of such a displacement of pattern, there arises the problem that a required spacing dl between adjacent patterns cannot be ensured. Further, as shown in FIG. 44(b), even in an overlapped portion of isolated light shielding patterns 2a and 3a, the respective patterns are greatly displaced in their width direction, making it impossible to ensure a satisfactory state of connection.

[0298] Therefore, in a mask PM16 of this sixteenth embodiment, as shown in FIG. 45, even for a portion where a light shielding pattern 2a of metal and a light shielding pattern 3a of resist film are to be connected together, if a predetermined condition is satisfied, both patterns are arranged spacedly from each other.

[0299]
FIG. 46(a) shows a case where light shielding patterns 2a of metal and light shielding patterns 3a of resist film are displaced from each other in the pattern width direction in the mask PM16 of this sixteenth embodiment. FIG. 46(b) is a plan view showing a case where conductor film patterns 10a1 were formed on a wafer 8 with use of the mask PM16. FIG. 46(c) is a sectional view taken on line AA in FIG. 46(b). Adjacent conductor film patterns 10a1 must be connected together and therefore, as shown in FIGS. 47(a) to (c), adjacent conductor film patterns 10a1 are connected together through an overlying conductor film pattern 10f. FIG. 47(a) shows a case where adjacent conductor film patterns 10a1 are in a satisfactory relative positional relation, FIG. 47(b) shows a case where both patterns are displaced from each other, and FIG. 47(c) is a sectional view taken on line A-A in FIGS. 47(a) and (b). Adjacent conductor film patterns 10a1 are electrically connected to the conductor film pattern 10f respectively through through-holes 25 formed in an insulating film 9b and are thereby connected electrically to each other.

[0300] (Seventeenth Embodiment)

[0301] This seventeenth embodiment describes another means for solving the problems referred to in the previous sixteenth embodiment.

[0302] According to this seventeenth embodiment, in both or one of a light shielding pattern of metal and a light shielding pattern of resist film, each connecting portion is made wider than the other pattern portion. FIG. 48 shows a concrete example thereof. FIG. 48(a) is a plan view of a principal portion of a mask PM17 and FIG. 48(b) is a sectional view taken on line A-A in FIG. 48(a). In the illustrated example, an end portion of a light shielding pattern 2a of metal is wider than the other portion, and an end portion of a light shielding pattern 3a of resist film overlaps the wide portion of the light shielding pattern 2a of metal. By so doing, even if there occurs a slight deviation in a relative position between the light shielding patterns 2a and 3a, it is possible to ensure a sufficient overlap quantity of both patterns. Patterns transferred by the mask PM17 are shown in FIG. 49. A conductor film pattern 10a transferred through the light shielding pattern 2a of metal and a conductor film pattern 10a1 transferred through the light shielding pattern 3a of resist film are connected together as designed although a wider portion is formed in the connection between both patterns. FIG. 49(a) is a plan view of a principal portion of a wafer and FIG. 49(b) is a sectional view taken on line A-A in FIG. 49(a).

[0303] As another method, the overlap quantity of both light shielding patterns 2a and 3a may be set at a value of not lower than the alignment accuracy of patterns.

[0304] (Eighteenth Embodiment)

[0305] This eighteenth embodiment describes a modification of the previous seventeenth embodiment.

[0306] According to this eighteenth embodiment, as shown in FIG. 50, in both of a light shielding pattern 2a of metal and a light shielding pattern 3a of resist film in a mask PM of this eighteenth embodiment, respective connecting portions are made wider than the other portions. FIG. 50(a) shows a case where both light shielding patterns 2a and 3a are arranged in a satisfactory state of alignment, while FIG. 50(b) shows a case where both light shielding patterns 2a and 3a are displaced from each other in their width direction. Also in this case, even if a relative position of both light shielding patters 2a and 3a undergoes a slight positional deviation, it is possible to ensure a sufficient overlap quantity of both patterns. This method is also applicable to the transfer of patterns narrow in the pitch of adjacent patterns because the thickening quantity of end portions of both light shielding patterns 2a and 3a can be made small.

[0307] (Nineteenth Embodiment)

[0308] This nineteenth embodiment describes a case where the technical idea of the present invention is applied to the manufacture such an ASIC (Application Specific IC) as a gate array or a standard cell.

[0309]
FIG. 51 shows a configuration example of a semiconductor chip 8c4 according to this nineteenth embodiment. On a main surface of the semiconductor chip 8c4 are arranged a memory, an IF controller, a CPU, an application logic circuit, and an analog section. Along an outer periphery of these circuits in the semiconductor chip 8c4 there are arranged a plurality of I/O circuit regions 26, in which are arranged input and output circuits or I/O bilateral circuits. Further, bonding pads BP are arranged along an outer periphery of and in corresponding relation to the I/O circuit regions 26.

[0310] Of those circuits, the I/F controller and the application logic circuit are apt to undergo correction or change in accordance with a customer's request. In this nineteenth embodiment, therefore, the portion concerned is gate-arrayed and the light shielding patterns on the mask for the transfer of that portion are formed of resist film as explained above in the first to eighteenth embodiments, and light shielding patterns on the mask for the transfer of patterns in the other circuit region are formed of metal.

[0311]
FIG. 52(a) is a plan view of a basic cell BC disposed in the IF controller and the application logic circuit and FIG. 52(b) is a sectional view of FIG. 52(a). In the region where the IF controller and the application logic circuit are formed there are arranged plural basic cells BC so as to spread all over the whole surface (so-called SOG structure: Sea Of Gate). For example, each BC is composed of two nMIS Qn and two pMIS Qp. Gate electrodes 10b are shared by nMIS Qn and pMIS Qp and are arranged so as to span both regions. A power line 10VDD is a high voltage (3.3V or 1.8V for example) power line, while a power line 10VSS is a low voltage (0V for exmaple) power line. The power lines 10VDD and 10VSS are arranged so as to cross the gate electrodes 10b and extend along an extending direction of n well NWL and p well PWL. Vertical structures of the nMIS Qn and pMIS Qp have already been described in the first embodiment and so explanations thereof will here be omitted.

[0312] Fabrication up to the stage of the basis cell BS has been completed and the shape of pattern up to that stage has been determined. Therefore, the basic cell BC is subjected to patterning through an ordinary type of mask. Desired circuits are formed by overlying wiring layers and by arranging contact holes and through holes. FIG. 52(c) is a sectional view after formation of a first-layer wiring 10e, a second-layer wiring 10 g, and a third-layer wiring 10h. The second-layer wiring 10 g is electrically connected to the first-layer wiring 10e through a through hole 27a formed in an interlayer insulating film 9f. The third-layer wiring 10h is electrically connected to the second-layer wiring 10 g through a through hole 27b formed in an interlayer insulating film 9g. The pattern shape of the first- to third-layer wirings 10e, 10g, 10h and the arrangement of contact holes 15 and through holes 27a, 27b may be changed in compliance with a customer's request, so for forming their patterns there is used a mask having light shielding patterns formed of resist film.

[0313] Next, the following description is provided about an example of changing patterns on a mask.

[0314]
FIG. 53 illustrates a NAND circuit ND formed using the basic cell BC described above. FIG. 53(a) is a symbol diagram of the NAND circuit ND, FIG. 53(b) is a circuit diagram thereof, and FIG. 53(c) is a plan view showing a layout thereof. The NAND circuit ND illustrated therein has two inputs 11, 12 and one output F.

[0315] As shown in FIG. 53(c), wiring lines 10i connected respectively to the inputs 11 and 12 are electrically connected to the gate electrodes 10b respectively through contact holes 15a. The power line 10VDD is electrically connected to semiconductor regions 14 of both pMIS Qp through contact holes 15b and 15c. The wiring line 10j is electrically connected through a contact hole 15d to a semiconductor region 14 which is common to both pMIS Qp. The wiring line 10j is also connected electrically through a contact hole 15e to a semiconductor region 13 of one nMIS Qn. Further, the power line 10VSS is electrically connected through a contact hole 15f to the semiconductor region 13 of one nMIS Qn. Although in FIG. 53 the contact holes 15a to 15f are shown in a square shape in plan, they are actually in a generally circular shape.

[0316] FIGS. 54(a) and (b) are examples of plan views of pattern principal portions in masks which are used for the transfer of patterns of the contact holes and wiring lines used in the NAND circuit ND. The masks shown in FIGS. 54(a) and (b) are separate masks and therefore X, Y axes are used to make a positional relation of the two clear.

[0317]
FIG. 54(a) illustrates patterns of a mask PM19C which is for transferring the contact holes 15a to 15f shown in FIG. 53(c) onto a wafer. A light shielding film 3f is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment, etc. The light shielding film 3f is partially removed to form fine light transmitting patterns 16g in plural positions which patterns 16g are each square in plan. The light transmitting patterns 16g are for forming the contact holes 15a to 15f. In transferring the patterns on the mask onto a wafer there is used a positive type resist film on the wafer.

[0318]
FIG. 54(b) illustrates patterns of a mask PM19L which is for transferring the wiring lines 10i, 10j and power lines 10VDD, 10VSS shown in FIG. 53(c) onto a wafer. A light shielding film 3g is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment, etc. The light shielding film 3g is partially removed to form light transmitting patterns 16h in plural positions. The light transmitting patterns 16h are for the formation of wiring lines 10i, 10j and power lines 10VDD, 10VSS. In transferring the patterns on the mask onto a wafer there is used a negative type resist film on the wafer.

[0319]
FIG. 55 illustrates a two-input NOR circuit NR formed using the basic cell BC described above. FIG. 55(a) is a symbol diagram of the NOR circuit NR, FIG. 55(b) is a circuit diagram thereof, and FIG. 55(c) is a plan view showing layout thereof. A description will be given below about a portion different from the NAND circuit configuration of FIG. 53(c).

[0320] As shown in FIG. 55(c), a power line 10VDD is electrically connected to a semiconductor region 14 of one pMIS Qp through a contact hole 15b. A wiring line 10k is electrically connected to the semiconductor region 14 of one pMIS Qp through a contact hole 15g. The wiring line 10k is also connected electrically to a common semiconductor region 13 of both nMIS Qn through a contact hole 15h. Further, a power line 10VSS is electrically connected to the semiconductor region 13 of both nMIS Qn through contact holes 15f and 15i. Also in FIG. 55 the contact holes 15a, 15b, 15f, 15g to 15i are shown in square shape in plan, but actually they are in a generally circular shape.

[0321] FIGS. 56(a) and (b) show examples of plan views of pattern principal portions in masks which are used for transfer of patterns of the contact holes and wiring lines in the NOR circuit NR. The masks shown in FIGS. 56(a) and (b) are separate masks and therefore X and Y axes are used to make a positional relation of the two clear.

[0322]
FIG. 56(a) illustrates patterns of a mask PM19C which is for transferring the contact holes 15a, 15b, 15f, and 15g to 15i shown in FIG. 55(c) onto a wafer. A light shielding film 3h is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment. The light shielding pattern 3h is partially removed to from fine light transmitting patterns 16i in plural positions which patterns 16i are each square in plan. The light transmitting patterns 16i are for forming the contact holes 15a, 15b, 15f, and 15g to 15i. In transferring the patterns on the mask onto a wafer there is used a positive type resist film on the wafer.

[0323]
FIG. 56(b) illustrates patterns of a mask PM19L which is for transferring the wiring lines 10i, 10k and power lines 10VDD, 10VSS shown in FIG. 55(c) onto a wafer. A light shielding film 3i is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment, etc. The light shielding film 3i is partially removed to form light transmitting patterns 16j in plural positions. The light transmitting patterns 16j are for forming the wiring lines 10i, 10k and power lines 10VDD, 10VSS. In transferring the patterns on the mask onto a wafer there is used a negative type resist film on the wafer.

[0324] The change of patterns on the masks PM19C and PM19L shown in FIGS. 54 and 56 may be done in the same way as in the first embodiment, etc. For example, patterns for the NAND circuit of the mask PM19C shown in FIG. 54 can be changed into patterns for the NOR circuit of the mask PM19C shown in FIG. 56 by first removing the light shielding film 3f on the mask PM19C shown in FIG. 56, then newly applying the resist film for forming a light shielding film onto the mask substrate and thereafter plotting patterns for the NOR circuit with use of electron beam or ultraviolet ray to form the light shield film 3h and light transmitting patterns 16i of the mask PM19C shown in FIG. 56. That is, a change of patterns from NAND circuit to NOR circuit and vice versa can be done easily in a short time. Consequently, it is possible to greatly shorten the time required for the development and manufacture of a semiconductor integrated circuit device using the mask. Besides, since the material cost and process cost can be reduced, it becomes possible to greatly reduce the cost of the semiconductor integrated circuit device obtained. Therefore, even in the case of a semiconductor integrated circuit device to be produced in a small lot, it is possible to attain the reduction of cost.

[0325] Thus, also in this nineteenth embodiment there can be obtained the same effects as in the first embodiment, etc.

[0326] (Twentieth Embodiment)

[0327] In this twentieth embodiment a description will be given below about the case where the technical idea of the present invention is applied to the manufacture of a mask ROM.

[0328] In a mask ROM it is possible to implement a memory of a large capacity because the mask ROM is formed of a MIS using one memory cell. Besides, an entire circuit configuration can be made simple because a write operation is not needed. However, since the contents of memory changes depending on a customer's request, TAT becomes longer than in other ROMs (e.g., EEPROM (Electric Erasable Programmable Read Only Memory). Moreover, it is required to fabricate different masks for various ROM codes of customers, thus giving rise to the problem that the product cost become high in case of a small lot production. In this twentieth embodiment, in view of these problems, various patterns for the change of a memory cell region are transferred on the basis of the above base data and using a mask which uses the foregoing light shielding patterns of resist film, to change the memory contents. As to patterns for the transfer of patterns in the other region than the memory cell region on the mask, they were formed using light shielding patterns of metal. Of course, all of the integrated circuit patterns may be formed using light shielding patterns of resist film.

[0329]
FIG. 57 shows base data of a mask ROM, in which (a) is a plan view showing a layout of a memory cell region, (b) is a circuit diagram thereof, and (c) is a sectional view taken on line A-A in (a). The illustrated mask ROM is an ion implantation program type mask ROM. Data lines 10m are electrically connected to semiconductor regions 13 through contact holes 15j. Gate electrodes 10b are formed of portions of word lines WL. One memory cell is formed of one nMOS Qn located near an intersecting point between a data line 10m and a word line WL. In this ion implantation program type ROM, a type with a high threshold voltage of nMIS Qn (high to the extent of not turning conductive even at a high level of word line WL) and a type with a low threshold voltage of nMIS Qn (turns conductive at a high level of word line WL) are fabricated selectively depending on whether an impurity is introduced or not into the channel region of nMIS Qn which constitutes the memory cell, and they are made corresponding to “0” and “1” of information. For the transfer of patterns of the base data there was used a mask having the foregoing light shielding patterns of metal. Of course, the data base patterns may be formed using light shielding patterns of resist film.

[0330] Next, an example of an information rewriting method in a mask ROM will be described below with reference to FIGS. 58 to 60. In each of FIGS. 58 and 59, (a) is a plan view of a principal portion of a mask, (b) is a plan view of layout of a memory cell region in a mask ROM, showing patterns for writing memory information, and (c) is a sectional view taken on line A-A in FIG. 57(a) in an information write step.

[0331] First, in FIG. 58, an opening pattern 28a shown in (b) is formed on a data base using a mask PM20 shown in (a), then as shown in (c), an impurity is ion-implanted into a semiconductor substrate 8s which is exposed from the opening pattern 28a, to write memory information. A light shielding film 3j of the mask PM20 is formed of the same resist material as that of the light shielding patterns 3a used in the first embodiment. A part of the light shielding film 3j is removed to form a light transmitting pattern 16k having a square shape in plan. The light transmitting pattern 16k is for forming the opening pattern 28a in a resist film lib on wafer 8. As the resist film 11b there is used a positive type resist film. The impurity introducing step for the write of information is carried out before the formation of gate electrodes 10b (i.e., word lines WL). As the impurity there may be used, for example, boron if it is intended to increase the threshold value of nMIS Qn, or phosphorus or arsenic if it is intended to decrease the threshold value of nMIS Qn.

[0332] In FIG. 59, opening patterns 28b and 28c shown in (b) are formed on a data base using a mask PM20 shown in (a), then, as shown in (c), an impurity is ion-implanted into a semiconductor substrate 8s which is exposed from the opening patterns 28b and 28c, to write memory information. A light shielding film 3k of the mask PM20 is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment. The light shielding pattern 3k is partially removed to form two light transmitting patterns 16m and 16n having a square shape in plan. The light transmitting patterns 16m and 16n are for forming opening patterns 28b and 28c in a resist film 11b on wafer 8.

[0333] Next, in FIG. 60, an opening pattern 28d shown in (b) is formed on a data base using a mask PM20 shown in (a), then, as shown in (c), an impurity is ion-implanted into a semiconductor substrate 8s which is exposed from the opening pattern 28d, to write memory information. A light shielding film 3m of the mask PM20 is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment. A part of the light shielding film 3m is removed to form a light transmitting pattern 16p. The light transmitting pattern 16p is for forming the opening pattern 28d in a resist film 11b on wafer 8.

[0334] In the masks PM20 shown in FIGS. 58 to 60, the change of pattern may be done in he same way as in the first embodiment, etc. For example, the pattern of mask PM20 in FIG. 58 can be changed into the patterns of mask PM20 in FIG. 59 by first removing the light shielding film 3j on the mask PM20 in FIG. 58, then newly applying the foregoing resist film for forming a light shielding film onto the mask substrate, and subsequently radiating electron beam or ultraviolet ray to predetermined positions of the resist film to form the light shielding film 3k and light transmitting patterns 16m, 16n of the mask PM20 shown in FIG. 59. In this way various types of mask ROMs can be fabricated efficiently and can greatly reduced in TAT. Moreover, since the material cost and process cost can be reduced, it is possible to greatly reduce the cost of a mask ROM even when produced in a small lot.

[0335] Thus, also in this twentieth embodiment there can be obtained the same effects as in the first embodiment, etc.

[0336] (Twenty-First Embodiment)

[0337] This twenty-first embodiment is a modification of the previous twentieth embodiment, described an information write method different from that using the mask ROM of the twentieth embodiment.

[0338]
FIG. 61 shows base data of a mask ROM according to this twenty-first embodiment, in which (a) is a plan view showing a layout of a memory cell region, (b) is a circuit diagram thereof, and (c) is a sectional view taken on line A-A in (a). The mask ROM of this embodiment is a contact hole program type ROM, in which programming is carried out by adjusting the layout of contact holes (indicated with broken lines in FIG. 61(b)) for connection between semiconductor region 13 and data lines 10m. The mask of this twenty-first embodiment also uses the foregoing light shielding patterns of metal for the transfer of base data patterns.

[0339] Next, an example of an information rewriting method using a mask ROM will be described with reference to FIGS. 62 to 65. In each of FIGS. 62, 64, and 65, (a) is a plan view of a principal portion of a mask, (b) is a plan view of layout of a memory cell region in a mask ROM, showing patterns for the write of information into memory, (c) is a circuit diagram thereof, and (d) is a sectional view taken on line A-A in (b).

[0340] In FIG. 62, first using a mask PM21 shown in (a), a contact hole 15k shown in (b) is formed on a data base, then, as shown in (c) and (d), semiconductor regions 13 in a predetermined nMIS Qn and data lines 10m are connected together to write memory information.

[0341] A light shielding film 3p of the mask PM21 is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment. The light shielding film 3p is partially removed to form a light transmitting pattern 16m having a square shape in plan. The light transmitting pattern 16m is for forming an opening pattern for the formation of the contact hole 15k in a resist film on wafer 8. How to form the contact hole 15k is the same as in the first embodiment, etc. A brief description will now be given on this point. First, as shown in FIG. 63(a), a positive type resist film 11 is applied onto an insulating film 9d, followed by the transfer of pattern onto the resist film 11b using the mask PM21 of FIG. 62, and subsequent development to form an opening pattern 28e. Then, with the resist film 11b as an etching mask, there is performed etching to form a contact hole 15k in the insulating film 9 so as to expose a part of a semiconductor substrate 8s, as shown in FIG. 63(b).

[0342] Next, in FIG. 64, using a mask PM21 shown in (a), two contact holes 15m and 15n shown in (b) are formed on a data base, then as shown in (c) and (d), semiconductor regions 12 and data lines 10m in a predetermined nMIS Qn are connected together to write memory information. A light shielding film 3q of the mask PM21 is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment. The light shielding film 3q is partially removed to form light transmitting openings 16q having a square shape in plan. The light transmitting patterns 16q are for forming opening patterns for the formation of contact holes 15m, 15n and word line contact holes in a resist film on wafer 8. How to form the contact holes 15m, 15n and word line contact holes is the same as that described in connection with FIGS. 63(a) and (b), so explanations thereof will here be omitted.

[0343] Next, in FIG. 65, using a mask PM21 shown in (a), three contact holes 15k, 15m, and 15n shown in (b) are formed on a data base, then as shown in (c) and (d), semiconductor regions 13 and data lines 10m in a predetermined nMIS Qn are connected together to write memory information. A light shielding film 3r of the mask PM21 is formed using the same resist material as that of the light shielding patterns 3a described in the first embodiment. The light shielding film 3r is partially removed to form light transmitting patterns 16r having a square shape in plan. The light transmitting patterns 16r are used to form opening patterns for the formation of contact holes 15k, 15m, 15n and word contact holes in a resist film on wafer 8. How to form the contact holes 15k, 15m, 15n and word contact holes is the same as that described in connection with FIGS. 63(a) and (b), so an explanation thereof will here be omitted.

[0344] In the masks PM21 of FIGS. 62, 64, and 65, the change of pattern may be done in the same way as in the first embodiment, etc. For example, for changing the patterns of the mask PM21 shown in FIG. 62 into the patterns of the mask PM21 shown in FIG. 64, first the light shielding film 3—on the mask PM2 of FIG. 62 is removed, then the foregoing resist film for the formation of a light shielding film is newly applied onto the mask substrate, and electron beam or ultraviolet ray is radiated to predetermined positions of the resist film to form the light shielding film 3q and light transmitting patterns 16q of the mask PM21 shown in FIG. 64. In this way various types of mask ROMs can be fabricated efficiently as in the twentieth embodiment. Besides, various types of mask ROMs can be greatly reduced in TAT. Further, since the material cost and the process cost can be reduced, it becomes possible to greatly reduce the cost of a mask ROM even when produced in a small lot.

[0345] Thus, also in this twenty-first embodiment there can be obtained the same effects as in the first embodiment, etc.

[0346] (Twenty-Second Embodiment)

[0347] This twenty-second embodiment is a modification of the previous twentieth embodiment, describing a mask ROM of a different structure from the twentieth embodiment.

[0348]
FIG. 66 illustrates a part of a NAND type mask ROM of this twenty-second embodiment. Plural nMISQn which constitute memory cells are connected in parallel through semiconductor regions 13. As a program method there is adopted an ion implantation method. That is, nMIS Qn (memory cell) of an ion-implanted portion becomes a depletion type, while nMIS Qn (memory cell) of a portion not ion-implanted becomes an enhancement type, corresponding respectively to “0” and “1” of information.

[0349] In FIG. 66 there is illustrated an example in which an impurity is introduced into a channel region of nMIS Qnd to provide a depletion type. An opening pattern 28f indicative of a memory information write pattern represents an opening pattern of an ion-implantation mask used at the time of carrying out a program (ion-implantation of impurity) for the nMIS Qnd. A semiconductor region 13VSS also possesses a function as a low voltage (for example, 0V=GND) power line.

[0350] In this twenty-second embodiment, how to change patterns on the mask and how to introduce an impurity selectively into a wafer for program are the same as in the twentieth embodiment, so explanations thereof will here be omitted.

[0351] Also in this twenty-second embodiment it is possible to obtain the same effects as in the previous twenty-first embodiment.

[0352] (Twenty-Third Embodiment)

[0353] In this embodiment a description will be given below about the case where a characteristic of a semiconductor integrated circuit is adjusted using a mask which has the foregoing light shielding patterns of resist film.

[0354]
FIGS. 67 and 68 illustrates circuit each implemented within a semiconductor integrated circuit device formed on a wafer and used for adjusting a characteristic of the integrated circuit device.

[0355]
FIG. 67 is a circuit diagram for characteristic adjustment, using plural resistors R1 to Rn connected in series. In this circuit diagram, the state of connection between a terminal Ta connected to a circuit (e.g., CPU in a semiconductor integrated circuit) and terminals Tb1 to Tbn connected to resistors R1 to Rn is changed by a connector J1 to thereby change the resistance value of the entire circuit.

[0356]
FIG. 68 is a circuit diagram for characteristic adjustment, using plural capacitors C1 to Cn connected in series. Here also the state of connection between a terminal Ta connected to a circuit and terminals Tb1 to Tbn connected to the capacitors C1 to Cn is changed by a connector J1 to thereby change the capacitance value of the entire circuit.

[0357] For example in a development phase of a semiconductor integrated circuit there sometimes is a case where a characteristic adjustment for the semiconductor integrated circuit such as adjustment of a signal timing is made by changing the value of resistance or capacitance variously as described above. If an ordinary mask is used in such a pattern transfer, it is necessary that the mask be re-fabricated at every adjustment despite the portion for change (connector J1) itself being small, as is seen also from the circuit diagrams of FIGS. 67 and 68. Consequently, a so much longer time is required for the fabrication of mask and hence the period for development of the semiconductor integrated circuit device becomes longer. Moreover, such a method is wasteful and causes an increase of both material cost and process cost, with consequent increase in the cost of the semiconductor integrated circuit device.

[0358] In the mask of this embodiment, therefore, the portions for transfer of the connector j1 are formed of light shielding patterns of resist film. FIG. 69(a) is a schematic plan view of the terminals Ta and Tb1 to Tbn formed on a wafer, the terminal Ta being connected to none of the terminals Tb1 to Tbn. FIG. 69(b) shows light shielding patterns 2g on a mask PM23 which are for transfer of the terminals Ta and Tb to Tbn shown in (a). The light shielding patterns 2g are formed of metal like the light shielding patterns 2a described in the first embodiment and are used as base data. For example, if the terminals Ta and Tb1 are to be connected together, as in FIG. 70(a), this requirement can be met by forming a light shielding pattern 3s of resist film at a position corresponding to a connector J1 for both terminals Ta and Tb1 on a main surface (the surface on which the light shielding patterns 2g of metal are formed) of a mask substrate 1 of the mask PM23. The resist material of the light shielding pattern 3s, as well as how to form and change the same pattern, are the same as in the first embodiment. Therefore, the change of connection between the terminal Ta and the terminals Tb1 to Tbn can be done easily in a short time and that at low cost. Consequently, the time required for development of the semiconductor integrated circuit device can be shortened to a great extent and it becomes possible to reduce the cost of the semiconductor integrated circuit device.

[0359] Also in this twenty-third embodiment there can be obtained the same effects as in the first embodiment, etc.

[0360] (Twenty-Fourth Embodiment)

[0361] In this embodiment a description will be given below about a technique for making a logic circuit of a semiconductor integrated circuit device redundant with use of a mask having the foregoing light shielding patterns of resist film.

[0362]
FIG. 71 illustrates a redundant circuit formed on a wafer. Redundancy is effected by changing the way of connection of a connector J2 to thereby change the state of connection among terminals Tc1 to Tc3. INV stands for an inverter circuit.

[0363] Even in such a redundant circuit configuration, if an ordinary mask is used for the transfer of pattern, the mask must be re-fabricated for redundancy despite the portion of change (connector J2) itself is small. Consequently, it takes times for fabrication of the mask and hence the period for the development and manufacture of the semiconductor integrated circuit device becomes longer. Besides, such a circuit configuration is wasteful and increases in both material cost and process cost, so that the cost of the semiconductor integrated circuit device increases.

[0364] In the mask of this embodiment, therefore, the portion for transfer of the connector J2 is formed of a light shielding pattern of resist film. FIG. 72(a) is a schematic plan view of the portions of the terminals Tc1 to Tc3 formed on the wafer. In the same figure, the terminal Tc2 is connected to neither the terminals Tc1 nor Tc3. FIG. 72(b) shows light shielding patterns 2g of metal formed on a mask PM24 for transfer of the terminals Tc1 to Tc3 and are used as base data. For example, as shown in FIG. 73(a), if the terminals Tc1 and Tc2 are to be connected with each other, this connection can be effected by forming a light shielding pattern 3s of resist film at the position corresponding to the connector J2 between the terminals Tc1 and Tc2 on a main surface (the surface where the light shielding patterns 2g of metal are formed) of a mask substrate 1 of the mask PM24. The resist material of the light shielding pattern 3s, as well as how to form and change the same pattern, are the same as in the first embodiment. Consequently, it becomes possible to change the connection of terminals Tc1 to Tc3 easily in a short time and that at low cost. Accordingly, the time required for the development and manufacture of the semiconductor integrated circuit can be greatly shortened and it becomes possible to reduce the cost of the semiconductor integrated circuit.

[0365] Also in this twenty-fourth embodiment it becomes possible to obtain the same effects as in the first embodiment.

[0366] (Twenty-Fifth Embodiment)

[0367] In this embodiment a description will be given below about an example of a series of steps in a fabrication process for a mask described above and in a manufacturing process for a semiconductor integrated circuit device using the mask.

[0368] An ordinary mask fabrication process is divided into a fabrication process for a substrate (mask blank) with a light shielding film of chromium for example and the foregoing translucent film (halftone film) formed on the whole of a main surface thereof and a mask fabrication process for forming semiconductor integrated circuit-forming patterns on the mask blank. There sometimes is a case where both are carried out at different departments.

[0369] A mask fabrication process according to this embodiment is divided into a mask blank fabrication process, a process for forming common light shielding patterns to be used in common in various projection exposure systems along an outer periphery of a mask substrate and for forming common device patterns to form integrated circuit patterns, and a resist pattern forming process. There sometimes is a case where these processes are carried out at different departments or different companies.

[0370] For example, FIG. 74(a) shows a process for forming common light shielding patterns and common device patterns. Common patterns can be provided for each semiconductor integrated circuit device or in accordance with a projection exposure system used in exposure. First, common light shielding patterns (corresponding to the light shielding patterns 2a and 2b in the mask PM1 of FIG. 1) (step 100). Subsequently, a check is made to see if there is any defect (step 101). If there is no defect, the mask concerned is stocked as a common mask completed at the stage of forming common light shielding patterns and common device patterns (step 102). On the other hand, if there is any defect, correction or the like is made (step 103) and thereafter the mask is stocked (step 102).

[0371] Thus, in the mask fabrication process of this embodiment the mask substrate can be stocked during fabrication of the mask and therefore the time required for fabrication and development of a semiconductor integrated circuit device can be greatly shortened. In the case of an ordinary mask, the substrate cannot be stocked in an intermediate step, so the operations from the deposition of a light shielding film (the mask blank manufacturing process) up to patterning of predetermined patterns must be carried out as a through process. On the other hand, in this embodiment the mask which has undergone steps up to the common light shielding patterns and common device patterns fabricating process can be stocked, so for forming concrete integrated circuit patterns (device patterns) in the development and manufacture of a semiconductor integrated circuit device, the fabrication of the mask concerned can be started from the mask stocked stage, thus permitting the mask fabrication time to be shortened. Accordingly, the process of forming integrated circuit patterns can be terminated in a short time. Thus, as noted previously, the technical idea of the present invention is suitable particularly to the fabrication of a mask for a logic device which is high in grade development frequency. In the case of the mask lying in the stage of FIG. 74(a), even if a defect such as a pin-hole is found in the region RE, there arises no problem because the metal film in the region RE is removed. Consequently, it is possible to moderate the quality control of the mask blank and hence possible to greatly improve the yield of the mask blank.

[0372]
FIG. 74(b) shows a process for forming light shielding patterns by resist film on the common mask. First, light shielding patterns of resist film for device manufacture (corresponding to the light shielding patterns 3a in the mask PM1 of FIG. 1) are formed in the integrated circuit pattern region of the common mask in the manner described above (steps 104 and 105). Subsequently, the mask substrate is checked for defect and dimension (step 106). If the mask passes this inspection, it is completed (step 107). On the other hand, if the photomask is rejected in the inspection, the light shielding patterns of resist film are removed and the mask is re-utilized (step 108). Thus, in this embodiment the common mask can be re-utilized. In the case where the light shielding patterns for device manufacture are formed of a metallic film, it is difficult to remove the film and re-utilize the mask, from the standpoint of ensuring the quality of the mask. On the other hand, removing the resist film and re-utilizing the mask as in this embodiment does not take time and can be done easily without deterioration of the mask quality. Consequently, it becomes possible to attain an effective utilization of resources.

[0373]
FIG. 74(c) shows a process wherein the mask thus completed is used in fabricating a semiconductor integrated circuit device and patterns are transferred onto a wafer. In this process, using the completed mask, integrated circuit patterns are transferred onto a wafer (step 109). If the mask is degraded to an unemployable extent or if there occurs a change in part of the semiconductor integrated circuit device, the mask is again fed to the resist removing/regenerating step (step 108) so as to be re-utilized as a common mask.

[0374] Thus, according to this embodiment the mask can be re-utilized from the manufacture of the mask until the manufacture of the semiconductor integrated circuit device. Consequently, it becomes possible to shorten the period for the development and manufacture of the semiconductor integrated circuit device. Besides, since it is possible to diminish wasteful materials and steps, it becomes possible to greatly reduce the cost of the semiconductor integrated circuit device.

[0375] (Twenty-Sixth Embodiment)

[0376] In this embodiment reference will be made below to an application example in the above semiconductor integrated circuit device manufacturing process using a mask.

[0377] A description will now be given of the case where trimming is performed lot by lot. More specifically, an average characteristic information of a multitude lot of semiconductor integrated circuit devices in mass production is fed back to a wiring layer forming step for semiconductor integrated circuit devices of a low which follows, to correct wiring, thereby adjusting a characteristic of the semiconductor integrated circuit devices. This wiring correction is made with use of a mask having light shielding patterns of resist film.

[0378]
FIG. 75 illustrates a related flow. In an elements forming step 301, predetermined integrated circuit elements are formed on a wafer. In a wiring layer forming step (step 302) which follows, wiring lines are formed on the wafer to form an integrated circuit. All wiring layers for a semiconductor integrated circuit device are formed, and after the completion of manufacture of the semiconductor integrated circuit device, each semiconductor integrated circuit device on the wafer is tested for an electric characteristic (step 303). Then, an average characteristic variation information of the semiconductor integrated circuit devices thus fabricated is fed back to the wiring layer forming step for semiconductor integrated circuit devices of the lot which follows the tested lot. On the basis of the information thus fed back, the size and shape of patterns for forming wiring lines on a mask are changed (step 304). As the mask there is used a mask having such light shielding patterns of resist film as described in the previous embodiment. Using this mask, wiring layers of semiconductor integrated circuit devices of the low which follows are formed. In this way trimming of semiconductor integrated circuit devices is performed lot by lot.

[0379] Thus, semiconductor integrated circuit devices uniform in electric characteristic and high in reliability can provided in a short period. Besides, in changing patterns of the mask for trimming, it is possible to omit wasteful material and step and hence possible to provide a highly reliable semiconductor integrated circuit device at low cost.

[0380] (Twenty-Seventh Embodiment)

[0381] This embodiment describes a modification of the previous twenty-sixth embodiment. According to this embodiment, each semiconductor integrated circuit device is tested for a characteristic halfway in the wiring layer forming step and the information obtained is fed forward to the subsequent wiring forming step to adjust the characteristic of the semiconductor integrated circuit device.

[0382]
FIG. 76 shows a related flow. First, after elements forming step (step 301), the flow goes through a wiring layer forming step (step 302a), in which each semiconductor integrated circuit device on the wafer is subjected to an electric characteristic test (step 303). Then, on the basis of the characteristic information on the semiconductor integrated circuit device obtained the size and shape of patterns for wiring formation on the mask, which patterns are to be used in a subsequent final wiring layer forming step (step 302b), are changed (step 304). The final wiring layer indicates a layer for forming bonding pads which function as external terminals of a semiconductor chip for example, or a wiring layer which precedes by one. As the mask there is used a mask having such light shielding patterns of resist film as described in the previous embodiment. Using the mask, there are formed patterns of the final wiring layer on the wafer. By thus trimming the semiconductor integrated circuit device it becomes possible to obtain the same effects as in the previous twenty-sixth embodiment.

[0383] The technical idea of this embodiment according to the present invention is such that in the wiring layer forming step a characteristic of the semiconductor integrated circuit device concerned is tested, then the characteristic information obtained is sent to the wiring layer forming step which follows, and trimming is performed on the basis of the characteristic information and using the mask. The technical idea in question is not limited to the transmission of the information to the final wiring layer forming step. For example, the characteristic information may be sent to any other wiring layer forming step than the final wiring layer forming step or may be sent to plural wiring layer forming steps. As a so-called wafer package technique wherein a sealing step is carried out for example at the stage of wafer, there is one having a structure wherein wiring is conducted again after the formation of bonding pads. In this re-wiring layer forming step the characteristic information may be transmitted and trimming may be conducted on the basis of the characteristic information and with use of the mask.

[0384] (Twenty-Eighth Embodiment)

[0385] In this twenty-eighth embodiment reference will be made below to the case where customer's information is written on a wafer with use of light shielding patterns of resist film formed on a mask.

[0386] In the semiconductor integrated circuit device manufacturing process it is preferable that information pieces such as, for example, customer's name, number, lot number, manufacturing year, month and date, type, grade, and version be written in part of a wafer or a semiconductor chip insofar as possible. This is because by so doing an electric characteristic of the resulting product and the state of pattern change can be seen and it becomes easier to conduct a characteristic test and sorting of semiconductor integrated circuits. With an ordinary mask, however, the write of very detailed information is infeasible because it takes time and cost for the fabrication of mask. In this embodiment, therefore, customer's information is transferred with a mask using the foregoing light shielding patterns of resist film, whereby it becomes possible to transfer detailed customer's information on a wafer in a short time at low cost.

[0387]
FIG. 77 shows a manufacturing process flow for a semiconductor integrated circuit device. In a wiring forming step 302, customer's information is transferred through a mask using light shielding patterns of resist film. At the completion of wafer (step 303), customer's information is read optically and is managed, followed by an assembling step 304 and subsequent final test (step 305). In this case, by making reference to the above customer's information automatically, a test program matching the semiconductor integrated circuit device concerned is recognized automatically and a circuit operation test is conducted. Thus, it becomes possible to perform a more accurate test.

[0388]
FIG. 78(a) is a plan view of a principal portion of a wafer 8. Customer's information is formed within a semiconductor chip 8c (region 30a) or in a cut region (region 30b) located between adjacent semiconductor chips 8c. FIGS. 78(b) and (c) illustrate customer's information patterns formed in the region 30a or 30b. FIG. 78(d) is a sectional view taken on line A-A in FIG. 78(b). In FIG. 78(b), plural conductor film patterns 10n are arranged in parallel to form a bar code. In FIG. 78(c), characters and numerals are formed of conductor film patterns 10p. The conductor film patterns 10n and 10p are formed simultaneously with the formation of wiring line patterns.

[0389]
FIG. 79 shows examples of masks used for forming the conductor film patterns 10n shown in FIG. 78(b). FIG. 79(a) illustrates a case where light shielding patterns 3t for the formation of customer's information are formed of resist film in part of the mask PM2 of the second embodiment, the light shielding patterns 3t being formed in the same step as the step of forming the light shielding patterns 3a and using the same material as that of the patterns 3a. FIG. 79(b) illustrates a case where light transmitting patterns 16s for the formation of customer's information are formed in part of the mask PM3 of the third embodiment, the light transmitting patterns 16s being formed by removing a part of a light shielding film 3u. The light shielding film 3u is formed in the same step as the step of forming the light shielding film 3b and using the same material as that of the film 3b. The light shielding patterns 16s in the light shielding film 3u are formed simultaneously with forming the light transmitting patterns 16b in the light shielding film 3b.

[0390] There may be adopted a configuration wherein simple circuit patterns are formed of light shielding patterns of resist so that binary signals of “0” and “1” can be read from predetermined bonding pads (or lead pins after packaging) formed on a semiconductor chip. With this configuration, in the step of testing a semiconductor integrated circuit device after the assembling step, the foregoing customer's information can be read electrically from the semiconductor integrated circuit device, so it becomes possible to automatically recognize a test program matching the semiconductor integrated circuit device and conduct a circuit operation test. In such a circuit configuration, “1” or “0” is allocated to a bonding pad (or lead) depending on whether there is made connection of the pad with a power terminal (high potential or low potential (0V)) formed within a semiconductor chip or whether it is the high or the low power terminal that is connected with the pad. The connecting pattern portions are formed of light shielding patterns of resist film as described in the twenty-third and twenty-fourth embodiments. By so doing it is possible to easily write or rewrite information on the mask. Of course, a simple circuit may be implemented in a semiconductor chip with use of light shielding patterns of resist film so that binary signals for the customer's information are outputted to the leads.

[0391] Although the present invention has been described above concretely on the basis of embodiments thereof, it goes without saying that the invention is not limited to those embodiments, but that various changes may be made within the scope not departing from the gist thereof.

[0392] For example, the wiring lines used in the above embodiments are of an ordinary wiring structure, but this constitutes no limitation. For example, there may be adopted what is called damascene method or dual damascene method wherein a wiring line is formed by embedding a conductor film into a trench for wiring or for hole which trench is formed in an insulating film for example.

[0393] Although in the above embodiments a semiconductor substrate constituted by a semiconductor alone is used as a semiconductor integrated circuit substrate, no limitation is placed thereon, but there may be used, for example, an SOI (Silicon On Insulator) substrate with a thin semiconductor layer formed on an insulating layer or an epitaxial substrate with an epitaxial layer formed on a semiconductor substrate.

[0394] In the case where the mark patterns are formed of a resist film in the above embodiments, a material which absorbs mark detection light (e.g., probe light in a defect inspecting apparatus (light having a longer wavelength than the wavelength of exposure light, for example, 500 nm in wavelength: information detection light)) may be incorporated in the resist film.

[0395] Although the present invention has been described above mainly about the case where it is applied to the fabrication of a semiconductor integrated circuit device which is an application field as a background of the invention, no limitation is made thereto, but the invention is also applicable to the manufacture of other electronic devices (electronic circuit devices) such as liquid crystal substrate and magnetic head.

[0396] The following is a brief description of effects obtained by typical inventions disclosed herein.

[0397] (1) According to one aspect of the present invention, predetermined patterns are transferred onto a resist film formed on a main surface of a semiconductor wafer by an exposure process using a mask, the mask having on a main surface of a mask substrate a light shielding portion formed of resist film and a light shielding portion formed of metal, whereby it becomes possible to shorten the time required for changing or correcting the mask patterns. Consequently, with use of the mask, it becomes possible to greatly shorten the period for the development or manufacture of a semiconductor integrated circuit device.

[0398] (2) According to another aspect of the present invention, a light shielding portion using metal in a peripheral portion of a main surface of a mask substrate and an opening is formed in the light shielding portion to form an information detecting pattern, whereby the information detecting ability can be improved in a mask wherein the resist film is allowed to function as a light shielding portion. Therefore, by using this mask in a manufacturing process for a semiconductor integrated circuit device, it becomes possible to improve the reliability of the semiconductor integrated circuit device.

[0399] (3) According to a further aspect of the present invention, a light shielding portion is formed using metal in a peripheral portion of a main surface of a mask substrate, wherein it becomes possible to suppress or prevent the generation of dust particles in a mask wherein resist film is allowed to function as a light shielding film. Thus, by using this mask in a manufacturing process for a semiconductor integrated circuit device, it becomes possible to improve the yield of the semiconductor integrated circuit device.

INDUSTRIAL APPLICABILITY

[0400] The present invention is effectively applicable to a semiconductor integrated circuit device manufacturing technique, especially a lithography technique in a manufacturing process for a semiconductor integrated circuit device.

Method of manufacturing integrated circuit

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