Claims
- 1. A method of manufacturing a semiconductor device, said method comprising the steps of:forming a dielectric film on an object to be treated; etching said dielectric film to form a via hole therein; forming a top dielectric film having an etch selectivity, which is different from that of said dielectric film and which is substantially equal to that of a resist, on a surface of said dielectric film, in which said via hole has been formed, so as to straddle an opening of said via hole; forming a resist of a predetermined pattern on said top dielectric film; etching said top dielectric film to form therein a groove, in which a metal is embedded for forming a wiring, so that said groove contacts at least a part of said via hole, and simultaneously ashing said resist; and continuously etching said top dielectric film for a predetermined period of time after said etching of said top dielectric film is completed, so that said top dielectric film deposited in said via hole is etched to be removed.
- 2. A method of manufacturing a semiconductor device as set forth in claim 1, wherein said dielectric film is an interlayer dielectric film in a semiconductor device having a multi-layer metallization structure.
- 3. A method of manufacturing a semiconductor device as set forth in claim 1, wherein said top dielectric film is a fluorine containing carbon film.
- 4. A method of manufacturing a semiconductor device as set forth in claim 1, wherein said top dielectric film is a coating film.
- 5. A method of manufacturing a semiconductor device, said method comprising the steps of:forming a dielectric film on an object to be treated; etching said dielectric film to form a via hole therein; forming a thin film having an etch selectivity, which is different from that of said dielectric film, on a surface of said dielectric film in which said via hole has been formed; forming a top dielectric film having an etch selectivity, which is substantially equal to those of said dielectric film and a resist, on a surface of said thin film; forming a resist of a predetermined pattern on said top dielectric film; continuously etching said top dielectric film to form therein a groove, in which a metal is embedded for forming a wiring, so that said groove contacts at least a part of said via hole, and simultaneously ashing said resist; and etching said top dielectric film for a predetermined period of time after said etching of said top dielectric film is completed, so that said top dielectric film deposited in said via hole is etched to be removed.
- 6. A method of manufacturing a semiconductor device as set forth in claim 5, wherein said top dielectric film is formed so as to straddle an opening of said via hole.
- 7. A method of manufacturing a semiconductor device as set forth in claim 5, wherein said dielectric film is an interlayer dielectric film in a semiconductor device having a multi-layer metallization structure.
- 8. A method of manufacturing a semiconductor device as set forth in claim 5, wherein said top dielectric film is a fluorine containing carbon film.
- 9. A method of manufacturing a semiconductor device as set forth in claim 5, wherein said top dielectric film is a coating film.
Priority Claims (2)
Number |
Date |
Country |
Kind |
10-264040 |
Sep 1998 |
JP |
|
10-321537 |
Oct 1998 |
JP |
|
Parent Case Info
This application is a Continuation of International Application No. PCT/JP99/04741, filed Sep. 1, 1999, which is incorporated herein by reference.
US Referenced Citations (4)
Foreign Referenced Citations (8)
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3-198327 |
Aug 1991 |
JP |
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9-246264 |
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2000208622 |
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Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/JP99/04741 |
Sep 1999 |
US |
Child |
09/665960 |
|
US |