Claims
- 1. A method of fabricating a heterojunction bipolar transistor comprising the steps of:
a) growing an carbon-doped base layer comprising gallium, indium, and arsenic from a gallium, an indium, and an arsenic source using a metalorganic chemical vapor deposition and an external carbon source over an n-doped collector layer; and b) growing an n-doped emitter layer over the base layer.
- 2. The method of claim 1, wherein the ratio of the arsenic source to the sum of the indium and gallium source is about 2.0 to about 3.5.
- 3. The method of claim 1, wherein the concentration of the carbon dopant in the base layer is about 1.5×1019 cm3 to about 5.0×1019 cm−3.
- 4. The method of claim 3, wherein the external carbon source is carbon tetrabromide or carbon tetrachloride.
- 5. The method of claim 2, wherein the base layer can be represented by the formula InxGa1−xAs, wherein x is about 0.4 to about 0.6.
- 6. The method of claim 5, wherein the base layer is grown at a temperature below about 650° C.
- 7. The method of claim 6, wherein the base layer is grown at a temperature between about 450° C. to about 600° C.
- 8. The method of claim 6, wherein the base layer is annealed in-situ.
- 9. The method of claim 6, wherein:
a) the collector is selected from InP, Inx,Ga1−x, As, InyAl1−yAs, InzGatAl1−z−t As or InwGa1−wAsuP1−u, wherein t, u, w, x′, y, and z are each, independently, less than 1; and b) the emitter is selected from InP or InyAl1−yAs, wherein y is less than 1.
- 10. The method of claim 9, wherein the collector and the emitter are InP.
- 11. The method of claim 6, wherein the composition of the base layer is linearly graded from a value for x that is larger at a surface of the base nearer the collector than a surface of the base nearer the emitter.
- 12. The method of claim 11, wherein x is linearly graded from about 0.56 to about 0.5.
- 13. The method of claim 3, wherein the base thickness is about 400 Å to about 1500 Å.
- 14. A heterojunction bipolar transistor, comprising:
a) an n-doped emitter composed of a material selected from InP or InyAl1−yAs, wherein y is less than 1; b) an n-doped collector composed of a material selected from InP,Inx,Ga1−xAs, InyAl1−yAs, InzGatAl1−z−tAs or InwGa1−wAsuP1−u, wherein t, u, w, x′, and z are each, independently, less than 1; and c) a compositionally graded p-doped base layer having a first surface in contact with the emitter and a second surface in contact with the collector and composed of a material represented by the formula InxGa1−xAs, wherein x is less than 1 and wherein x is larger at the second surface than at the first surface.
- 15. The transistor of claim 14, wherein the compositional grade of the base is linear.
- 16. The transistor of claim 15, wherein x is graded from about 0.56 to about 0.5.
- 17. The transistor of claim 16, wherein the emitter and the collector are InP.
- 18. The transistor of claim 15, wherein the base is doped with carbon at a concentration of about 1.5×1019 cm−3 to about 5.0×1019 cm−3.
RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Application No. 60/260,236, filed on Jan. 8, 2001, the entire teachings of which are incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60260236 |
Jan 2001 |
US |