Patent Application
20100140774
This application claims priority from French Application for Patent No. 08 58322 filed Dec. 5, 2008, the disclosure of which is incorporated by reference.
The present invention relates to the field of semiconductor devices.
Usually, semiconductor devices such as integrated-circuit chips have flat electrical connection pads placed with predetermined pitches. These pads are produced in a last metallization level of the integrated circuit chip. In one known case, electrical connection balls may be bonded to the pads, via approximately spherical caps, the diameter of the balls and the pitch of the pads being interdependent. In another known case, ball-shaped ends of electrical connection wires may be bonded to the pads, the diameter of the balls and the pitch of the pads also being interdependent. Furthermore, both the balls and the wires produce losses and perturbations that often are not negligible.
Embodiments herein provide a method of producing external electrical connection pads on a semiconductor device.
This method may comprise: the production of wells in an outer surface of the device which at least partially expose internal electrical connection pads of this device; and the production of electrical connection tabs having respectively branches, extending over the internal pads, external branches, extending over the outer surface of the component and over part of the perimeter of the wells, and linking branches, extending over the sidewalls of the wells.
The production of the tabs may comprise: the formation of a mask on the outer surface of the device and in the wells; the formation of holes in this mask corresponding to the tabs to be obtained; the formation of the tabs in the holes of the mask; and the removal of the mask.
The tabs may be produced by chemical deposition.
The method may comprise: the formation of a last metallization level, which includes the internal pads on an anterior surface; the formation of an outer surface layer on the last metallization level; and the formation of the wells in this outer surface layer.
The invention also provides a semiconductor device which may comprise: internal pads formed below and at some distance from an outer surface; wells provided above the internal pads and at least partially exposing the internal pads; and tabs having, respectively, internal branches extending over the internal pads, external branches extending over the outer surface and over part of the perimeter of the wells, and linking branches extending over the sidewalls of the wells.
The external branches of the tabs may protrude from said outer surface.
The external branches of the tabs may lie on one side of the wells.
The external branches of the tabs may have parallel sides.
Embodiments further provide an assembly comprising a first semiconductor device, such as the one above, and a second device having electrical connection pads, these pads being bonded to the external branches of the tabs of the semiconductor device.
A semiconductor device and method for fabricating it will now be described by way of non-limiting examples and illustrated by the accompanying drawings, in which:
Reference is made to
The semiconductor device 1 also has a surface layer 6 formed on the anterior surface 2 and covering the last metallization level 3, this surface layer 6 having an outer surface 7.
Provided in the outer surface 7 and through the surface layer 6 are wells 8 which expose, preferably partially, the internal pads 4. These wells 8 may be produced by etching through a mask. The wells 8 may have sloping sidewalls 9, for example in the form of four-sided pyramids.
The semiconductor device 1 furthermore includes flat electrical connection tabs 10 which have, respectively, internal branches 11 extending over the internal pads 4, external branches 12 extending over the outer surface 7, and linking branches 13 extending over the sidewalls 9 of the wells 4. The external branches 12 thus have outer surfaces 12a of external electrical connection, which are capable of receiving any means for electrically connecting the integrated circuit to another device.
The external branches 12 extend over part of the perimeter of the wells 8 and, in the example shown, are formed on one side of the wells 8. The linking branches 13 may extend over part of the perimeter of the wells 8 and, in the examples shown, are on the same side of the sidewalls 9 of the wells 8. The internal branches 11 may partially cover the exposed parts of these internal pads 4.
In the example shown, the branches 11, 12 and 13 constituting the tabs 10 may be aligned one after another and placed in such a way that the tabs 10 extend along directions 14 that are perpendicular to the direction 5.
The external branches 12 of the tabs 10 may be established with the pitch P of the internal pads 4.
In a variant, the external branches 12 of the tabs 10 may have parallel opposed edges 12a and 12b which are parallel to the direction 14, it being possible for the width between corresponding opposed edges 12a and 12b and for the distance between the external branches 12 of two adjacent tabs 10 to be matched to the pitch P between the internal pads 4.
For example, the width of the external branches 12 (between edges 12a and 12b) may be approximately equal to the corresponding width of the entrance of the wells 8. Thus, the external branches 12 may be included within an angle, taken at the center of the internal pads 4, of less than 90°.
For example, the corresponding width of the internal branches 11 may be smaller than the width of the external branches 12. The corresponding width of the linking branches may decrease from the external branches 12 to the internal branches 11.
As shown in
Tabs 10 are therefore obtained which have their internal branches 11 protruding from the internal pads 4, their external branches 12 protruding from the outer surface 7, and their linking branches 13 protruding from the sidewalls 9 of the wells 8.
The flat external pads 19 of the second device are placed so as to be flat on the flat protruding external branches 12 of the tabs 10 of the semiconductor device 1, it being possible for the pads 19 and the branches 12 to be of very similar and corresponding dimensions. The pads 19 may be fastened to the branches 12 by thermosonic bonding.
The semiconductor device 1 could in particular have the following variants.
The external branches 12 of the tabs 10 could extend over a larger part of the perimeter of the wells 8, for example overhanging the two adjacent sides.
The linking branches 13 of the tabs 10 could extend over a larger part of the perimeter of the wells 8, for example overhanging the two adjacent sides or going around them.
The internal branches 11 of the tabs 10 could completely cover the internal pads 4.
The wells 8 could be offset along the direction 14.
The external branches 12 of the tabs 10 could be oriented so that some of them lie along one direction and others along the opposite direction, or perpendicularly, or making other angles, depending for example on relative dispositions of the internal pads 4.
A well common to a plurality of internal pads 4 could be provided and a plurality of tabs 10 could be associated with this common well, these tabs 10 being spaced apart along the periphery of this common well.
The semiconductor device 1 that has been described above may reduce the electrical losses and perturbations in its connections with another device 18 and may reduce the pitches P between these connections, possibly then allowing the pitch density to be increased.
Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| FR 08 58322 | Dec 2008 | FR | national |
