This disclosure concerns semiconductor technology. In particular, this disclosure concerns passivation of semiconductor structures and devices.
In conventional semiconductor devices, semiconductor surfaces are often passivated by growing an oxide layer onto said surfaces. However, many methods for forming oxides result in oxide layers with considerable defect densities. This necessarily leads to existence of defect states at passivated semiconductor surfaces, inevitably deteriorating performance of conventional semiconductor devices. Moreover, conventional methods for forming oxides may rely on relatively high processing temperatures, which may deteriorate properties of semiconductor substrates and/or structures fabricated onto such substrates. In light of such challenges, it may be desirable to develop new solutions related to passivation of semiconductor structures and devices.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
According to a first aspect, a method for passivating a semiconductor structure, comprising a semiconductor layer and an oxide layer on the semiconductor layer, is provided. The method comprises providing the semiconductor structure in a vacuum chamber and, while keeping the semiconductor structure in the vacuum chamber throughout a refinement period (RP) with a duration (tRP) of at least 25 seconds (s), refining the oxide layer by maintaining temperature (T) of the semiconductor structure within a refinement temperature range (ΔT) extending from 20 degrees Celsius (° C.) to 800° C., and maintaining total pressure (ptot) in the vacuum chamber below a maximum total pressure (ptotmax) of 1×10−3 millibars (mbar).
According to a second aspect, a semiconductor structure passivated using a method in accordance with the first aspect is provided.
It is specifically to be understood that a semiconductor structure according to the second aspect may be passivated using any method according to the first aspect. Correspondingly, any semiconductor structure according to the second aspect may be passivated using a method according to the first aspect.
According to a third aspect, a vacuum processing system is provided. The vacuum processing system comprises a vacuum chamber; a pumping unit for evacuating the vacuum chamber; a pressure sensor for measuring total pressure (ptot) in the vacuum chamber; a temperature-controlled sample holder for holding a sample in the vacuum chamber; and a control unit operatively coupled with the pumping unit, the pressure sensor, and the sample holder and configured to receive sample structure data relating to a structure of a sample to be processed by the vacuum processing system and sample position data indicative of a position of the sample to be processed. In response to receiving sample structure data indicative of a sample with a semiconductor layer and an oxide layer on the semiconductor layer and sample position data indicative of the sample being arranged in the sample holder, the control unit is configured to run a process of refining the oxide layer in accordance with a process of refining the oxide layer of a method in accordance with the first aspect by operating the pumping unit, the pressure sensor, and the sample holder.
It is specifically to be understood that the vacuum processing system according to the third aspect may be specifically configured to execute any method according to the first aspect.
The present disclosure will be better understood from the following Detailed Description read in light of the accompanying drawings, wherein:
Unless specifically stated to the contrary, any drawing of the aforementioned drawings may be not drawn to scale such that any element in said drawing may be drawn with inaccurate proportions with respect to other elements in said drawing in order to emphasize certain structural aspects of the embodiment of said drawing.
In this specification, a “semiconductor” may refer to a material, such as silicon (Si), possessing a conductivity intermediate between the conductivity of conductive materials, such as metals, and the conductivity of insulating materials, such as many plastics and glasses. Further, a “semiconductor structure” may refer to a structure which may comprise all or only part of structural parts, layers, and/or other elements of a complete, operable semiconductor device, e.g., a diode; a photodiode; a solar cell; a photodetector; a radiation detector; an image sensor; a light-emitting diode; a laser diode; a capacitor; a transistor; or an integrated circuit, such as a microprocessor, a microcontroller, a memory chip, a programmable logic device, a radio frequency (RF) circuit, or a three-dimensional integrated circuit; or a memristor. In the case of forming only a part of such component, element, or device, the term “structure” may be considered as a structure “for”, or a building block of, such component, element, or device. A semiconductor structure may generally comprise non-semiconducting materials, such as conductors and/or insulators, in addition to semiconductor materials.
Throughout this disclosure, “passivation” may refer to a process, whereby a structure of device becomes less sensitive to its surroundings during use. Passivation may involve the formation of one or more protective outer layers, which may or may not be implemented as oxide layers. Additionally or alternatively, passivation may refer to surface passivation, i.e., a process, whereby a surface of semiconductor layer may be rendered more inert.
Herein, a “layer” may refer to a generally sheet-shaped element arranged on a surface or a body. Additionally or alternatively, a layer may refer to one of a series of super-imposed, overlaid, or stacked generally sheet-shaped elements. Generally, the extent of a layer may or may not be defined by a boundary between different materials or material compositions. However, a “semiconductor layer” may refer to a layer formed of a semiconductor material, and an “oxide layer” may refer to a layer formed of an oxide material.
In the embodiment of
In this specification, a “process” may refer to a series of one or more steps, leading to an end result. As such, a process may be a single-step or a multi-step process. Additionally, a process may be divisible to a plurality of sub-processes, wherein individual sub-processes of such plurality of sub-processes may or may not share common steps. Herein, a “step” may refer to a measure taken in order to achieve a pre-defined result.
Throughout this disclosure, a “vacuum chamber” may refer to an enclosure configured to withstand evacuation by a vacuum pump. Additionally or alternatively, a vacuum chamber may refer to an enclosure suitable for maintaining a low-pressure environment brought about by such evacuation, i.e., a vacuum, in said enclosure.
Further, “providing” may refer to arranging available the element or item at issue. It may comprise forming, producing, or manufacturing the element or part at issue at least partly. Additionally or alternatively, providing may comprise arranging available an element or part which is ready-made or produced or manufactured beforehand. For example, a process of providing the semiconductor structure may or may not comprise one or more steps taken in order to form a semiconductor structure.
Consequently, in the embodiment, of
The chemical vapor deposition step 111 of the embodiment of
The thermal oxidation step 112 of the embodiment of
In the embodiment of
In the embodiment of
Throughout this specification, “degree of crystallinity” may refer to a fraction of crystalline phase(s) in a material. Herein, the degree of crystallinity of an oxide layer may refer to a value determinable based on X-ray diffraction measurements.
In the embodiment of
Generally, refining the oxide layer of a semiconductor structure by maintaining T of the semiconductor structure within ΔT, extending from 20° C., 800° C., and maintaining ptot in a vacuum chamber below ptotmax of 1×10−3 mbar, while keeping the semiconductor structure in the vacuum chamber throughout a RP with a tRP of at least 25 s, may enable passivating the semiconductor structure. Without necessarily limiting the present disclosure to any specific underlying physical mechanism(s), such passivation may result from lowered density of defect states at an interface between a semiconductor layer and an oxide layer, brought about by an increase in the degree of crystallinity of the oxide layer. Again, without necessarily limiting the present disclosure to any specific underlying physical mechanism(s), such passivation may additionally or alternatively result from re-arrangement of hydrogen atoms inside the semiconductor layer due to diffusion.
In the embodiment of
In the embodiment of
Generally, a process of refining the oxide layer may comprise supplying one or more gases other than O2 into a vacuum chamber during or throughout a RP, in addition or as an alternative to supplying O2. For example, in some embodiments, a process of refining the oxide layer may comprise supplying one or more of molecular hydrogen (H2), hydrogen peroxide (H2O2), ammonia (NH5), molecular nitrogen (N2), nitrogen dioxide (NO2), ethanol (C2H5OH), and noble gas(es), e.g., helium (He) or Argon (Ar). In embodiments, wherein a process of refining the oxide layer comprises supplying a gas other than O2 into a vacuum chamber during or throughout a RP, the process of refining the oxide layer may or may not comprise maintaining a partial pressure of the gas above a minimum partial pressure of the gas with a value corresponding to some value of po
In an embodiment, a method for passivating a semiconductor structure comprises processes corresponding to the processes 110, 120, 130, 131, 132, 133, and 134 of the method 100 of the embodiment of
Generally, steps of a method for passivating a semiconductor structure implementing processes corresponding to any of the processes 110, 120, 130, 131, 132, 133, and 134 of the method 100 of the embodiment of
Above, mainly process and parameter issues of methods for passivating semiconductor structures are discussed. In the following, more emphasis will lie on structural features of semiconductor structures before and after being passivated using a method in accordance with any method disclosed within this specification. What is said above about the ways of implementation, definitions, details, and advantages related to the process and parameter issues apply, mutatis mutandis, to the semiconductor structures discussed below. The same applies vice versa.
The semiconductor structure 200 of the embodiment of
In the embodiment of
Throughout this specification, a “capping layer” may refer to any layer arranged on an oxide layer of a semiconductor structure such that the oxide layer is arranged at a distance from a periphery of the semiconductor structure.
Further, a “periphery” of an object may refer to outermost boundaries of the object. In practice, such outermost boundaries may be considered to extend a nanoscopic distance, for example, at most 20 nanometers, nm, or at most 10 nm, or at most 5 nm, or at most 2 nm, towards a center of an object, from its outermost atoms.
Prior to being subjected to a process of refining the oxide layer 220, the oxide layer 220 has a first degree of crystallinity (w1c). In the embodiment of
After being subjected to a process of refining the oxide layer 220, the oxide layer 220 has a second degree of crystallinity (w2c), which nay be greater than w1c. In the embodiment of
The oxide layer 220 of the embodiment has a thickness (t), measured following a process of refining the oxide layer and perpendicular to an interface between the semiconductor layer 210 and the oxide layer 220. In the embodiment of
The semiconductor layer 210 of the embodiment of
In the embodiment of
Herein, a “main constituent element” of a layer may refer to a chemical element of an atomic nucleus of a repeating structural motif or a lattice of material in the layer.
The first main constituent element of the embodiment of
The semiconductor layer 210 of the embodiment of
The semiconductor layer 210 of the embodiment of
The oxide layer 220 of the embodiment of
In the embodiment of
In the following, a number of examples are detailed.
In a first example, a silicon dioxide (SiO2) layer was grown by atomic layer deposition onto an unpatterned 4-inch Si sample wafer and a corresponding reference wafer.
The sample wafer was then placed into the cylindrical stainless-steel vacuum chamber of an ultra-high vacuum (UHV) system. In the system, the vacuum chamber was connected to a turbomolecular pump with a rotary backing pump, and an all-metal gas regulating valve was connected to the vacuum chamber for adjusting the partial pressure of oxygen (po
Inside the vacuum chamber, the sample wafer was mounted onto a cradle formed of an austenitic nickel-chromium-based superalloy material without the use of plates, bolts, or clams to fix the wafer onto the cradle. When mounted on the cradle, the temperature of the wafer could be controlled by a heating system, comprising a heating element as well as a combined temperature controller-power supply device connected to a type K thermocouple.
While the sample wafer was kept in the vacuum chamber, the total pressure (ptot) in the vacuum chamber was maintained below a maximum total pressure (ptotmax) of approximately 5×10−6 mbar, the temperature of the wafer was maintained at 350° C., and the partial pressure of oxygen (po
During the refinement period, reflection high-energy electron diffraction (RHEED) measurements were conducted to study the morphology of the SiO2 layer. Results of the RHEED measurements indicated that, the degree of crystallinity of the SiO2 layer increased during the treatment of the sample wafer in the vacuum chamber.
Following the treatment of the sample wafer in the vacuum chamber, carrier lifetime measurements were conducted on both the sample wafer and the reference wafer using a Semilab PV-2000A lifetime scanner tool. The results of the carrier lifetime measurements indicated that the treatment of the sample wafer in the vacuum chamber resulted in an increase in average carrier lifetime from 2.12 milliseconds (ms) to 2.90 ms.
In a second example, a Si photodiode sample with alumina-coated black silicon (b-Si) surface featuring and a size of 6 mm×6 mm was diced from a Si wafer after completion of wafer-scale device processing. The dicing step introduced scratches to the sidewalls of the photodiode sample and exposed the sidewalls to the ambient such that native oxide formed to cover the sidewalls.
The photodiode sample was then placed into a temperature-controlled sample holder of a vacuum chamber of a UHV system. While the photodiode sample wafer was kept in the vacuum chamber, the total pressure (ptot) in the vacuum chamber was maintained below a maximum total pressure (ptotmax) of 2×10−4 mbar, the temperature of the wafer was maintained at 400° C., and the partial pressure of oxygen (po
Leakage current measurements were carried out for the photodiode sample before and after the vacuum treatment using an LCR precision meter at a controlled temperature without illumination. According to the results of the leakage current measurements, the vacuum treatment resulted in decreased leakage currents for the photodiode sample. Such results may be indicative of the vacuum treatment decreasing the density of defect-induced gap levels in the proximity of the sidewalls. Such effect may be caused by a reformation of the structure of the oxide layers on the sidewalls.
In a third example, a photodiode sample identical to the photodiode sample of the second sample was prepared and placed into a temperature-controlled sample holder of a vacuum chamber of a UHV system. While the photodiode sample wafer was kept in the vacuum chamber, the total pressure (ptot) in the vacuum chamber was maintained below a maximum total pressure (ptotmax) of 1×10−5 mbar, the temperature of the wafer was maintained at 200° C., and the partial pressure of oxygen (po
Similarly to the second example, leakage current measurements were carried cut for the photodiode sample before and after the vacuum treatment. According to the results of the leakage current measurements, the vacuum treatment resulted in decreased leakage currents for the photodiode sample. Such results may be indicative of the vacuum treatment decreasing the density of defect-induced gap levels in the proximity of the sidewalls. Such effect may be caused by a reformation of the structure of the oxide layers on the sidewalls.
It is to be understood that the embodiments of the first and second aspects described above may be used in combination with each other. Several of the embodiments may be combined together to form a further embodiment of the first aspect or the second aspect.
Above, mainly process and parameter issues of methods for passivating semiconductor structures and structural features of semiconductor structures before and after being passivated using such methods are discussed. In the following, more emphasis will lie on features of vacuum processing systems configured to realize methods in accordance with any method disclosed within this specification. What is said above about the ways of implementation, definitions, details, and advantages related to the method and semiconductor structure aspects apply, mutatis mutandis, to the vacuum processing systems discussed below. The same applies vice versa.
In the embodiment of
In the embodiment of
Herein, a “pumping unit” may refer to apparatus e.g., vacuum pumps and electronics, as well as interconnect ion elements, e.g., valves, sealing elements, and gas lines, necessary or beneficial for evacuating a vacuum chamber.
In the embodiment of
Herein, a “pressure sensor” may refer to any device for measuring (static) pressure of gases in a vacuum chamber. Generally, selection of a suitable type of commercially available pressure sensor for any given application may be considered standard practice for the skilled person. For example, in oxygen-containing environments, a cold cathode pressure gauge may foe commonly used to measure pressures above approximately 1×10−9 mbar.
In the embodiment of
Herein, a “temperature-controlled sample holder” may refer to a part of a vacuum processing system specifically configured for holding as well as heating, and, optionally, cooling a sample in a vacuum chamber, when the vacuum processing system is used. Such sample holder may comprise, for example, electrical connections for conducting electrical measurements on a sample inside a vacuum chamber; and/or an integrated quartz balance for measuring a mass of a sample; and/or sample heating element(s), which may be based, for example, on resistive, electron bombardment, and/or direct heating of a sample; and/or sample cooling element(s), which may utilize, for example, cryogenic cooling. Generally, selection of a suitable type of commercially available sample holder for any given application may be considered standard practice for the skilled person.
In the embodiment of
In this specification, a “control unit” may refer to a device, e.g., an electronic device, having at least one specified function related to determining and/or influencing an operational condition, status, or parameter related to another device, unit, or element. A control unit, may or may not form a part of a multifunctional control system.
Further, a control unit being “operatively coupled” with a device, unit, or element may refer to the control unit having at least one specified function related to determining and/or influencing an operational condition, status, or parameter related to said device, unit, or element.
The control unit 350 of the embodiment of
A control unit being “configured to” perform a process may refer to capability of and suitability of said control unit for such process. This may be achieved in various ways. For example, a control unit may comprise at least one processor and at least one memory coupled to the at least one processor, the memory storing program code instructions which, when executed on said at least one processor, cause the processor to perform the process(es) at issue.
Additionally or alternatively, any functionally described features of a control unit may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, illustrative types of suitable hardware logic components include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc. A control unit may generally be operated in accordance with any appropriate principles and by means of any appropriate circuitry and/or signals known in the art.
Herein, “sample structure data” may refer to any data relating to a structure of a sample to be processed by a vacuum processing system. In some embodiments, sample structure data may comprise, for example, a partial or complete fabrication recipe of a sample. In some embodiments, sample structure data may comprise recipe data used exclusively for a particular sample type.
Throughout this specification, “sample position data” may refer to any data indicative of a position of the sample to be processed by a vacuum processing system. In some embodiments, sample structure data may comprise, for example, a start signal, indicating that processing of a sample may be initiated. Such start signal may be sent, for example, in response to automatically sensing that a sample is arranged into a sample holder or in response to user input.
The control unit 350 of the embodiment of
The vacuum chamber 310 of the embodiment of
Herein, a “pressure regulator” of a gas inlet may refer to a control valve suitable for or configured to set, e.g., reduce, a pressure of gas supplied via the gas inlet to a desired value or within a desired pressure range.
In the embodiment of
The process of refining the oxide layer of the embodiment of
Generally, a process of refining the oxide layer run by a control unit may comprise supplying one or more gases other than O2 into a vacuum chamber during or throughout a RP, in addition or as an alternative to supplying O2. For example in some embodiments such process of refining the oxide layer nay comprise supplying one or more of molecular hydrogen (H2), hydrogen peroxide (H2O2), ammonia (NH3), molecular nitrogen (N2), nitrogen dioxide (NO2), ethanol (C2H5OH), and noble gas(es), e.g., helium (He) or Argon (Ar). In embodiments, wherein a process of refining the oxide layer run by a control unit of a vacuum processing system comprises supplying a gas other than O2 into a vacuum chamber during or throughout a RP, the vacuum processing system may comprise any element(s) required for supplying the gas, for example, a gas inlet with a pressure regulator and a gas line for supplying the gas into the vacuum chamber via the gas inlet. In said embodiments, the control unit may be configured to run the process of refining the oxide layer by operating a pumping unit, a pressure sensor, a sample holder, and the pressure regulator.
In the embodiment of
Herein, a “user interface unit” may refer to a unit configured to provide a user interface for operating a vacuum processing system. Generally, a user interface unit may comprise any elements and/or devices necessary or beneficial for providing such user interface. A user interface unit may comprise, for example, an input device, e.g., a button, a switch, a pedal, a keyboard, a mouse, a track-ball, or a lever, and/or a display device, which may generally be based on any known display technologies. In some embodiments, a user interface unit may comprise a touchscreen, usable as both an input device and a display device. In some embodiments, user interface unit may be implemented as software, for example, as a computer program.
It is to be understood that the embodiments of the third aspect described above may be used in combination with each other. Several of the embodiments may be combined together to form a further embodiment.
It is obvious to a person skilled in the art that with the advancement of technology, the basic idea of the invention may be implemented in various ways. The invention and its embodiments are thus not limited to the examples described above, instead they may vary within the scope of the claims.
It will be understood that any benefits and advantages described within this specification may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.
The term “comprising” is used in this specification to mean including the feature(s) or act(s) followed thereafter, without excluding the presence of one or more additional features or acts. It will further be understood that reference to ‘an’ item refers to one or more of those items.
Number | Date | Country | Kind |
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20205316 | Mar 2020 | FI | national |
Filing Document | Filing Date | Country | Kind |
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PCT/FI2021/050220 | 3/29/2021 | WO |