Patent Application
20250015167
The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
As merely one example, fabricating transistors having a low density of interface traps and oxide traps is vital to providing high-performance devices. However, with the continued scaling of IC dimensions and the introduction of multi-gate devices (e.g., such as fin field-effect transistors (FinFETs)), the challenges have increased. One particular challenge is noise, such as flicker (1/f) noise, which may be caused by interface and oxide traps, and which can degrade device performance. Moreover, given the increased proportion of transistor channel-to-gate dielectric interface surface area for multi-gate devices, the occurrence of charge trapping of carriers at the channel-to-gate dielectric interface may only increase.
Thus, existing techniques have not proved entirely satisfactory in all respects.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
It is also noted that the present disclosure presents embodiments in the form of a method and related structure which may be employed in any of a variety of device types. For example, embodiments of the present disclosure may be used in the fabrication of planar bulk metal-oxide-semiconductor field-effect transistors (MOSFETs), multi-gate transistors (planar or vertical) such as FinFET devices, gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices, as well as strained-semiconductor devices, silicon-on-insulator (SOI) devices, partially-depleted SOI devices, fully-depleted SOI devices, or other devices as known in the art. In addition, embodiments disclosed herein may be employed in the formation of P-type and/or N-type devices. One of ordinary skill may recognize other embodiments of semiconductor devices that may benefit from aspects of the present disclosure.
In advanced semiconductor processing, fabricating transistors having a low density of interface traps and oxide traps is vital to providing high-performance devices. However, with the continued scaling of IC dimensions and the introduction of multi-gate devices (e.g., such as FinFETs), the challenges have increased. One particular challenge is noise, such as flicker (1/f) noise, which may be caused by interface and oxide traps, and which can degrade device performance. Moreover, given the increased proportion of transistor channel-to-gate dielectric interface surface area for multi-gate devices, the occurrence of charge trapping of carriers at the channel-to-gate dielectric interface may only increase. As a result, existing techniques have not proved entirely satisfactory in all respects.
Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include methods and structures for reducing noise (e.g., such as flicker noise) for advanced transistor structures. Generally, the disclosed embodiments may effectively reduce flicker noise by improving (reducing) the density of interface traps and oxide traps, as well as by modulating a transistor channel current path (e.g., a current path between a source and a drain of the transistor) such that the current path is a distance (e.g., greater than about 2 Angstroms) away from the transistor channel-to-gate dielectric interface, thereby minimizing the occurrence of charge trapping at the channel-to-gate dielectric interface. In some embodiments, the reduction of traps may be accomplished by use of a post-deposition anneal (PDA) process (e.g., performed after formation of the gate dielectric), where the PDA process is performed at a PDA soak temperature of between about 80-150 degrees Celsius in a nitrogen (N2) ambient. The PDA process may have the effect of filling oxide vacancies, thereby reducing oxide trapping centers. In some cases, the reduction of traps may be accomplished by use of a TiN layer (e.g., such as a TiN capping layer) to reduce oxygen absorption into the gate dielectric and reduce oxide defects.
In various embodiments, the current path may be moved a distance away from the transistor channel-to-gate dielectric interface by doping the transistor channel (e.g., semiconductor layer) near the channel-to-gate dielectric interface. In an example, the transistor channel may be doped using an ion implantation process, a diffusion doping process, an ALD deposition of a doped layer followed by a drive-in anneal process, a plasma doping (PLAD) process, or using another appropriate doping process. In particular, the doping process may be used to introduce a dopant species (e.g., such as an N-type dopant species, a P-type dopant species, positively charged ions, or negatively charged ions) in the semiconductor channel layer near the channel-to-gate dielectric interface that is of the same type as the transistor within which it is being introduced (e.g., an N-type dopant species or negatively charged ions for an N-type transistor and a P-type dopant species or positively charged ions for a P-type transistor). As a result, in some examples, the transistor may operate as a buried-channel transistor, where during operation current in the transistor will flow in a bulk portion of the transistor (e.g., within a bulk portion of a fin structure of a FinFET device) between a source and a drain, and away from the channel-to-gate dielectric interface. In some embodiments, when the dopant species includes negatively charged ions introduced into the gate dielectric near the channel-to-gate dielectric interface of an N-type transistor, electrons flowing in the transistor channel may be repelled from the channel-to-gate dielectric interface by the negatively charged ions. In another example, when the dopant species includes positively charged ions introduced into the gate dielectric near the channel-to-gate dielectric interface of a P-type transistor, holes flowing in the transistor channel may be repelled from the channel-to-gate dielectric interface by the positively charged ions. Regardless of the method by which the current path is moved a distance away from the transistor channel-to-gate dielectric interface, charge trapping of carriers at the channel-to-gate dielectric interface, as well as the associated flicker noise, can be reduced. Other embodiments and advantages will be evident to those skilled in the art upon reading the present disclosure.
Referring now to the example of
The gate stack 104 includes a gate dielectric 106 and a gate electrode 108 disposed on the gate dielectric 130. In some embodiments, the gate dielectric 106 may include an interfacial layer such as silicon oxide layer (SiO2) or silicon oxynitride (SiON), where such interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. In some examples, the gate dielectric 106 includes a high-k dielectric layer such as hafnium oxide (HfO2). Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2. ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. High-K gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). In still other embodiments, the gate dielectric 106 may include silicon dioxide or other suitable dielectric. The gate dielectric 106 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. In some embodiments, the gate electrode 108 may be deposited as part of a gate first or gate last (e.g., replacement gate) process. In various embodiments, the gate electrode 108 includes a conductive layer such as W. Ti, TiN, TiAl, TiAlN, Ta, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, CoSi, Ni, NiSi, combinations thereof, and/or other suitable compositions. In some examples, the gate electrode 108 may include a first metal material for an N-type transistor and a second metal material for a P-type transistor. Thus, the transistor 100 may include a dual work-function metal gate configuration. For example, the first metal material (e.g., for N-type devices) may include metals having a work function substantially aligned with a work function of the substrate conduction band, or at least substantially aligned with a work function of the conduction band of a channel region 114 of the transistor 100. Similarly, the second metal material (e.g., for P-type devices) may include metals having a work function substantially aligned with a work function of the substrate valence band, or at least substantially aligned with a work function of the valence band of the channel region 114 of the transistor 100. Thus, the gate electrode 104 may provide a gate electrode for the transistor 100, including both N-type and P-type devices. In some embodiments, the gate electrode 108 may alternately or additionally include a polysilicon layer. In various examples, the gate electrode 108 may be formed using PVD, CVD, electron beam (e-beam) evaporation, and/or other suitable process. In some embodiments, sidewall spacers are formed on sidewalls of the gate stack 104. Such sidewall spacers may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.
The transistor 100 further includes a source region 110 and a drain region 112 each formed within the semiconductor substrate 102, adjacent to and on either side of the gate stack 104. In some embodiments, the source and drain regions 110, 112 include diffused source/drain regions, ion implanted source/drain regions, epitaxially grown regions, or a combination thereof. The channel region 114 of the transistor 100 is defined as the region between the source and drain regions 110, 112 under the gate dielectric 106, and within the semiconductor substrate 102. The channel region 114 has an associated channel length “L” and an associated channel width “W”. In operation, an electric current (e.g., a transistor drive current) flows between the source and drain regions 110, 112 through the channel region 114. The amount of drive current developed for a given bias voltage (e.g., applied to the gate electrode 108 or between the source and drain regions 110, 112) is a function of, among others, the mobility of the material used to form the channel region 114. In some examples, the channel region 114 includes silicon (Si) and/or a high-mobility material such as germanium, which may be epitaxially grown, as well as any of the plurality of compound semiconductors or alloy semiconductors as known in the art. High-mobility materials include those materials with electron and/or hole mobility greater than silicon (Si), which has an intrinsic electron mobility at room temperature (300 K) of around 1350 cm2/V-s and an intrinsic hole mobility at room temperature (300 K) of around 480 cm2/V-s.
Referring to
The fin-element 154, like the substrate 152, may include one or more epitaxially-grown layers, and may comprise silicon or another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP; or combinations thereof. The fin elements 154 may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (resist) overlying the substrate (e.g., on a silicon layer), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, pattering the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the substrate while an etch process forms recesses into the silicon layer, thereby leaving an extending fin 154. The recesses may be etched using a dry etch (e.g., chemical oxide removal), a wet etch, and/or other suitable processes. Numerous other embodiments of methods to form the fins 154 on the substrate 152 may also be used. It is also noted that when the multi-gate device 150 includes a FinFET device, the fins 154 may include a continuous fin of substantially uniform composition, and when the multi-gate device 150 includes a GAA device, the fins 154 may include a plurality of channels disposed in a plurality of semiconductor channel layers interposed by portions of the gate structure 158.
Each of the plurality of fins 154 also include a source region 155 and a drain region 157 where the source/drain regions 155, 157 are formed in, on, and/or surrounding the fin 154. The source/drain regions 155, 157 may be epitaxially grown over the fins 154. In addition, a channel region (or multiple channel regions) of a transistor is disposed within the fin 154, underlying the gate structure 158, along a plane substantially parallel to a plane defined by section AA′ of
The isolation regions 156 may be shallow trench isolation (STI) features. Alternatively, a field oxide, a LOCOS feature, and/or other suitable isolation features may be implemented on and/or within the substrate 152. The isolation regions 156 may be composed of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable material known in the art. In an embodiment, the isolation regions 156 are STI features and are formed by etching trenches in the substrate 152. The trenches may then be filled with isolating material, followed by a chemical mechanical polishing (CMP) process. However, other embodiments are possible. In some embodiments, the isolation regions 156 may include a multi-layer structure, for example, having one or more liner layers.
The gate structure 158 includes a gate stack having an interfacial layer 160 formed over the channel region of the fin 154, a gate dielectric layer 162 formed over the interfacial layer 160, and a metal layer 164 formed over the gate dielectric layer 162. In various embodiments, the interfacial layer 160 is substantially the same as the interfacial layer described as part of the gate dielectric 106. In some embodiments, the gate dielectric layer 162 is substantially the same as the gate dielectric 106 and may include high-k dielectrics similar to that used for the gate dielectric 106. Similarly, in various embodiments, the metal layer 164 is substantially the same as the gate electrode 108, described above. In some embodiments, sidewall spacers are formed on sidewalls of the gate structure 158. The sidewall spacers may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.
Each of the transistor 100 and multi-gate device 150 may include one or more embodiments of the present disclosure, which are described in more detail below. However, for the sake of clarity, the discussion that follows is primarily directed to multi-gate devices, such as the multi-gate device 150. As used herein, the term “multi-gate device” is used to describe a device (e.g., a semiconductor transistor) that has at least some gate material disposed on multiple sides of at least one channel of the device. For instance, the multi-gate device may include a FinFET device having gate material disposed on at least three sides of a transistor channel, a GAA device having gate material disposed on at least four sides of a transistor channel, or a FinFET device formed in combination with a GAA device. When the multi-gate device includes a GAA device, the channel regions may be referred to as “nanowires,” which may include channel regions of various geometries (e.g., cylindrical, bar-shaped) and various dimensions.
Referring to
The method 200 begins at block 202 where a partially fabricated multi-gate device is provided. Referring to the example of
As shown in
It is noted that while seven (7) layers of the epitaxial layer 306 and six (6) layers of the epitaxial layer 308 are illustrated in
In some embodiments, the epitaxial layer 306 has a thickness range of about 4-8 nanometers (nm). In some embodiments, the epitaxial layers 306 may be substantially uniform in thickness. However, in some cases, a topmost layer of the epitaxial layers 306 may be thicker than the remaining epitaxial layers 306, for example, to mitigate layer loss that may occur to the topmost layer of the epitaxial layers 306 during a subsequent CMP process. In some embodiments, the epitaxial layer 308 has a thickness range of about 5-8 nm. In some embodiments, the epitaxial layers 308 are substantially uniform in thickness. As described in more detail below, the epitaxial layer 308 may serve as channel region(s) for the subsequently formed GAA device 300A and its thickness chosen based on device performance considerations. The epitaxial layer 306 may serve to define a gap distance between adjacent channel region(s) for the subsequently formed multi-gate device and its thickness chosen based on device performance considerations.
By way of example, epitaxial growth of the epitaxial layers 306, 308 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers such as, the layers 308 include the same material as the substrate 302. In some embodiments, the epitaxially grown layers 306, 308 include a different material than the substrate 302. As stated above, in at least some examples, the epitaxial layer 306 includes an epitaxially grown silicon germanium (SiGe) layer and the epitaxial layer 308 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers 306, 308 may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers 306, 308 may be chosen based on providing differing oxidation, etch rates, and/or etch selectivity properties. In various embodiments, the epitaxial layers 306, 308 are initially substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3 to about 1×1017 cm−3), where for example, no intentional doping is performed during the epitaxial growth process. However, as discussed below and in accordance with embodiments of the present disclosure, portions of the epitaxial layers 308 near a surface of the epitaxial layers 308 (e.g., at a channel-to-gate dielectric interface) may be intentionally doped so that the current path (e.g., between source and drain) is moved a distance (e.g., greater than about 2 Angstroms) away from the transistor channel-to-gate dielectric interface. To be sure, in some examples, the portions of the epitaxial layers 308 near the surface of the epitaxial layers 308 may be in situ doped during the epitaxial growth of the epitaxial layers 308.
As shown in
Similar to the epitaxial layers 306, 308, epitaxial growth of the epitaxial layer 402 may be performed by an MBE process, an MOCVD process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxial layer 402 may include the same material as the substrate 302. In some embodiments, the epitaxial layer 402 may include a different material than the substrate 302. As stated above, in at least some examples, the epitaxial layer 402 includes an epitaxially grown silicon or silicon germanium (SiGe) layer. Alternatively, in some embodiments, the epitaxial layer 402 may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP. AlInAs, AlGaAs, InGaAs, GalnP, and/or GaInAsP, or combinations thereof. In various embodiments, the epitaxial layer 402 is initially substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3 to about 1×1017 cm−3), where for example, no intentional doping is performed during the epitaxial growth process. However, as discussed below and in accordance with embodiments of the present disclosure, portions of the epitaxial layer 402 near a surface of the epitaxial layer 402 (e.g., at a channel-to-gate dielectric interface) may be intentionally doped so that the current path (e.g., between source and drain) is moved a distance (e.g., greater than about 2 Angstroms) away from the transistor channel-to-gate dielectric interface.
In various embodiments, the fins 602, 604 may be fabricated using suitable processes including photolithography and etch processes, and in a manner substantially similar to that described above with reference to the fins 154 of the multi-gate device 150. Upon formation of the fins 602, 604, trenches may be formed adjacent to and interposing the fins 602, 604. In various embodiments, the trenches may be filled with a dielectric material, which may then be planarized and recessed, to form shallow trench isolation features 602. In some embodiments, the dielectric layer used to fill the trenches may include SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials known in the art. In various examples, the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process. In some embodiments, the devices 300A, 300B may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and thus the STI features 602) may include a multi-layer structure, for example, having one or more liner layers.
As shown in the example of
The method 200 then proceeds to block 204 where a dummy gate structure is formed. While the present discussion is directed to a replacement gate (gate-last) process whereby a dummy gate structure is formed and subsequently replaced, other configurations (e.g., such as gate-first) may be possible. With reference to
In some embodiments, prior to forming the gate stacks 702, 704, a dielectric layer 706 may be optionally formed. In some embodiments, the dielectric layer 706 is deposited over the substrate 302 and over the fins 602, 604, including within trenches between adjacent fins 602, 604. In some embodiments, the dielectric layer 706 may include SiO2, silicon nitride, a high-K dielectric material or other suitable material. In various examples, the dielectric layer 706 may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. By way of example, the dielectric layer 706 may be used to prevent damage to the fin elements 602, 604 by subsequent processing (e.g., subsequent formation of the dummy gate).
In some embodiments using a gate-last process, the gate stacks 702, 704 are dummy gate stacks and will be replaced by the final gate stack at a subsequent processing stage of the GAA device 300A and the FinFET device 300B. In particular, the gate stacks 702, 704 may be replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG). In some embodiments, the gate stacks 702, 704 are formed over the substrate 302 and are at least partially disposed over the fin elements 602, 604. Additionally, in various embodiments, the gate stacks 702, 704 may be formed over the dielectric layer 706, which was optionally deposited as described above prior to formation of the gate stacks 702, 704. The portion of the fin elements 602, 604 underlying the gate stacks 702, 704 may be referred to as the channel region. The gate stacks 702. 704 may also define a source/drain region of the fins 602, 604, for example, the regions of the fins 602, 604 adjacent to and on opposing sides of the channel region.
In some embodiments, the gate stacks 702, 704 include a dielectric layer and an electrode layer, both of which are represented by element 707. The gate stacks 702, 704 may also include one or more hard mask layers 708, 710. In some embodiments, the hard mask layer 708 may include an oxide layer, and the hard mask layer 710 may include a nitride layer. In some embodiments, the gate stacks 702, 704 are formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. In some examples, the layer deposition process includes CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or a combination thereof. In forming the gate stack for example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods.
In some embodiments, the dielectric layer of the gate stacks 702, 704 includes silicon oxide. Alternatively, or additionally, the dielectric layer of the gate stacks 702, 704 may include silicon nitride, a high-K dielectric material or other suitable material. In some embodiments, the electrode layer of the gate stacks 702, 704 may include polycrystalline silicon (polysilicon). In some embodiments, the oxide of the hard mask layer 708 includes a pad oxide layer that may include SiO2. In some embodiments, the nitride of the hard mask layer 710 includes a pad nitride layer that may include Si3N4, silicon oxynitride or silicon carbide.
The method 200 then proceeds to block 206 where a first channel doping process is performed. With reference to
With reference first to
In various embodiments, the dopant species used to form the doped layer 505 is of the same type (polarity) as the transistor within which it is being introduced (e.g., an N-type dopant species or negatively charged ions for an N-type transistor and a P-type dopant species or positively charged ions for a P-type transistor). Stated another way, the dopant species used to form the doped layer 505 may be of the same type (polarity) as a source/drain doping species of the device within which it is being introduced (e.g., an N-type dopant species or negatively charged ions for a device having an N-type source/drain and a P-type dopant species or positively charged ions for a device having a P-type source/drain). While the dopant species may be of the same type (polarity), it is noted that the dopant concentration of the doped layer 505 will be less than the dopant concentration of the source/drain. By way of example, if the FinFET device 300B is an N-type device, the ion implantation process 502 (and the resulting doped layer 505) may include an N-type dopant species (e.g., a column V element such as phosphorous, arsenic, antimony, and/or a negatively charged ion such as a negatively charged phosphorous ion). In another example, if the FinFET device 300B is a P-type device, the ion implantation process 502 (and the resulting doped layer 505) may include a P-type dopant species (e.g., a column III element such as boron and/or a positively charged ion such as a positively charged boron ion). In such a case, the FinFET device 300B may operate similar to a buried-channel transistor, where during operation current in the FinFET device 300B flows primarily in a bulk portion 507 of the epitaxial layer 402 of FinFET device 300B between a source and a drain, and away from the channel-to-gate dielectric interface. In some embodiments, after formation of the doped layer 505, the FinFET device 300B May be subject to a high thermal budget process (anneal) to remove defects and activate dopants (i.e., to place dopants into substitutional sites).
With reference now to
The method 200 then proceeds to block 208 where spacer elements are formed. With reference to
In some embodiments, the deposition of the spacer material layer is followed by an etching back (e.g., anisotropically) of the dielectric spacer material. Referring to the example of
The method 200 then proceeds to block 210 where source/drain features are formed. Initially, in an embodiment of block 210, after formation of the gate stacks 702, 704 and/or the sidewall spacers 802, the dielectric layer 706 (
Referring again to the example of
The method 200 then proceeds to block 212 where an inter-layer dielectric (ILD) layer is formed. Referring to the example of
In some examples, after depositing the ILD (and/or CESL or other dielectric layers), a planarization process may be performed to expose a top surface of the gate stacks 702, 704 of the GAA device 300A and the FinFET device 300B. For example, a planarization process includes a CMP process which removes portions of the ILD layer 902 (and CESL layer, if present) overlying the gate stacks 702, 704 and planarizes a top surface of each of the GAA device 300A and the FinFET device 300B. In addition, the CMP process may remove the hard mask layers 708, 710 overlying the gate stacks 702, 704 to expose the underlying electrode layer, such as a polysilicon electrode layer, of the dummy gate.
The method 200 proceeds to block 214 where the dummy gate (see block 204) is removed and a channel layer release process is performed if needed (e.g., as needed for fabrication of the GAA device 300A). Referring to the example of
In some embodiments, an electrode layer (e.g., such as a polysilicon gate electrode) of the dummy gate stacks 702, 704 over each of the GAA device 300A and the FinFET device 300B may initially be removed, by suitable etching processes. After removal of the dummy electrode layer, an etching process is performed to etch the dummy dielectric layer of the dummy gate stacks 702, 704 over each of the GAA device 300A and the FinFET device 300B. Stated another way, removal of the dummy gate in block 214 may include removal of the element 707 (which includes the dummy dielectric layer and electrode layer) from the gate stacks 702, 704 of each of the GAA device 300A and the FinFET device 300B. In some examples, the etching processes may include a wet etch, a dry etch, or a combination thereof.
After removing the dummy gate from the GAA device 300A and the FinFET device 300B, in some examples and in an embodiment of block 214, a channel release process is performed to the GAA device 300A, where the epitaxial layers 306 (dummy layers) in the channel region of the GAA device 300A may be selectively removed (e.g., using a selective etching process), while the epitaxial layers 308 (semiconductor channel layers) remain unetched. In embodiments, the selected epitaxial layer(s) are removed from the fins 602 through a trench provided by the removal of the dummy gate of the GAA device 300A. In some embodiments, the selective etching process may include a selective wet etching process. In some cases, the selective wet etching includes ammonia and/or ozone. As merely one example, the selective wet etching process includes tetra-methyl ammonium hydroxide (TMAH). In some embodiments, the selective etching process may include a dry, plasma-free etching process performed using a CERTAS® Gas Chemical Etch System, available from Tokyo Electron Limited, Tokyo, Japan.
It is noted that as a result of the selective removal of the epitaxial layers 306 (dummy layers), gaps 1002 are formed between the adjacent semiconductor channel layers (the epitaxial layers 308) in the channel region of the GAA device 300A, as illustrated in
The method 200 then proceeds to block 216 where a second channel doping process is performed. With reference to
As shown in
The method 200 then proceeds to block 218 where a gate structure is formed for each of the GAA device 300A and the FinFET device 300B. As described in more detail below, the gate structure may include a gate dielectric and a metal gate formed over the gate dielectric. In some embodiments, the gate structure may form the gate associated with the plurality of semiconductor channels (epitaxial layers 308) of the GAA device 300A, as well as the gate associated with the semiconductor channel provided by the epitaxial layer 402 in the channel region of the FinFET device 300B.
Referring to the example of
In some embodiments, the interfacial layer 1102 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable method. The high-K gate dielectric layer 1104 may include a high-K dielectric layer such as hafnium oxide (HfO2). Alternatively, the high-K gate dielectric layer 1104 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3 (BST), Al2O3. Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The high-K gate dielectric layer 1104 may be formed by ALD, PVD, CVD, oxidation, and/or other suitable methods.
In various examples, after deposition of the interfacial layer 1102 and/or after deposition of the high-K gate dielectric layer 1104, a post-deposition anneal (PDA) process may be performed to reduce the interface traps and oxide traps, thereby reducing flicker noise. In some embodiments, the PDA process is performed at a PDA soak temperature of between about 80-150 degrees Celsius in a nitrogen (N2) ambient for a duration of about 40-80 seconds. The PDA process may have the effect of filling oxide vacancies, thereby reducing oxide trapping centers.
In a further embodiment of block 218, a metal gate including a metal layer 1202 is formed over the gate dielectric of the GAA device 300A and over the gate dielectric of the FinFET device 300B. The metal layer 1202 may include a metal, metal alloy, or metal silicide. Additionally, the formation of the gate dielectric/metal gate stack may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials and thereby planarize a top surface of the GAA device 300A and the FinFET device 300B. In some examples, after deposition of the metal layer 1202, an optional post-metallization anneal (PMA) process may be performed to further reduce the interface traps and oxide traps, thereby reducing flicker noise.
In some embodiments, the metal layer 1202 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the metal layer 1202 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. In at least some cases, the metal layer 1202 may include a thick capping layer (e.g., such as a TiN capping layer), having a thickness of between about 10-80 Angstroms, formed over the gate dielectric to reduce oxygen absorption into the gate dielectric and reduce oxide defects, thereby also reducing flicker noise. In some examples, the thick capping layer may include a TiN capping layer with an in-situ silane pretreatment process (TiN-iSP) to form high-quality Si on the TiN capping layer, rather than potentially absorbing oxygen via a thermal process. In various embodiments, the metal layer 1202 may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the metal layer 1202 may be formed separately for N-type and P-type transistors which may use different metal layers. In various embodiments, a CMP process may be performed to remove excessive metal from the metal layer 1202, and thereby provide a substantially planar top surface of the metal layer 1202. In addition, the metal layer 1202 may provide an N-type or P-type work function, may serve as a gate electrode of the GAA device 300A and the FinFET device 300B, and in at least some embodiments, the metal layer 1202 may include a polysilicon layer. With respect to the GAA device 300A, the gate structure includes portions that interpose each of the epitaxial layers 308, which each form channels of the GAA device 300A.
It is noted that the GAA device 300 is illustrated as not including an inner spacer layer at lateral ends 1111 of the portions of the gate structure disposed between adjacent epitaxial layers 308 (e.g., as shown in
Each of the GAA device 300A and the FinFET device 300B may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 302, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method 200, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method 200.
With respect to the description provided herein, the present disclosure provides methods and structures for reducing noise (e.g., such as flicker noise) for advanced transistor structures. Generally, the disclosed embodiments may effectively reduce flicker noise by improving (reducing) the density of interface traps and oxide traps, as well as by modulating a transistor channel current path (e.g., a current path between a source and a drain of the transistor) such that the current path is a distance away from the transistor channel-to-gate dielectric interface, thereby minimizing the occurrence of charge trapping at the channel-to-gate dielectric interface. In some embodiments, the reduction of traps may be accomplished by use of PDA process and/or by use of a thick TiN capping layer to reduce oxygen absorption into the gate dielectric. In various embodiments, the current path may be moved a distance away from the transistor channel-to-gate dielectric interface by doping the transistor channel (e.g., semiconductor layer) near the channel-to-gate dielectric interface. In an example, the transistor channel may be doped using an ion implantation process, a diffusion doping process, an ALD deposition of a doped layer followed by a drive-in anneal process, a plasma doping (PLAD) process, or using another appropriate doping process. In particular, the doping process may be used to introduce a dopant species (e.g., such as an N-type dopant species, a P-type dopant species, positively charged ions, or negatively charged ions) in the semiconductor channel layer near the channel-to-gate dielectric interface that is of the same type as the transistor within which it is being introduced. As a result, and during operation, current in the transistor will flow in a bulk portion of the transistor between a source and a drain, and away from the channel-to-gate dielectric interface, such that charge trapping of carriers at the channel-to-gate dielectric interface and the associated flicker noise is reduced. Those of skill in the art will readily appreciate that the methods and structures described herein may be applied to a variety of other semiconductor devices to advantageously achieve similar benefits from such other devices without departing from the scope of the present disclosure.
Thus, one of the embodiments of the present disclosure described a method of fabricating a semiconductor device including providing a first fin extending from a substrate. In some embodiments, the method further includes forming a first gate stack over the first fin. In various examples, the method further includes forming a first doped layer along a surface of the first fin including beneath the first gate stack. In some cases, a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device.
In another of the embodiments, discussed is a method of fabricating a multi-gate semiconductor device including providing a fin extending from a substrate. In some embodiments, the fin includes a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. In some examples, the method further includes selectively removing the second epitaxial layers to form gaps between adjacent ones of the plurality of first epitaxial layers and expose surfaces of the plurality of first epitaxial layers. In some embodiments, the method further includes forming a first doped layer over the exposed surfaces of the plurality of first epitaxial layers. In some cases, the method further includes performing a drive-in anneal to cause dopants within the first doped layer to diffuse into the surfaces of the plurality of first epitaxial layers to form a second doped layer along the surfaces of the plurality of first epitaxial layers. In some examples, the method further includes after performing the drive-in anneal, removing a remaining portion of the first doped layer.
In yet another of the embodiments, discussed is a multi-gate semiconductor device including a first fin having a plurality of silicon epitaxial layers. In some embodiments, each of the plurality of silicon epitaxial layers includes a first doped layer along a surface of the silicon epitaxial layer, and the first doped layer has a first polarity type and a first dopant concentration. In some cases, the multi-gate semiconductor device further includes a first gate structure over a channel region of the first fin, where a portion of the first gate structure is disposed between adjacent layers of the plurality of silicon epitaxial layers. In some examples, the multi-gate semiconductor device further includes a first epitaxial source/drain feature adjacent to the channel region of the first fin, where the first epitaxial source/drain feature has a second polarity type the same as the first polarity type, and where the first epitaxial source/drain feature has a second dopant concentration greater than the first dopant concentration.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
