Claims
- 1. A multiplier processing system for performing a group-multiply-and-sum instruction, said system comprising:
means for partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width; means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and means for adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.
- 2. The multiplier processing system for performing a group-multiply-and-sum instruction according to claim 1, wherein the instruction comprises a fixed-point arithmetic operation.
- 3. The multiplier processing system for performing-a group-multiply-and-sum instruction according to claim 1, wherein the instruction comprises a fixed-point arithmetic operation.
- 4. The multiplier processing system for performing a group-multiply-and-sum instruction according to claim 1, further comprising:
means for including a third operand in the addition of said products.
- 5. A multiplier processing system for performing a group-multiply-sum-and-add instruction, said system comprising:
means for partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width; means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and means for adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.
- 6. The multiplier processing system for performing a group-multiply-sum-and-add instruction according to claim 5, wherein the instruction comprises a fixed-point arithmetic operation.
- 7. The multiplier processing system for performing a group-multiply-sum-and-add instruction according to claim 5, wherein the instruction comprises a fixed-point arithmetic operation.
- 8. A method for performing a group-multiply-and-sum instruction, said method comprising the steps of:
partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width; multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.
- 9. The method for performing a group-multiply-and-sum instruction according to claim 8, wherein the instruction comprises a fixed-point arithmetic operation.
- 10. The method for performing a group-multiply-and-sum instruction according to claim 8, wherein the instruction comprises a fixed-point arithmetic operation.
- 11. The method for performing a group-multiply-and-sum instruction according to claim 8, further comprising:
including a third operand in the addition of said products.
- 12. A method for performing a group-multiply-sum-and-add instruction, said method comprising the steps of:
partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width; multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.
- 13. The method for performing a group-multiply-sum-and-add instruction according to claim 12, wherein the instruction comprises a fixed-point arithmetic operation.
- 14. The method for performing a group-multiply-sum-and-add instruction according to claim 12, wherein the instruction comprises a fixed-point arithmetic operation.
RELATED APPLICATIONS
[0001] This is a continuation of Provisional Application Serial No. 60/021,132, filed on May 17, 1996, entitled MULTIPLIER ARRAY PROCESSING SYSTEM WITH ENHANCED UTILIZATION AT LOWER PRECISION, which is a continuation-in-part of U.S. patent application Ser. No. 08/516,036 filed Aug. 16, 1995.
Provisional Applications (1)
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Number |
Date |
Country |
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60021132 |
May 1996 |
US |
Continuations (2)
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Number |
Date |
Country |
Parent |
09377182 |
Aug 1999 |
US |
Child |
10418113 |
Apr 2003 |
US |
Parent |
08857596 |
May 1997 |
US |
Child |
09377182 |
Aug 1999 |
US |
Continuation in Parts (1)
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Number |
Date |
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Parent |
08516036 |
Aug 1995 |
US |
Child |
09377182 |
Aug 1999 |
US |