Patent Application
20070026575
Embodiments of the present invention relate generally to the field of circuit interconnection and, in particular, selected aspects of the present invention relate to no-flow interconnection of electronic devices.
Semiconductor chips such as processor chips are housed in chip packages, which are subsequently attached to circuit boards in the manufacture of a number of electronic devices. These devices, include personal computers, handheld computers, mobile telephones, MP3 players and other numerous information processing devices. One common configuration of input/output connections between chips, substrates, packages, and adjacent circuit boards, etc. includes grid array connection structures. In one common grid array connection structure, solder balls such as C4 connection solder structures are used to connect between grids.
There are a number of design concerns that are taken into account when forming grid arrays. High mechanical strength and reliability of the grid array connections are desirable. In a solder structure grid interconnection example, two connection surfaces with one or more solder balls in between are heated to reflow the solder and form an electrical connection. The heating process causes adjacent structures such as chips, substrates, chip packages and circuit boards to expand and contract at different rates due to differences in the coefficient of thermal expansion (CTE) in each component. The differences in CTE may cause unwanted stresses and strains in resulting products.
In the following detailed description of the invention reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, mechanical, chemical, materials choices, etc. may be made, without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
One method of providing increased mechanical strength to an interconnecting region of an electronic assembly includes introduction of an epoxy underfill layer after solder balls have already been connected between two component surfaces. In one underfill process, liquid epoxy or other curable liquid is flowed into a gap between two component surfaces and around the reflowed solder connections using capillary forces to draw the liquid into the gap. The liquid epoxy is then cured to form a more robust connection between the two component surfaces and protect the solder connections from failures such as stress cracking. Such capillary flow methods can be used between chips and substrates, or between chip packages and adjacent circuit boards, between two circuit boards, etc. One drawback of using capillary flow methods is that most of the stresses in the assembly are generated during the solder reflow step, before any stress mitigating epoxy is introduced at the interface. Another drawback of using capillary flow methods includes increased manufacturing time to both introduce the epoxy, and cure the epoxy.
No-flow processes are sometimes used in place of capillary flow methods in operations such as chip attachment to substrates.
One disadvantage of this method includes the manufacturing time and cost of individual application of each pool of epoxy. Another disadvantage of this method includes the possibility of solder balls 112 and 122 not contacting each other, leaving an electrical open. Although pressure can be used to force solder balls 112 and 122 into contact during manufacturing, a disadvantage of using force includes the possibility of solder balls 112 and 122 slipping alongside each other causing misalignment of the connection.
In one embodiment, the partially cured polymer layer 310 includes a partially cured epoxy layer. Although an epoxy layer is described, other polymer layers capable of partial curing or partial conversion from one set of mechanical properties to another are within the scope of the invention. In one embodiment, the partially cured epoxy is cured to an amount that is sufficient for tactile handling by an assembly person, or assembly robot, etc. In one embodiment, some level of flowing of the partially cured polymer layer 310 is acceptable while still maintaining an ability for tactile handling. In one embodiment, some level of flowing or other deformation helps to wet adjacent solder structures prior to a cure operation.
In one embodiment, the partially cured epoxy is cured to an amount between 70% and 100%. One of ordinary skill in the art, having the benefit of the present disclosure will recognize that an amount of partial curing is dependent upon the specific chemistry and associate properties of a given polymer or epoxy. One of ordinary skill in the art, having the benefit of the present disclosure will also recognize that the amount of partial curing can be determined without undue experimentation.
In one embodiment the number of through thickness holes is determined by a number of electrical connections in corresponding devices such as a semiconductor chip and a substrate. In one embodiment, a pattern of through thickness holes in the partially cured polymer layer 310 is formed to line up with corresponding solder structures on a semiconductor chip package. One possible number of solder structures includes an array of C4 structures. In one embodiment, alignment is facilitated for a ball grid array.
In one embodiment, to ensure contact between the chip solder structures 412 and the substrate solder structures 422, a force is applied along direction 440 during processing. Once the chip solder structures 412 and the substrate solder structures 422 are in contact, the solder is reflowed to form an electrical connection between the chip 410 and the substrate 420. In one embodiment, the electronic assembly 400 is heated to a temperature sufficient to reflow the solder. In one embodiment, the reflow operation is carried out concurrently with a further curing operation of the underfill assembly 430, thus further reducing manufacturing time.
Because no underfill material was located in holes 432 between the chip solder structures 412 and the substrate solder structures 422, the resulting reflowed solder is more likely to connect, and less likely to entrap either the chip solder structures 412 or the substrate solder structures 422 and leave an electrical open. Additionally, because no underfill material was located in holes 432 between the chip solder structures 412 and the substrate solder structures 422 little or no force is needed along direction 440 to form a reliable connection. Less force during this operation reduces the chance of misalignment due to solder structures 412, 422 being forced past each other prior to reflow.
In contrast to a pool of liquid epoxy 130 as shown in
Embodiments using the conductive plug 514 include the advantage of eliminating solder bumps on one or more connection surfaces such as the substrate or the chip. Similar to embodiments described above, the underfill assembly 500 can be mass produced, and is manufactured separately from putting together an assembly such as shown in
An example of an electronic device using semiconductor chips and underfill layers is included to show an example of a higher level device application for the present invention.
An electronic assembly 710 is coupled to system bus 702. The electronic assembly 710 can include any circuit or combination of circuits. In one embodiment, the electronic assembly 710 includes a processor 712 which can be of any type. As used herein, “processor” means any type of computational circuit, such as but not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit.
Other types of circuits that can be included in electronic assembly 710 are a custom circuit, an application-specific integrated circuit (ASIC), or the like, such as, for example, one or more circuits (such as a communications circuit 714) for use in wireless devices like mobile telephones, pagers, personal data assistants, portable computers, two-way radios, and similar electronic systems. The IC can perform any other type of function.
The electronic device 700 can also include an external memory 720, which in turn can include one or more memory elements suitable to the particular application, such as a main memory 722 in the form of random access memory (RAM), one or more hard drives 724, and/or one or more drives that handle removable media 726 such as compact disks (CD), digital video disk (DVD), and the like.
The electronic device 700 can also include a display device 716, one or more speakers 718, and a keyboard and/or controller 730, which can include a mouse, trackball, game controller, voice-recognition device, or any other device that permits a system user to input information into and receive information from the electronic device 700.
A more reliable and easier to manufacture underfill assembly is shown. One advantage of underfill layers provided above includes the ability to manufacture beforehand and pick and place the underfill layers during assembly. Another advantage of underfill layers provided above includes self aligning holes that aid in placing semiconductor chips over an appropriate location on a substrate. Another advantage of selected embodiments shown above includes pre-formed conductive plugs within an underfill layer that eliminate the need for forming solder bumps on an adjacent component surface.
Although selected advantages are detailed above, the list is not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of embodiments described above. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
