This application claims the priority benefit of Taiwan application serial no. 109123873, filed on Jul. 15, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The invention relates to a substrate structure and a manufacturing method thereof, and in particular, to a package carrier and a manufacturing method thereof.
In order to achieve a chip stacking structure, a flip chip or package-on-package (POP) circuit substrate or carrier is provided with an electroplated copper pillar structure. However, due to the necessary electroplating and build-up processes during manufacturing of the circuit board or the carrier, the coplanarity is not good, which conversely affects a height of the electroplated copper pillar structure. In other words, the surface coplanarity of the circuit substrate or the carrier with the copper pillar structure is not good. In order to solve the above-mentioned problems, before the chip is packaged on the circuit substrate or the carrier with the copper pillar structure, the copper pillar structure needs to be additionally subjected to a grinding process to improve the chip packaging yield. However, due to the need for the additional grinding process, the manufacturing process is redundant and the manufacturing cost is high.
The invention provides a package carrier, which has better flatness.
The invention provides a method for manufacturing a package carrier, which is used to manufacture the above-mentioned package carrier, thereby improving the chip packaging yield.
The package carrier of the invention includes a build-up circuit structure, a first insulation protective layer, a plurality of connection pads, and a plurality of metal balls. The build-up circuit structure has an upper surface. The first insulation protective layer is disposed on the upper surface of the build-up circuit structure and has a plurality of first openings. The connection pads are respectively disposed in the first openings of the first insulation protective layer and are structurally and electrically connected to the build-up circuit structure. Each of the connection pads has an arc-shaped groove. The metal balls are respectively disposed in the arc-shaped grooves of the connection pads. The metal balls and the corresponding connection pads respectively define a plurality of bump structures, and a plurality of top surfaces of the bump structures are on a same plane.
In an embodiment of the invention, the package carrier further includes a second insulation protective layer disposed on a lower surface of the build-up circuit structure relative to the upper surface and having a plurality of second openings, where the second openings expose a portion of the build-up circuit structure.
In an embodiment of the invention, the build-up circuit structure includes at least one dielectric layer, at least one circuit layer, and at least one conductive via. The dielectric layer covers the connection pad, the circuit layer is disposed on the dielectric layer, and the conductive via penetrates the dielectric layer to electrically connect at least one of the connection pads and the at least one circuit layer.
In an embodiment of the invention, each of the metal balls includes a copper core, a first metal layer, and a second metal layer. The first metal layer covers a surface of the copper core, and the second metal layer covers the first metal layer.
In an embodiment of the invention, the second metal layer completely covers the first metal layer, and the metal balls and the corresponding connection pads respectively define a plurality of flat bump structures.
In an embodiment of the invention, the second metal layer covers a portion of the first metal layer, and the metal balls and the corresponding connection pads respectively define a plurality of top-convex bump structures.
The method for manufacturing a package carrier of the invention includes the following steps. A substrate including a core layer, two first copper foil layers, and two second copper foil layers is provided, where the two first copper foil layers are disposed on two opposite surfaces of the core layer and are located between the core layer and the two second copper foil layers. Two photoresist layers are respectively formed on the two second copper foil layers of the substrate, where the two photoresist layers have a plurality of openings respectively, and the openings expose a portion of the two second copper foil layers. A plurality of metal balls is bonded to the two second copper foil layers exposed by the openings. Two first insulation protective layers are respectively formed on the two photoresist layers, where the two first insulation protective layers have a plurality of first openings respectively, and the first openings respectively expose the metal balls. A plurality of connection pads is formed in the first openings of the two first insulation protective layers and extending onto the two first insulation protective layers, where the connection pads respectively cover the metal balls, and there is an arc-shaped contact surface between each of the connection pads and the corresponding metal ball. Two build-up circuit structures are respectively formed on the two first insulation protective layers, where the connection pads are electrically connected to the two build-up circuit structures The substrate and the photoresist layer are removed to expose the two first insulation protective layers and the metal balls, where the metal balls and the corresponding connection pads respectively define a plurality of bump structures, and a plurality of top surfaces of the bump structures are on a same plane.
In an embodiment of the invention, the method for manufacturing the package carrier further includes after forming two build-up circuit structures respectively on the two first insulation protective layers and before removing the substrate and the photoresist layer, two second insulation protective layers are respectively formed on the two build-up circuit structures, where the two second insulation protective layers each have a plurality of second openings, and the second openings respectively expose a portion of the two build-up circuit structures.
In an embodiment of the invention, each of the metal balls includes a copper core, a first metal layer, and a second metal layer. The first metal layer covers a surface of the copper core, and the second metal layer covers the first metal layer.
In an embodiment of the invention, the second metal layer completely covers the first metal layer, and the step of removing the substrate and the photoresist layer includes: peeling off the two first copper foil layers and the two second copper foil layers of the substrate to remove the core layer and the two first copper foil layers; removing the two second copper foil layers to expose the photoresist layers and a surface of the second metal layer of each of the metal balls; and removing the photoresist layers to expose the two first insulation protective layers and the metal balls, where the metal balls and the corresponding connection pads respectively define a plurality of flat bump structures.
In an embodiment of the invention, after removing the photoresist layers, a part of the second metal layer of each of the metal balls is removed to expose a part of the first metal layer. The metal balls and the corresponding connection pads respectively define a plurality of top-convex bump structures.
Based on the above, in the design of the package carrier of the invention, the metal balls are respectively disposed in the arc-shaped groove of each of the connection pads, and the metal balls and the corresponding connection pads can define the plurality of bump structures, where the top surfaces of the bump structures are on the same plane. That is, the bump structure of the invention has better coplanarity. In this way, the package carrier of the invention can have better flatness, thereby improving a yield of subsequent chip packaging. In addition, in comparison with a conventional method for forming the copper pillar structure through electroplating and grinding process, in the method for manufacturing the package carrier of the invention, the bump structure is defined through the connection pad and the metal ball. Therefore, there is no need to perform grinding process before the chip packaging, thereby simplifying the manufacturing process and reducing the production costs.
To make the features and advantages of the invention clear and easy to understand, the following gives a detailed description of embodiments with reference to accompanying drawings.
Regarding a method for manufacturing a package carrier in the present embodiment, firstly, referring to
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Furthermore, the metal balls 110 and the corresponding connection pads 130 in the present embodiment define the flat bump structures B1, where surfaces 117 of the second metal layers 116 of the metal balls 110 are on the same plane P1. In addition, the package carrier 100a in the present embodiment further includes the second insulation protective layer 150 disposed on the lower surface 143 of the build-up circuit structure 140 relative to the upper surface 141 and having the second openings 152, where the second openings 152 expose a portion of the circuit layer 144 of the build-up circuit structure 140.
Since the flat bump structure B1 in the present embodiment includes the metal balls 110 and the corresponding connection pads 130, it means that the copper pillar structure is not formed by electroplating the copper layer, and surfaces 117 of the second metal layers 116 of the metal balls 110 are on the same plane P1. Therefore, the flat bump structure B1 in the present embodiment can have better coplanarity, so that the package carrier 100a in the present embodiment can have better flatness, thereby improving the yield of subsequent chip packaging. In addition, in the present embodiment, better flatness can be achieved without additional grinding process before the chip packaging, thereby simplifying the manufacturing process and reducing the production costs.
It should be noted herein that in the following embodiments, reference numerals and some content of the foregoing embodiments are used, and same reference numerals are used to represent same or similar elements, and descriptions about same technical content are omitted. For the omitted descriptions, reference may be made to the foregoing embodiments, and details are not repeated again in the following embodiments.
In the package carrier 100b in the present embodiment, the metal balls 110b are disposed in the arc-shaped groove C of each of the connection pads 130, and the metal balls 110b and the corresponding connection pads 130 may define the top-convex bump structures B2, where the top surfaces T of the top-convex bump structures B2 are on the same plane P2. That is, the top-convex bump structure B2 in the present embodiment may have better coplanarity. Therefore, the package carrier 100b in the present embodiment can have better flatness, thereby improving the yield of subsequent chip packaging. In addition, in the present embodiment, better flatness can be achieved without grinding process, thereby effectively simplifying the manufacturing process and reducing the production costs.
In view of the above, in the design of the package carrier of the invention, the metal balls are respectively disposed in the arc-shaped groove of each of the connection pads, and the metal balls and the corresponding connection pads can define the plurality of bump structures, where the top surfaces of the bump structures are on the same plane. That is, the bump structure of the invention has better coplanarity. In this way, the package carrier of the invention can have better flatness, thereby improving a yield of subsequent chip packaging. In addition, in comparison with a conventional method for forming the copper pillar structure through electroplating and grinding process, in the method for manufacturing the package carrier of the invention, the bump structure is defined through the connection pad and the metal ball. Therefore, there is no need to perform grinding process before the chip packaging, thereby simplifying the manufacturing process and reducing the production costs.
Although the invention is described with reference to the above embodiments, the embodiments are not intended to limit the invention. A person of ordinary skill in the art may make variations and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the invention should be subject to the appended claims.
Number | Date | Country | Kind |
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109123873 | Jul 2020 | TW | national |